verif/env/tcu/vera/include/cluster_hdr.port.vri

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: cluster_hdr.port.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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// it under the terms of the GNU General Public License as published by
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
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// along with this program; if not, write to the Free Software
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// choice is available it will apply instead, Sun elects to use only
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// ========== Copyright Header End ============================================
#ifndef INC_CLUSTER_HDR_PORT_VRI
#define INC_CLUSTER_HDR_PORT_VRI

//===============================================================
// WHAT: port declaration for clkgen modules (aka cluster headers)
//
// NAMING CONVENTION:
//   -Signals without "tag" is a Vera CLOCK.
//   -SignalNameInRtl__VeraInterfaceClock. Eg. dr_sync_en__gclk.
//
// WARNING: this file is generated by gen_cluster_hdr.pl. Do not modify.
//===============================================================

port CLKGEN_port {
  //---All signals (listed in alphabetical order). gclk is Vera CLOCK---
  //---NOTE: gclk is an always-running clock---
  aclk__gclk;
  aclk_wmr__gclk;
  array_wr_inhibit__gclk;
  bclk__gclk;
  ccu_cmp_slow_sync_en__gclk;
  ccu_div_ph__gclk;
  ccu_dr_sync_en__gclk;
  ccu_io2x_sync_en__gclk;
  ccu_serdes_dtm__gclk;
  ccu_slow_cmp_sync_en__gclk;
  clk_ext__gclk;
  cluster_arst_l__gclk;
  cluster_div_en__gclk;
  cmp_slow_sync_en__gclk;
  dr_sync_en__gclk;
  gclk;
  io2x_sync_en__gclk;
  l2clk__gclk;
  pce_ov__gclk;
  por___gclk;
  rst_por___gclk;
  rst_wmr___gclk;
  rst_wmr_protect__gclk;
  scan_en__gclk;
  scan_in__gclk;
  scan_out__gclk;
  slow_cmp_sync_en__gclk;
  tcu_aclk__gclk;
  tcu_atpg_mode__gclk;
  tcu_bclk__gclk;
  tcu_clk_stop__gclk;
  tcu_div_bypass__gclk;
  tcu_pce_ov__gclk;
  tcu_wr_inhibit__gclk;
  wmr___gclk;
  wmr_protect__gclk;
  pc_clk__gclk;
  pc_clk_sel__gclk;
  test_clk__gclk;
  test_clk_sel__gclk;

  //---output signals (listed in alphabetical order). l2clk is Vera CLOCK---
  aclk__l2clk;
  aclk_wmr__l2clk;
  array_wr_inhibit__l2clk;
  bclk__l2clk;
  cmp_slow_sync_en__l2clk;
  dr_sync_en__l2clk;
  io2x_sync_en__l2clk;
  l2clk;
  pce_ov__l2clk;
  por___l2clk;
  scan_out__l2clk;
  slow_cmp_sync_en__l2clk;
  wmr___l2clk;
  wmr_protect__l2clk;
}

#endif