verif/env/tcu/vera/include/tcu_top_defines.vri

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// OpenSPARC T2 Processor File: tcu_top_defines.vri
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#ifndef INC_TCU_TOP_DEFINES_VRI
#define INC_TCU_TOP_DEFINES_VRI

//---- common parts for all benches
//---- will separate this part and put it in a common file at the top-level
//---- (eg. :/verif/env/common/vera/include/top_defines.vri)

#define TOP     tb_top
#define CPU     `TOP.cpu        // design top module
#define TCU     `TOP.cpu.tcu    // Test control unit
#define CCU     `TOP.cpu.ccu    // Clock control unit
#define RST     `TOP.cpu.rst    // Reset logic unit
#define EFU     `TOP.cpu.efu    // Electronic fuse unit
#define NCU     `TOP.cpu.ncu    // Non-cacheable unit
#define SII     `TOP.cpu.sii    // sii unit
#define SIO     `TOP.cpu.sio    // sio unit

//---- TCU SAT specific ----

#define MONTCU  `TOP.tcu_mon    // Verilog DUT monitors
#define MONCCU  `TOP.ccu_mon    // Verilog DUT monitors
#define MONRST  `TOP.rst_mon    // Verilog DUT monitors

#define OUTPUT_EDGE_N  NHOLD
#define INPUT_EDGE   PSAMPLE
#define INPUT_SKEW   #-3

#define NUM_MBIST_ENGINES  48   // Total number of MBIST engines
#define NUM_LBIST_ENGINES  8    // Total number of LBIST engines
#define NUM_THREADS        64   // Total number of threads


#endif