// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: fbdimm_DIMMx4.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
module fbdimm_DIMMx4 (CK, bCK, CKE, bCS, bRAS, bCAS, bWE,
BA, Addr, DQ, CB, DQS, bDQS, DM_RDQS,
bRDQS, ODT, term, CS_SEL, l0state);
parameter regdel=500; // ps
input CK,bCK; // Clock Signals
input [17:0] CKE; // Clock Enable
input [17:0] bCS; // Rank/Chip Selects
input [17:0] bRAS, bCAS, bWE; // Command Inputs
input [(bank_bits-1):0] BA; // Address Inputs (Bank sel)
input [(addr_bits-1):0] Addr; // Address Inputs
inout [(data_bits-1):0] DQ; // Data Bus
inout [(dqs_bits-1):0] DQS, bDQS; // Data Strobe (bidir)
inout [(dqs_bits-1):0] DM_RDQS, bRDQS; // Data Mask
input [17:0] ODT; // On Die Termination
reg [17:0] CKE_int, bCS_int;
reg [17:0] bRAS_int, bCAS_int, bWE_int;
reg [(bank_bits-1):0] BA_int;
reg [(addr_bits-1):0] Addr_int;
bRAS_int <= #regdel bRAS;
bCAS_int <= #regdel bCAS;
Addr_int <= #regdel Addr;
end // always @ (posedge CK)
wire [17:0] CKE_int, bCS_int;
wire [17:0] bRAS_int, bCAS_int, bWE_int;
wire [(bank_bits-1):0] BA_int;
wire [(addr_bits-1):0] Addr_int;
projects / OpenSPARC-T2-DV / blob