verif/model/verilog/mem/fbdimm/design/sys_fbdimm4.v

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// OpenSPARC T2 Processor File: sys_fbdimm4.v
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module sys_fbdimm4 (   ps , ps_bar, sn , sn_bar, pn, pn_bar, ss , ss_bar , // channel interface
                       sclk);
// Parameters
parameter NB_LINK = 14;
parameter SB_LINK = 10;

// Inputs/Outputs
output  [NB_LINK-1:0] pn,pn_bar; // primary northbound
input   [NB_LINK-1:0] sn,sn_bar; // secondary northbound
output  [SB_LINK-1:0] ss,ss_bar; // secondary southbound
input   [SB_LINK-1:0] ps,ps_bar; // primary southbound
input                sclk;

// internal registers/wires
wire [NB_LINK-1:0] fbdimm0_sn,fbdimm1_sn,fbdimm2_sn,fbdimm3_sn;
wire [SB_LINK-1:0] fbdimm0_ss,fbdimm1_ss,fbdimm2_ss,fbdimm3_ss;

fbdimm #(NB_LINK,SB_LINK,0) fbdimm0 ( .ps   (ps),
                                      .sn   (fbdimm0_sn),
                                      .pn   (pn),
                                      .ss   (fbdimm0_ss),
                                      .sclk (sclk));

fbdimm #(NB_LINK,SB_LINK,1) fbdimm1 ( .ps   (fbdimm0_ss),
                                      .sn   (fbdimm1_sn),
                                      .pn   (fbdimm0_sn),
                                      .ss   (fbdimm1_ss),
                                      .sclk (sclk));

fbdimm #(NB_LINK,SB_LINK,2) fbdimm2 ( .ps   (fbdimm1_ss),
                                      .sn   (fbdimm2_sn),
                                      .pn   (fbdimm1_sn),
                                      .ss   (fbdimm2_ss),
                                      .sclk (sclk));

fbdimm #(NB_LINK,SB_LINK,3) fbdimm3 ( .ps   (fbdimm2_ss),
                                      .sn   (fbdimm3_sn),
                                      .pn   (fbdimm2_sn),
                                      .ss   (fbdimm3_ss),
                                      .sclk (sclk));


endmodule