verif/model/verilog/mem/fbdimm/library/fifo/sync_w2r.v

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// OpenSPARC T2 Processor File: sync_w2r.v
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module sync_w2r (rwptr2,wptr,rclk,rrst_n);
parameter ADDRSIZE=6;
output [ADDRSIZE:0] rwptr2;
input  [ADDRSIZE:0] wptr;
input              rclk,rrst_n;
reg [ADDRSIZE:0] rwptr2,rwptr1;

always @(posedge rclk or negedge rrst_n)
  if ( !rrst_n)
   begin
    rwptr1 <= 1'b0;
    rwptr2 <= 1'b0;
   end
  else
   begin
    {rwptr2,rwptr1 }<= {rwptr1,wptr};
   end
endmodule