Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / common / include / config.h
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1/*
2* ========== Copyright Header Begin ==========================================
3*
4* Hypervisor Software File: config.h
5*
6* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
7*
8* - Do no alter or remove copyright notices
9*
10* - Redistribution and use of this software in source and binary forms, with
11* or without modification, are permitted provided that the following
12* conditions are met:
13*
14* - Redistribution of source code must retain the above copyright notice,
15* this list of conditions and the following disclaimer.
16*
17* - Redistribution in binary form must reproduce the above copyright notice,
18* this list of conditions and the following disclaimer in the
19* documentation and/or other materials provided with the distribution.
20*
21* Neither the name of Sun Microsystems, Inc. or the names of contributors
22* may be used to endorse or promote products derived from this software
23* without specific prior written permission.
24*
25* This software is provided "AS IS," without a warranty of any kind.
26* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
27* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
28* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
29* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
30* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
31* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
32* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
33* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
34* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
35* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
36* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
37*
38* You acknowledge that this software is not designed, licensed or
39* intended for use in the design, construction, operation or maintenance of
40* any nuclear facility.
41*
42* ========== Copyright Header End ============================================
43*/
44/*
45 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
46 * Use is subject to license terms.
47 */
48
49#ifndef _CONFIG_H
50#define _CONFIG_H
51
52#pragma ident "@(#)config.h 1.39 07/07/18 SMI"
53
54#ifdef __cplusplus
55extern "C" {
56#endif
57
58#include <svc_vbsc.h> /* dbgerror */
59#include <platform/config.h>
60
61#define NGUESTS NSTRANDS
62#define NVCPUS NGUESTS /* 1 per guest */
63
64#define DUMPBUF_MINSIZE 8192 /* smallest dump buffer allowed */
65#define HVCTL_BUF_SIZE 8 /* HVCTL ibuf and obuf size */
66
67/*
68 * cpu_pokedelay - the number of ticks between pokes to a target
69 * cpu that has had a mondo outstanding. The target's cpu queue
70 * may have been full and it needs a poke to check it again.
71 */
72#define CPU_POKEDELAY 2000 /* clock ticks */
73
74/*
75 * memscrub_max default - used as the default if the memscrub_max
76 * was not specified in the hypervisor description or if the
77 * setting does not correspond to an 8k-aligned byte count.
78 */
79#define MEMSCRUB_MAX_DEFAULT ((4LL * 1024LL * 1024LL) >> L2_LINE_SHIFT)
80
81/*
82 * Dummy TSB to fake up real address space.
83 */
84#define DUMMYTSB_ENTRIES (DUMMYTSB_SIZE/16)
85#define DUMMYTSB_SIZE 0x2000
86#define DUMMYTSB_ALIGN DUMMYTSB_SIZE
87
88/*
89 * Hypervisor MD content-version. We start with 1.0.
90 * If the property is not present in the MD we assume pre 1.0.
91 * Pre 1.0 MDs are not supported by this hypervisor.
92 * The hypervisor will support MDs in the same major version number.
93 * Minor version numbers less than the version specified below require
94 * the hypervisor to be backward compatible. Minor versions above can be
95 * ignored as the version is only incremented on content additions. Removing
96 * content requires a Major version bump.
97 */
98#define HV_MDCONT_VER_MAJOR 1
99#define HV_MDCONT_VER_MINOR 0
100
101/*
102 * Extract major and minor numbers. The property is encoded as an uint64_t.
103 * Where:
104 * Top 32 bits = major version number
105 * Bottom 32 bits = minor version number
106 */
107#define MDCONT_VER_MAJOR(x) (x >> 32)
108#define MDCONT_VER_MINOR(x) ((x << 32) >> 32)
109
110#ifndef _ASM
111
112struct nametable {
113 uint64_t hdname_root;
114 uint64_t hdname_fwd;
115 uint64_t hdname_back;
116 uint64_t hdname_id;
117 uint64_t hdname_cpus;
118 uint64_t hdname_cpu;
119 uint64_t hdname_devices;
120 uint64_t hdname_device;
121 uint64_t hdname_services;
122 uint64_t hdname_service;
123 uint64_t hdname_guests;
124 uint64_t hdname_guest;
125#ifdef CONFIG_CRYPTO
126 uint64_t hdname_mau;
127 uint64_t hdname_maus;
128 uint64_t hdname_cwq;
129 uint64_t hdname_cwqs;
130#endif /* CONFIG_CRYPTO */
131 uint64_t hdname_romsize;
132 uint64_t hdname_rombase;
133 uint64_t hdname_memory;
134 uint64_t hdname_mblock;
135 uint64_t hdname_unbind;
136 uint64_t hdname_mdpa;
137 uint64_t hdname_size;
138 uint64_t hdname_uartbase;
139 uint64_t hdname_base;
140 uint64_t hdname_link;
141 uint64_t hdname_inobitmap;
142 uint64_t hdname_tod;
143 uint64_t hdname_todfrequency;
144 uint64_t hdname_todoffset;
145 uint64_t hdname_vid;
146 uint64_t hdname_xid;
147 uint64_t hdname_pid;
148 uint64_t hdname_sid;
149 uint64_t hdname_gid;
150 uint64_t hdname_strandid;
151 uint64_t hdname_parttag;
152 uint64_t hdname_ign;
153 uint64_t hdname_ino;
154 uint64_t hdname_mtu;
155 uint64_t hdname_memoffset;
156 uint64_t hdname_memsize;
157 uint64_t hdname_membase;
158 uint64_t hdname_realbase;
159 uint64_t hdname_hypervisor;
160 uint64_t hdname_perfctraccess;
161 uint64_t hdname_perfctrhtaccess;
162 uint64_t hdname_rngctlaccessible;
163 uint64_t hdname_vpcidevice;
164 uint64_t hdname_pciregs;
165 uint64_t hdname_cfghandle;
166 uint64_t hdname_cfgbase;
167 uint64_t hdname_diskpa;
168#ifdef T1_FPGA_SNET
169 uint64_t hdname_snet;
170 uint64_t hdname_snet_pa;
171 uint64_t hdname_snet_ino;
172#endif
173 uint64_t hdname_diagpriv;
174 uint64_t hdname_debugprintflags;
175 uint64_t hdname_iobase;
176 uint64_t hdname_hvuart;
177 uint64_t hdname_flags;
178 uint64_t hdname_stickfrequency;
179 uint64_t hdname_ceblackoutsec;
180 uint64_t hdname_cepollsec;
181 uint64_t hdname_memscrubmax;
182 uint64_t hdname_erpt_pa;
183 uint64_t hdname_erpt_size;
184 uint64_t hdname_vdevs;
185 uint64_t hdname_reset_reason;
186 uint64_t hdname_ldc_endpoints;
187 uint64_t hdname_sp_ldc_endpoints;
188 uint64_t hdname_ldc_endpoint;
189 uint64_t hdname_channel;
190 uint64_t hdname_target_type;
191 uint64_t hdname_target_guest;
192 uint64_t hdname_target_channel;
193 uint64_t hdname_tx_ino;
194 uint64_t hdname_rx_ino;
195 uint64_t hdname_svc_id;
196 uint64_t hdname_svc_arg;
197 uint64_t hdname_svc_vino;
198 uint64_t hdname_private_svc;
199 uint64_t hdname_ldc_mapinrabase;
200 uint64_t hdname_ldc_mapinsize;
201#ifdef CONFIG_SPLIT_SRAM /* { */
202 uint64_t hdname_sram_ptrs;
203 uint64_t hdname_inq_offset;
204 uint64_t hdname_inq_data_offset;
205 uint64_t hdname_inq_num_pkts;
206 uint64_t hdname_outq_offset;
207 uint64_t hdname_outq_data_offset;
208 uint64_t hdname_outq_num_pkts;
209#endif /* { */
210 uint64_t hdname_idx;
211 uint64_t hdname_resource_id;
212 uint64_t hdname_consoles;
213 uint64_t hdname_console;
214 uint64_t hdname_virtual_devices;
215 uint64_t hdname_channel_devices;
216 uint64_t hdname_sys_hwtw_mode;
217#ifdef CONFIG_PCIE
218 uint64_t hdname_pcie_bus;
219 uint64_t hdname_allow_bypass;
220#endif
221#ifdef STANDALONE_NET_DEVICES
222 uint64_t hdname_network_device;
223#endif
224#ifdef CONFIG_CLEANSER
225 uint64_t hdname_l2scrub_interval;
226 uint64_t hdname_l2scrub_entries;
227#endif
228#ifdef PLX_ERRATUM_LINK_HACK
229 uint64_t hdname_ignore_plx_link_hack;
230#endif
231 uint64_t hdname_content_version;
232};
233
234struct erpt_svc_pkt {
235 uint64_t addr;
236 uint64_t size;
237};
238
239
240/*
241 * Global configuration
242 */
243
244typedef struct config config_t;
245
246struct config {
247 uint64_t membase; /* original membase value */
248 uint64_t memsize; /* original memsize value */
249
250 /* HV state as reflected by a HV MD */
251 void *active_hvmd; /* active hypervisor MD */
252 void *parse_hvmd; /* hypervisor MD being parsed */
253
254 uint64_t reloc; /* hv relocation offset */
255
256 void *guests; /* pointer to base of guests array */
257 void *mblocks; /* pointer to base of mblocks array */
258 void *vcpus; /* pointer to base of vcpus array */
259 void *strands; /* pointer to base of strands array */
260 void *vstate; /* pointer to base of vstate array */
261#ifdef CONFIG_LDC_BRIDGE
262 uint64_t ldcb_pa; /* Bridge base address */
263#endif
264#ifdef CONFIG_PCIE
265 void *pcie_busses; /* pcie busses */
266#endif
267#ifdef STANDALONE_NET_DEVICES
268 void *network_devices; /* network devices */
269#endif
270 void *hv_ldcs; /* ptr to array of HV LDC endpoints */
271 void *sp_ldcs; /* ptr to array of SP LDC endpoints */
272 uint64_t sp_ldc_max_cid;
273
274 void *dummytsbp; /* pointer to dummy tsb */
275
276 /*
277 * lock to ensure that only one strand executes
278 */
279 uint64_t single_strand_lock;
280
281 uint64_t strand_startset;
282 uint64_t strand_present; /* strand state information */
283 uint64_t strand_active;
284 uint64_t strand_idle;
285 uint64_t strand_halt;
286
287 uint64_t print_spinlock; /* print output serialization */
288
289 uint64_t heartbeat_cpu; /* physical cpu# of heartbeat handler */
290
291 uint64_t error_svch; /* hypervisor error service handle */
292
293#ifdef CONFIG_VBSC_SVC
294 uint64_t vbsc_svch;
295 struct dbgerror vbsc_dbgerror;
296#endif
297
298 struct hv_svc_data *svc;
299 struct vintr_dev *vintr;
300
301 uint64_t hvuart_addr;
302 uint64_t tod;
303 uint64_t todfrequency;
304 uint64_t stickfrequency;
305
306 uint64_t sys_hwtw_mode; /* MMU HWTW Mode */
307
308 uint64_t erpt_pa; /* address of erpt buffer */
309 uint64_t erpt_size; /* size */
310 uint64_t sram_erpt_buf_inuse;
311 /*
312 * Cached hypervisor description nodes
313 */
314 void *root_dtnode;
315 void *devs_dtnode;
316 void *svcs_dtnode;
317 void *guests_dtnode;
318 void *cpus_dtnode;
319 void *hv_ldcs_dtnode;
320 void *sp_ldcs_dtnode;
321#ifdef CONFIG_LDC_BRIDGE
322 void ldcb_dtnode; /* FIXME: To go away */
323#endif
324
325 /*
326 * error log lock
327 */
328 uint64_t error_lock;
329
330 /*
331 * Name to nameindex translation table for hypervisor description
332 */
333 struct nametable hdnametable;
334
335 uint64_t intrtgt; /* SSI interrupt targets */
336
337 /*
338 * hcall memory scrub and sync limit
339 *
340 * It's a cacheline count, not byte count, and must correspond to
341 * a byte count multiple of 8k.
342 */
343 uint64_t memscrub_max;
344
345 /* devinst */ void *devinstancesp;
346
347 /*
348 * cyclic timers
349 */
350 uint64_t cyclic_maxd; /* max delay in ticks */
351
352 /*
353 * HVCTL (hypervisor control) messaging storage
354 */
355 uint8_t hvctl_state;
356 uint16_t hvctl_hv_seq; /* HV's next seqn */
357 uint16_t hvctl_zeus_seq; /* Zeus ' next seqn */
358 uint16_t hvctl_version_major;
359 uint16_t hvctl_version_minor;
360 uint64_t hvctl_rand_num;
361 uint64_t hvctl_ibuf[HVCTL_BUF_SIZE];
362 uint64_t hvctl_obuf[HVCTL_BUF_SIZE];
363
364 /*
365 * HVCTL state
366 */
367 uint64_t hvctl_ip;
368 uint64_t hvctl_ldc; /* HV LDC endpoint number */
369 volatile uint64_t hvctl_ldc_lock; /* serializes HV LDC sends */
370
371 /*
372 * CE Storm Prevention
373 */
374 uint64_t ce_blackout; /* ticks */
375 uint64_t ce_poll_time; /* poll time in ticks */
376
377 /*
378 * Error buffers still needed to be sent
379 */
380 uint64_t errs_to_send;
381
382 uint64_t physmemsize; /* Total phys memory size */
383
384 /*
385 * Delayed reconfiguration
386 */
387 uint64_t del_reconf_gid; /* ID of delayed reconfig guest */
388 volatile uint64_t del_reconf_lock; /* protects delayed reconfig */
389
390 /*
391 * Scratch used at beginning of time for scrubbing.
392 * Could be overloaded with other fields.
393 */
394 uint64_t scrub_sync;
395 uint64_t fpga_status_lock;
396
397#ifdef CONFIG_CLEANSER
398 /*
399 * Interval (in seconds) for invoking the L2 Cache Cleanser
400 */
401 uint64_t l2scrub_interval;
402 /*
403 * Number of L2 cache entries to be scrubbed on each invocation
404 * as a percentage of the total number of entries (64k)
405 */
406 uint64_t l2scrub_entries;
407#endif /* CONFIG_CLEANSER */
408
409#ifdef PLX_ERRATUM_LINK_HACK
410 /*
411 * Global setting to ignore the PLX link training reset hack
412 * in case the system gets in an never-ending reset loop.
413 */
414 uint64_t ignore_plx_link_hack;
415#endif /* PLX_ERRATUM_LINK_HACK */
416
417 struct machconfig config_m;
418};
419
420extern config_t config;
421
422#endif /* !_ASM */
423
424/*
425 * The intrtgt property is a byte array of physical cpuids for the SSI
426 * interrupt targets (INT_MAN devices 1 and 2)
427 */
428#define INTRTGT_CPUMASK 0xff /* Mask for a single array element */
429#define INTRTGT_DEVSHIFT 8 /* #bits for each entry in array */
430
431/*
432 * The reset-reason property provided by VBSC
433 */
434#define RESET_REASON_POR 0
435#define RESET_REASON_SIR 1
436
437/*
438 * Watchdog timeout limits
439 */
440#define MSEC_PER_SEC 1000
441#define WATCHDOG_MAX_TIMEOUT (365 * 24 * 60 * 60) /* roughly a year */
442
443#ifdef __cplusplus
444}
445#endif
446
447#endif /* _CONFIG_H */