[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / huron / dumbreset / reset.s

/*
* ========== Copyright Header Begin ==========================================
*
* Hypervisor Software File: reset.s
* 
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* 
*  - Do no alter or remove copyright notices
* 
*  - Redistribution and use of this software in source and binary forms, with 
*    or without modification, are permitted provided that the following 
*    conditions are met: 
* 
*  - Redistribution of source code must retain the above copyright notice, 
*    this list of conditions and the following disclaimer.
* 
*  - Redistribution in binary form must reproduce the above copyright notice,
*    this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution. 
* 
*    Neither the name of Sun Microsystems, Inc. or the names of contributors 
* may be used to endorse or promote products derived from this software 
* without specific prior written permission. 
* 
*     This software is provided "AS IS," without a warranty of any kind. 
* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, 
* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN 
* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR 
* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR 
* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN 
* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR 
* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE 
* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, 
* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF 
* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* 
* You acknowledge that this software is not designed, licensed or
* intended for use in the design, construction, operation or maintenance of
* any nuclear facility. 
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#pragma ident	"@(#)reset.s	1.2	07/09/20 SMI"

/*
 * dumbreset - a minimal Niagara reset sequence with the same
 * hypervisor invocation as the real reset/config.  This is useful
 * when running the hypervisor with Legion, Simics, RTL simulation,
 * Axis, etc.
 */

#include <sys/asm_linkage.h>
#include <sparcv9/asi.h>
#include <hprivregs.h>
#include <sun4v/traps.h>
#include <asi.h>
#include <cache.h>
#include <dram.h>
#include <config.h>
		
#define	MEMBASE		(4 * 1024 * 1024)
#define	MEMSIZE		(60 * 1024 * 1024)
#define	LOCK_ADDR	(MEMBASE + MEMSIZE - 16)
#define	LOCK_SIZE	64
#define	HVPD		0x180000
#define	HV_IN_ROM	0xfff0010000
#define	HV_IN_RAM	0x0000100000

#ifdef AXIS
#define	HV		HV_IN_RAM
#else
#define	HV		HV_IN_ROM
#endif

#define	SET_MCU_REG(_reg, _val, _scr1, _scr2) \
	setx	_reg, _scr1, _scr2		;\
	set	_val, _scr1			;\
	stx	_scr1, [_scr2]

#define	SET_MCU(_scr1, _scr2, _bank) \
	SET_MCU_REG((DRAM_BASE + (_bank*DRAM_BANK_STEP) + DRAM_DIMM_INIT_REG), 0x0, _scr1, _scr2)		;\
	SET_MCU_REG((DRAM_BASE + (_bank*DRAM_BANK_STEP) + DRAM_SEL_LO_ADDR_BITS_REG), 0x0, _scr1, _scr2)	;\
	SET_MCU_REG((DRAM_BASE + (_bank*DRAM_BANK_STEP) + DRAM_DIMM_STACK_REG), 0x0, _scr1, _scr2)		;\
	SET_MCU_REG((DRAM_BASE + (_bank*DRAM_BANK_STEP) + DRAM_FBD_CHNL_RESET), 0x1, _scr1, _scr2)

/*
 * Niagara reset trap tables
 */

#define	TRAP_ALIGN_SIZE		32
#define	TRAP_ALIGN		.align TRAP_ALIGN_SIZE
#define	TRAP_ALIGN_BIG		.align (TRAP_ALIGN_SIZE * 4)

#define	TT_TRACE(label)
#define	TT_TRACE_L(label)

#define	TRAP(ttnum, action) \
	.global	r/**/ttnum	;\
	r/**/ttnum:		;\
	action			;\
	TRAP_ALIGN

#define	BIGTRAP(ttnum, action) \
	.global	r/**/ttnum	;\
	r/**/ttnum:		;\
	action			;\
	TRAP_ALIGN_BIG

#define	GOTO(label)		\
	TT_TRACE(trace_gen)	;\
	.global	label		;\
	ba,a	label		;\
	.empty

/* revector to hypervisor */
#define	HREVEC(ttnum)		\
	TT_TRACE(trace_gen)	;\
	mov	ttnum, %g1	;\
	ba,a	revec		;\
	.empty
	

#define	NOT	GOTO(rtrap)
#define	NOT_BIG	NOT NOT NOT NOT
#define	RED	NOT
#define	SAVE_RESTORE	.xword 0x0

/*
 * The basic hypervisor trap table
 */

	.section ".text"
	.align	0x8000
	.global	rtraptable
	.type	rtraptable, #function
rtraptable:
	/* hardware traps */
	TRAP(tt0_000, NOT)		/* reserved */
	TRAP(tt0_001, GOTO(start_reset)) /* power-on reset */
	TRAP(tt0_002, HREVEC(0x2))	/* watchdog reset */
	TRAP(tt0_003, HREVEC(0x3))	/* externally initiated reset */
	TRAP(tt0_004, NOT)		/* software initiated reset */
	TRAP(tt0_005, NOT)		/* red mode exception */
	TRAP(tt0_006, NOT)		/* reserved */
	TRAP(tt0_007, NOT)		/* reserved */
ertraptable:
	.size	rtraptable, (.-rtraptable)
	.global	rtraptable
	.type	rtraptable, #function

	/* 
	 * The section below is for save-restore(checkpointing from Legion to AXIS/Palladium.
	 * In normal runs, when dumbreset is done, it hands off to hv. On a saved and restored
	 * run, it needs to handoff to the restore code. So, during a save, Legion patches in
	 * a non-zero value into this location.
	 */
	.align	0x200
	.section ".text"
	.global save_restore
save_restore:
	SAVE_RESTORE
	.size	save_restore, (.-save_restore)

	ENTRY_NP(start_reset)
	wrpr	%g0, 1, %gl
	wrpr	%g0, 1, %tl
	wrpr	%g0, 0, %cwp

	! set ENB bit
	set	HPSTATE_ENB, %g1
	rdhpr	%hpstate, %g2
	or	%g1, %g2, %g1
	wrhpr	%g1, %hpstate

	set	(LSUCR_DC | LSUCR_IC), %g1
	stxa	%g1, [%g0]ASI_LSUCR

	set	((PSTATE_PRIV | PSTATE_MM_TSO) << TSTATE_PSTATE_SHIFT), %g2
	wrpr	%g2, %pstate	! gl=0 ccr=0 asi=0
	! before exiting RED state, setup htba
	setx	0xfff0000000, %g3, %g2	! XXXQ correct value?
	wrhpr	%g2, %htba
	set	(HPSTATE_HPRIV | HPSTATE_ENB), %g2
	wrhpr	%g2, %hpstate


	mov	CMP_CORE_ID, %g1;
	ldxa	[%g1]ASI_CMP_CORE, %g1;
	andcc	%g1, NSTRANDS - 1, %g0;
	bnz	bypass_mcu_init;
	nop;

	SET_MCU(%g1, %g2, 0)
	SET_MCU(%g1, %g2, 1)
	SET_MCU(%g1, %g2, 2)
	SET_MCU(%g1, %g2, 3)

bypass_mcu_init:
	
	mov	CMP_CORE_ENABLE_STATUS, %g6
	ldxa    [%g6]ASI_CMP_CHIP, %g6    	! get enabled cores

	! find lowest bit set (the 1st nonzero bit) in asi_core_enable	
	clr	%g2				! %g2: initial bit to start btst
	mov	1, %g3				! %g3: bit mask of selected bit
1:
	inc	%g2				! 
	btst	%g3, %g6			! perform btst on bits 0,1,...,x 
	bz,a,pt %xcc, 1b			! until asi_core_enable[x]=1.
	sllx	%g3, 1, %g3			!
	dec	%g2				! 

	mov	CMP_CORE_ID, %g1
	ldxa	[%g1]ASI_CMP_CORE, %g1		! get virtual core id
	and	%g1, 0x3f, %g1			! %g1 - current core id

	! sync up tick regs in all enabled cores with bit masks set to LOCK_ADDR
	wrpr	%g0, %tick
	setx	LOCK_ADDR, %g4, %g3		! the initial mask value is zero
	mov	1, %g5				! set bit mask
	sllx	%g5, %g1, %g5			! (e.g., bit[i]=1 if %g1=i)
2:	
	ldx	[%g3], %g4			! get the old mask
	or	%g4, %g5, %g7			! set the new mask 
	casx	[%g3], %g4, %g7			! try to update [LOCK_ADDR] with 
	cmp	%g4, %g7			!  the new mask
	bne	2b				! try again if update failed 
	nop
	
	! branch out as master or slave (the lowest core becomes master)
	cmp	%g2, %g1
	be,pt	%xcc, .master_entry
	nop

.slave_entry:
	/*
	 * Slave
	 */
	setx	MEMBASE, %g4, %g1 ! Mem base XXX
	setx	MEMSIZE, %g4, %g2 ! Mem size XXX
	setx	HVPD, %g4, %g3	! Partition Description

	setx	save_restore, %g5, %g4	! are we running a checkpointed image?
	ldx	[%g4], %g4
	brnz,pn	%g4, 4f			! yes, then jump to SR code
	nop

	setx	HV, %g5, %g4
	jmp	%g4 + 0x30
	nop
4:
	jmp	%g4 + 0x20
	nop

.master_entry:
	/*
	 * Master
	 */
	mov     CMP_TICK_ENABLE, %g4
	mov     1, %g5
	stxa    %g5, [%g4]ASI_CMP_CHIP
	
	setx	L2_CONTROL_REG, %g2, %g1	! enable L2$ and scrubbing
	setx	L2_SCRUBENABLE | (1<<L2_SCRUBINTERVAL_SHIFT), %g3, %g2
	stx	%g2, [%g1]
	stx	%g2, [%g1 + 0x040]
	stx	%g2, [%g1 + 0x080]
	stx     %g2, [%g1 + 0x0c0]
	stx     %g2, [%g1 + 0x100]
	stx     %g2, [%g1 + 0x140]
	stx     %g2, [%g1 + 0x180]
	stx     %g2, [%g1 + 0x1c0]

	setx	MEMBASE, %g4, %g1 ! Mem base XXX
	setx	MEMSIZE, %g4, %g2 ! Mem size XXX
	setx	HVPD, %g4, %g3	! Partition Description

	mov	CMP_CORE_ENABLE_STATUS, %g6
	ldxa    [%g6]ASI_CMP_CHIP, %g6    	! get enabled cores

	setx	save_restore, %g5, %g4	! are we running a checkpointed image?
	ldx	[%g4], %g4
	brnz,pn	%g4, 5f			! yes, then jump to SR code
	nop

	setx	HV, %g5, %g4
5:	
	jmp	%g4 + 0x20
	mov	%g6, %g4		! %g4:  CPU start set

	SET_SIZE(start_reset)

	ENTRY_NP(rtrap)
	ta	0x1
	SET_SIZE(rtrap)

	! %g1 contains trap# to revector to 
	ENTRY_NP(revec)
	rdhpr	%htba, %g2
	sllx	%g1, 5, %g1
	add	%g2, %g1, %g2
	jmp	%g2
	wrhpr	%g0, (HPSTATE_HPRIV | HPSTATE_ENB), %hpstate
	SET_SIZE(revec)

	!! KEEP THIS AT THE END
	.align	0x100
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* Hypervisor Software File: reset.s
	5	*
	6	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	7	*
	8	* - Do no alter or remove copyright notices
	9	*
	10	* - Redistribution and use of this software in source and binary forms, with
	11	* or without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistribution of source code must retain the above copyright notice,
	15	* this list of conditions and the following disclaimer.
	16	*
	17	* - Redistribution in binary form must reproduce the above copyright notice,
	18	* this list of conditions and the following disclaimer in the
	19	* documentation and/or other materials provided with the distribution.
	20	*
	21	* Neither the name of Sun Microsystems, Inc. or the names of contributors
	22	* may be used to endorse or promote products derived from this software
	23	* without specific prior written permission.
	24	*
	25	* This software is provided "AS IS," without a warranty of any kind.
	26	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
	27	* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
	28	* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
	29	* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
	30	* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
	31	* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
	32	* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
	33	* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
	34	* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
	35	* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
	36	* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
	37	*
	38	* You acknowledge that this software is not designed, licensed or
	39	* intended for use in the design, construction, operation or maintenance of
	40	* any nuclear facility.
	41	*
	42	* ========== Copyright Header End ============================================
	43	*/
	44	/*
	45	* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
	46	* Use is subject to license terms.
	47	*/
	48
	49	#pragma ident "@(#)reset.s 1.2 07/09/20 SMI"
	50
	51	/*
	52	* dumbreset - a minimal Niagara reset sequence with the same
	53	* hypervisor invocation as the real reset/config. This is useful
	54	* when running the hypervisor with Legion, Simics, RTL simulation,
	55	* Axis, etc.
	56	*/
	57
	58	#include <sys/asm_linkage.h>
	59	#include <sparcv9/asi.h>
	60	#include <hprivregs.h>
	61	#include <sun4v/traps.h>
	62	#include <asi.h>
	63	#include <cache.h>
	64	#include <dram.h>
65	#include <config.h>
66
67	#define MEMBASE (4 * 1024 * 1024)
68	#define MEMSIZE (60 * 1024 * 1024)
69	#define LOCK_ADDR (MEMBASE + MEMSIZE - 16)
70	#define LOCK_SIZE 64
71	#define HVPD 0x180000
72	#define HV_IN_ROM 0xfff0010000
73	#define HV_IN_RAM 0x0000100000
74
75	#ifdef AXIS
76	#define HV HV_IN_RAM
77	#else
78	#define HV HV_IN_ROM
79	#endif
80
81	#define SET_MCU_REG(_reg, _val, _scr1, _scr2) \
82	setx _reg, _scr1, _scr2 ;\
83	set _val, _scr1 ;\
84	stx _scr1, [_scr2]
85
86	#define SET_MCU(_scr1, _scr2, _bank) \
87	SET_MCU_REG((DRAM_BASE + (_bank*DRAM_BANK_STEP) + DRAM_DIMM_INIT_REG), 0x0, _scr1, _scr2) ;\
88	SET_MCU_REG((DRAM_BASE + (_bank*DRAM_BANK_STEP) + DRAM_SEL_LO_ADDR_BITS_REG), 0x0, _scr1, _scr2) ;\
89	SET_MCU_REG((DRAM_BASE + (_bank*DRAM_BANK_STEP) + DRAM_DIMM_STACK_REG), 0x0, _scr1, _scr2) ;\
90	SET_MCU_REG((DRAM_BASE + (_bank*DRAM_BANK_STEP) + DRAM_FBD_CHNL_RESET), 0x1, _scr1, _scr2)
91
92	/*
93	* Niagara reset trap tables
94	*/
95
96	#define TRAP_ALIGN_SIZE 32
97	#define TRAP_ALIGN .align TRAP_ALIGN_SIZE
98	#define TRAP_ALIGN_BIG .align (TRAP_ALIGN_SIZE * 4)
99
100	#define TT_TRACE(label)
101	#define TT_TRACE_L(label)
102
103	#define TRAP(ttnum, action) \
104	.global r/**/ttnum ;\
105	r/**/ttnum: ;\
106	action ;\
107	TRAP_ALIGN
108
109	#define BIGTRAP(ttnum, action) \
110	.global r/**/ttnum ;\
111	r/**/ttnum: ;\
112	action ;\
113	TRAP_ALIGN_BIG
114
115	#define GOTO(label) \
116	TT_TRACE(trace_gen) ;\
117	.global label ;\
118	ba,a label ;\
119	.empty
120
121	/* revector to hypervisor */
122	#define HREVEC(ttnum) \
123	TT_TRACE(trace_gen) ;\
124	mov ttnum, %g1 ;\
125	ba,a revec ;\
126	.empty
127
128
129	#define NOT GOTO(rtrap)
130	#define NOT_BIG NOT NOT NOT NOT
131	#define RED NOT
132	#define SAVE_RESTORE .xword 0x0
133
134	/*
135	* The basic hypervisor trap table
136	*/
137
138	.section ".text"
139	.align 0x8000
140	.global rtraptable
141	.type rtraptable, #function
142	rtraptable:
143	/* hardware traps */
144	TRAP(tt0_000, NOT) /* reserved */
145	TRAP(tt0_001, GOTO(start_reset)) /* power-on reset */
146	TRAP(tt0_002, HREVEC(0x2)) /* watchdog reset */
147	TRAP(tt0_003, HREVEC(0x3)) /* externally initiated reset */
148	TRAP(tt0_004, NOT) /* software initiated reset */
149	TRAP(tt0_005, NOT) /* red mode exception */
150	TRAP(tt0_006, NOT) /* reserved */
151	TRAP(tt0_007, NOT) /* reserved */
152	ertraptable:
153	.size rtraptable, (.-rtraptable)
154	.global rtraptable
155	.type rtraptable, #function
156
157	/*
158	* The section below is for save-restore(checkpointing from Legion to AXIS/Palladium.
159	* In normal runs, when dumbreset is done, it hands off to hv. On a saved and restored
160	* run, it needs to handoff to the restore code. So, during a save, Legion patches in
161	* a non-zero value into this location.
162	*/
163	.align 0x200
164	.section ".text"
165	.global save_restore
166	save_restore:
167	SAVE_RESTORE
168	.size save_restore, (.-save_restore)
169
170	ENTRY_NP(start_reset)
171	wrpr %g0, 1, %gl
172	wrpr %g0, 1, %tl
173	wrpr %g0, 0, %cwp
174
175	! set ENB bit
176	set HPSTATE_ENB, %g1
177	rdhpr %hpstate, %g2
178	or %g1, %g2, %g1
179	wrhpr %g1, %hpstate
180
181	set (LSUCR_DC \| LSUCR_IC), %g1
182	stxa %g1, [%g0]ASI_LSUCR
183
184	set ((PSTATE_PRIV \| PSTATE_MM_TSO) << TSTATE_PSTATE_SHIFT), %g2
185	wrpr %g2, %pstate ! gl=0 ccr=0 asi=0
186	! before exiting RED state, setup htba
187	setx 0xfff0000000, %g3, %g2 ! XXXQ correct value?
188	wrhpr %g2, %htba
189	set (HPSTATE_HPRIV \| HPSTATE_ENB), %g2
190	wrhpr %g2, %hpstate
191
192
193	mov CMP_CORE_ID, %g1;
194	ldxa [%g1]ASI_CMP_CORE, %g1;
195	andcc %g1, NSTRANDS - 1, %g0;
196	bnz bypass_mcu_init;
197	nop;
198
199	SET_MCU(%g1, %g2, 0)
200	SET_MCU(%g1, %g2, 1)
201	SET_MCU(%g1, %g2, 2)
202	SET_MCU(%g1, %g2, 3)
203
204	bypass_mcu_init:
205
206	mov CMP_CORE_ENABLE_STATUS, %g6
207	ldxa [%g6]ASI_CMP_CHIP, %g6 ! get enabled cores
208
209	! find lowest bit set (the 1st nonzero bit) in asi_core_enable
210	clr %g2 ! %g2: initial bit to start btst
211	mov 1, %g3 ! %g3: bit mask of selected bit
212	1:
213	inc %g2 !
214	btst %g3, %g6 ! perform btst on bits 0,1,...,x
215	bz,a,pt %xcc, 1b ! until asi_core_enable[x]=1.
216	sllx %g3, 1, %g3 !
217	dec %g2 !
218
219	mov CMP_CORE_ID, %g1
220	ldxa [%g1]ASI_CMP_CORE, %g1 ! get virtual core id
221	and %g1, 0x3f, %g1 ! %g1 - current core id
222
223	! sync up tick regs in all enabled cores with bit masks set to LOCK_ADDR
224	wrpr %g0, %tick
225	setx LOCK_ADDR, %g4, %g3 ! the initial mask value is zero
226	mov 1, %g5 ! set bit mask
227	sllx %g5, %g1, %g5 ! (e.g., bit[i]=1 if %g1=i)
228	2:
229	ldx [%g3], %g4 ! get the old mask
230	or %g4, %g5, %g7 ! set the new mask
231	casx [%g3], %g4, %g7 ! try to update [LOCK_ADDR] with
232	cmp %g4, %g7 ! the new mask
233	bne 2b ! try again if update failed
234	nop
235
236	! branch out as master or slave (the lowest core becomes master)
237	cmp %g2, %g1
238	be,pt %xcc, .master_entry
239	nop
240
241	.slave_entry:
242	/*
243	* Slave
244	*/
245	setx MEMBASE, %g4, %g1 ! Mem base XXX
246	setx MEMSIZE, %g4, %g2 ! Mem size XXX
247	setx HVPD, %g4, %g3 ! Partition Description
248
249	setx save_restore, %g5, %g4 ! are we running a checkpointed image?
250	ldx [%g4], %g4
251	brnz,pn %g4, 4f ! yes, then jump to SR code
252	nop
253
254	setx HV, %g5, %g4
255	jmp %g4 + 0x30
256	nop
257	4:
258	jmp %g4 + 0x20
259	nop
260
261	.master_entry:
262	/*
263	* Master
264	*/
265	mov CMP_TICK_ENABLE, %g4
266	mov 1, %g5
267	stxa %g5, [%g4]ASI_CMP_CHIP
268
269	setx L2_CONTROL_REG, %g2, %g1 ! enable L2$ and scrubbing
270	setx L2_SCRUBENABLE \| (1<<L2_SCRUBINTERVAL_SHIFT), %g3, %g2
271	stx %g2, [%g1]
272	stx %g2, [%g1 + 0x040]
273	stx %g2, [%g1 + 0x080]
274	stx %g2, [%g1 + 0x0c0]
275	stx %g2, [%g1 + 0x100]
276	stx %g2, [%g1 + 0x140]
277	stx %g2, [%g1 + 0x180]
278	stx %g2, [%g1 + 0x1c0]
279
280	setx MEMBASE, %g4, %g1 ! Mem base XXX
281	setx MEMSIZE, %g4, %g2 ! Mem size XXX
282	setx HVPD, %g4, %g3 ! Partition Description
283
284	mov CMP_CORE_ENABLE_STATUS, %g6
285	ldxa [%g6]ASI_CMP_CHIP, %g6 ! get enabled cores
286
287	setx save_restore, %g5, %g4 ! are we running a checkpointed image?
288	ldx [%g4], %g4
289	brnz,pn %g4, 5f ! yes, then jump to SR code
290	nop
291
292	setx HV, %g5, %g4
293	5:
294	jmp %g4 + 0x20
295	mov %g6, %g4 ! %g4: CPU start set
296
297	SET_SIZE(start_reset)
298
299	ENTRY_NP(rtrap)
300	ta 0x1
301	SET_SIZE(rtrap)
302
303	! %g1 contains trap# to revector to
304	ENTRY_NP(revec)
305	rdhpr %htba, %g2
306	sllx %g1, 5, %g1
307	add %g2, %g1, %g2
308	jmp %g2
309	wrhpr %g0, (HPSTATE_HPRIV \| HPSTATE_ENB), %hpstate
310	SET_SIZE(revec)
311
312	!! KEEP THIS AT THE END
313	.align 0x100