Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / huron / include / error_soc.h
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1/*
2* ========== Copyright Header Begin ==========================================
3*
4* Hypervisor Software File: error_soc.h
5*
6* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
7*
8* - Do no alter or remove copyright notices
9*
10* - Redistribution and use of this software in source and binary forms, with
11* or without modification, are permitted provided that the following
12* conditions are met:
13*
14* - Redistribution of source code must retain the above copyright notice,
15* this list of conditions and the following disclaimer.
16*
17* - Redistribution in binary form must reproduce the above copyright notice,
18* this list of conditions and the following disclaimer in the
19* documentation and/or other materials provided with the distribution.
20*
21* Neither the name of Sun Microsystems, Inc. or the names of contributors
22* may be used to endorse or promote products derived from this software
23* without specific prior written permission.
24*
25* This software is provided "AS IS," without a warranty of any kind.
26* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
27* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
28* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
29* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
30* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
31* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
32* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
33* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
34* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
35* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
36* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
37*
38* You acknowledge that this software is not designed, licensed or
39* intended for use in the design, construction, operation or maintenance of
40* any nuclear facility.
41*
42* ========== Copyright Header End ============================================
43*/
44/*
45 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
46 * Use is subject to license terms.
47 */
48
49#ifndef _NIAGARA2_ERROR_SOC_H
50#define _NIAGARA2_ERROR_SOC_H
51
52#pragma ident "@(#)error_soc.h 1.2 07/06/20 SMI"
53
54#include <sys/htypes.h>
55
56#ifdef __cplusplus
57extern "C" {
58#endif
59
60#define SOC_ERROR_STATUS_REG 0x8000003000
61#define SOC_ERROR_LOG_ENABLE 0x8000003008
62#define SOC_ERROR_TRAP_ENABLE 0x8000003010
63#define SOC_ERROR_INJECTION_REG 0x8000003018
64#define SOC_FATAL_ERROR_ENABLE 0x8000003020
65#define SOC_PENDING_ERROR_STATUS_REG 0x8000003028
66#define SOC_SII_ERROR_SYNDROME_REG 0x8000003030
67#define SOC_NCU_ERROR_SYNDROME_REG 0x8000003038
68#define SOC_ERRORSTEER_REG 0x9001041000
69
70/*
71 * All SOC ESRs have the same format
72 */
73#define SOC_SIINIUCTAGUE (1 << 0)
74#define SOC_SIIDMUCTAGUE (1 << 1)
75#define SOC_SIINIUCTAGCE (1 << 2)
76#define SOC_SIIDMUCTAGCE (1 << 3)
77#define SOC_SIINIUAPARITY (1 << 4)
78#define SOC_SIIDMUDPARITY (1 << 5)
79#define SOC_SIINIUDPARITY (1 << 6)
80#define SOC_SIIDMUAPARITY (1 << 7)
81#define SOC_DMUINTERNAL (1 << 8)
82#define SOC_DMUNCUCREDIT (1 << 9)
83#define SOC_DMUCTAGCE (1 << 10)
84#define SOC_DMUCTAGUE (1 << 11)
85#define SOC_DMUSIICREDIT (1 << 12)
86#define SOC_DMUDATAPARITY (1 << 13)
87#define SOC_NCUDATAPARITY (1 << 14)
88#define SOC_NCUMONDOTABLE (1 << 15)
89#define SOC_NCUMONDOFIFO (1 << 16)
90#define SOC_NCUINTTABLE (1 << 17)
91#define SOC_NCUPCXDATA (1 << 18)
92#define SOC_NCUPCXUE (1 << 19)
93#define SOC_NCUCPXUE (1 << 20)
94#define SOC_NCUDMUUE (1 << 21)
95#define SOC_NCUCTAGUE (1 << 22)
96#define SOC_NCUCTAGCE (1 << 23)
97#define SOC_SIOCTAGUE (1 << 25)
98#define SOC_SIOCTAGCE (1 << 26)
99#define SOC_NIUCTAGCE (1 << 27)
100#define SOC_NIUCTAGUE (1 << 28)
101#define SOC_NIUDATAPARITY (1 << 29)
102#define SOC_MCU0FBR (1 << 31)
103#define SOC_MCU0ECC (1 << 32)
104#define SOC_MCU1FBR (1 << 34)
105#define SOC_MCU1ECC (1 << 35)
106#define SOC_MCU2FBR (1 << 37)
107#define SOC_MCU2ECC (1 << 38)
108#define SOC_MCU3FBR (1 << 40)
109#define SOC_MCU3ECC (1 << 41)
110#define SOC_NCUDMUCREDIT (1 << 42)
111#define SOC_V (1 << 63)
112
113#define SOC_ALL_ERRORS \
114 (SOC_NCUDMUCREDIT | SOC_MCU3ECC | SOC_MCU3FBR | \
115 SOC_MCU2ECC | SOC_MCU2FBR | SOC_MCU1ECC | SOC_MCU1FBR | \
116 SOC_MCU0ECC | SOC_MCU0FBR | SOC_NIUDATAPARITY | \
117 SOC_NIUCTAGUE | SOC_NIUCTAGCE | SOC_SIOCTAGCE | \
118 SOC_SIOCTAGUE | SOC_NCUCTAGCE | SOC_NCUCTAGUE | \
119 SOC_NCUDMUUE | SOC_NCUCPXUE | SOC_NCUPCXUE | \
120 SOC_NCUPCXDATA | SOC_NCUINTTABLE | SOC_NCUMONDOFIFO | \
121 SOC_NCUMONDOTABLE |SOC_NCUDATAPARITY | \
122 SOC_DMUDATAPARITY | SOC_DMUSIICREDIT | SOC_DMUCTAGUE | \
123 SOC_DMUCTAGCE | SOC_DMUNCUCREDIT | SOC_DMUINTERNAL | \
124 SOC_SIIDMUAPARITY | SOC_SIINIUDPARITY | \
125 SOC_SIIDMUDPARITY | SOC_SIINIUAPARITY | \
126 SOC_SIIDMUCTAGCE | SOC_SIINIUCTAGCE | \
127 SOC_SIIDMUCTAGUE | SOC_SIINIUCTAGUE)
128
129#define SOC_CORRECTABLE_ERRORS \
130 (SOC_MCU3ECC | SOC_MCU3FBR | SOC_MCU2ECC | SOC_MCU2FBR |\
131 SOC_MCU1ECC | SOC_MCU1FBR | SOC_MCU0ECC | SOC_MCU0FBR | \
132 SOC_NIUCTAGCE | SOC_SIOCTAGCE | SOC_NCUCTAGCE | \
133 SOC_SIIDMUCTAGCE | SOC_SIINIUCTAGCE)
134
135#define SOC_FATAL_ERRORS \
136 (SOC_ALL_ERRORS & ~SOC_CORRECTABLE_ERRORS)
137
138#define SUN4V_DESC_FLAGS_TBD 0
139
140#define SUN4V_SIINIUDPARITY ERR_PCIE_ERPT_DESC(1, 2, 2, 3, 2, 1)
141#define SUN4V_SIIDMUDPARITY ERR_PCIE_ERPT_DESC(1, 2, 2, 3, 2, 1)
142#define SUN4V_NCUMONDOTABLE ERR_PCIE_ERPT_DESC(1, 1, 2, 3, 1, \
143 SUN4V_DESC_FLAGS_TBD)
144#define SUN4V_NCUPCXDATA ERR_PCIE_ERPT_DESC(1, 2, 2, 3, 0, 1)
145
146/*
147 * SOC NCU Error Syndrome register
148 *
149 * +------------------------------------------------------------+
150 * |63|62|61|60|59|58|57:56|55:51| 50:46| 45:43| 42:40| 39:0|
151 * +------------------------------------------------------------+
152 * | v| g| r| c| s| p| - | etag|reqtype|coreid|standid|pa_ctag|
153 * +------------------------------------------------------------+
154 */
155#define SOC_NCU_ESR_V_SHIFT 63 /* syndrome valid bit */
156#define SOC_NCU_ESR_V (1 << SOC_NCU_ESR_V_SHIFT)
157#define SOC_NCU_ESR_G_SHIFT 62 /* CTAG valid bit */
158#define SOC_NCU_ESR_G (1 << SOC_NCU_ESR_G_SHIFT)
159#define SOC_NCU_ESR_R_SHIFT 61 /* reqtype valid bit */
160#define SOC_NCU_ESR_R (1 << SOC_NCU_ESR_R_SHIFT)
161#define SOC_NCU_ESR_C_SHIFT 60 /* coreid valid bit */
162#define SOC_NCU_ESR_C (1 << SOC_NCU_ESR_C_SHIFT)
163#define SOC_NCU_ESR_S_SHIFT 59 /* strandid valid bit */
164#define SOC_NCU_ESR_S (1 << SOC_NCU_ESR_S_SHIFT)
165#define SOC_NCU_ESR_P_SHIFT 58 /* PA valid bit */
166#define SOC_NCU_ESR_P (1 << SOC_NCU_ESR_P_SHIFT)
167#define SOC_NCU_ESR_ETAG_SHIFT 51 /* Error tag */
168#define SOC_NCU_ESR_ETAG_MASK 0x1f
169#define SOC_NCU_ESR_REQTYPE_SHIFT 46 /* request type */
170#define SOC_NCU_ESR_REQTYPE_MASK 0x1f
171#define SOC_NCU_ESR_COREID_SHIFT 43 /* Physical strand id */
172#define SOC_NCU_ESR_COREID_MASK 0x7
173#define SOC_NCU_ESR_STRANDID_SHIFT 40 /* Strand id on physical core */
174#define SOC_NCU_ESR_STRANDID_MASK 0x7
175/* PA[39:0] if p is set. CTAG[15:0] if g is set */
176#define SOC_NCU_ESR_PA_SHIFT 0
177#define SOC_NCU_ESR_PA_MASK 0xffffffffff
178#define SOC_NCU_ESR_PA_MSB_MASK 0xff00000000
179
180/*
181 * Filter FBRs to minimise the number of SERs sent to the SP.
182 */
183#define DRAM_ERROR_COUNTER_FBR_RATIO 8
184
185#ifdef __cplusplus
186}
187#endif
188
189#endif /* _NIAGARA2_ERROR_SOC_H */