[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / huron / src / setup.s

/*
* ========== Copyright Header Begin ==========================================
*
* Hypervisor Software File: setup.s
* 
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* 
*  - Do no alter or remove copyright notices
* 
*  - Redistribution and use of this software in source and binary forms, with 
*    or without modification, are permitted provided that the following 
*    conditions are met: 
* 
*  - Redistribution of source code must retain the above copyright notice, 
*    this list of conditions and the following disclaimer.
* 
*  - Redistribution in binary form must reproduce the above copyright notice,
*    this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution. 
* 
*    Neither the name of Sun Microsystems, Inc. or the names of contributors 
* may be used to endorse or promote products derived from this software 
* without specific prior written permission. 
* 
*     This software is provided "AS IS," without a warranty of any kind. 
* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, 
* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN 
* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR 
* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR 
* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN 
* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR 
* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE 
* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, 
* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF 
* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* 
* You acknowledge that this software is not designed, licensed or
* intended for use in the design, construction, operation or maintenance of
* any nuclear facility. 
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

	.ident	"@(#)setup.s	1.5	07/07/25 SMI"

	.file	"setup.s"

/*
 * Routines that configure the hypervisor
 */

#include <sys/asm_linkage.h>
#include <sys/htypes.h>
#include <hprivregs.h>
#include <asi.h>
#include <fpga.h>
#include <intr.h>
#include <sun4v/traps.h>
#include <sun4v/mmu.h>
#include <sun4v/asi.h>
#include <sun4v/queue.h>
#include <devices/pc16550.h>

#include <guest.h>
#include <offsets.h>
#include <md.h>
#include <svc.h>
#include <vdev_intr.h>
#include <abort.h>
#include <vcpu.h>
#include <util.h>
#include <debug.h>
#include <error_asm.h>
#include <cmp.h>


#define	HVALLOC(root, size, ptr, tmp)		\
	ldx	[root + CONFIG_BRK], ptr	;\
	add	ptr, size, tmp			;\
	stx	tmp, [root + CONFIG_BRK]

#define	CPUID_2_MAUID(cpu, mau)		\
	srlx	cpu, CPUID_2_COREID_SHIFT, mau
#define	CPUID_2_CWQID(cpu, cwq)		\
	srlx	cpu, CPUID_2_COREID_SHIFT, cwq

#define	CONFIG	%i0
#define	GUESTS	%i1
#define	CPUS	%i2


#if defined(CONFIG_PIU)
/*
 * setup_piu: Initialize PIU
 *
 * in:
 *	%i0 - global config pointer
 *	%i1 - base of guests
 *	%i2 - base of cpus
 *	%g7 - return address
 *
 * volatile:
 *	%locals
 *	%outs
 *	%globals
 */
	ENTRY_NP(setup_piu)

	mov	%g7, %l7	/* save return address */
	PRINT("HV:setup_piu \r\n")
	/*
	 * Relocate PIU TSB base pointers
	 */
	ldx	[%i0 + CONFIG_RELOC], %o0
	setx	piu_dev, %o2, %o1
	sub	%o1, %o0, %o1
	ldx	[%o1 + PIU_COOKIE_IOTSB0], %o2
	sub	%o2, %o0, %o2
	stx	%o2, [%o1 + PIU_COOKIE_IOTSB0]
	ldx	[%o1 + PIU_COOKIE_IOTSB1], %o2
	sub	%o2, %o0, %o2
	stx	%o2, [%o1 + PIU_COOKIE_IOTSB1]

	/*
	 * Relocate PIU MSI EQ base pointers
	 */
	ldx	[%o1 + PIU_COOKIE_MSIEQBASE], %o2
	sub	%o2, %o0, %o2
	stx	%o2, [%o1 + PIU_COOKIE_MSIEQBASE]

	/*
	 * Relocate PIU Virtual Interrupt pointer
	 */
	ldx	[%o1 + PIU_COOKIE_VIRTUAL_INTMAP], %o2
	sub	%o2, %o0, %o2
	stx	%o2, [%o1 + PIU_COOKIE_VIRTUAL_INTMAP]

	/*
	 * Relocate PIU MSI and ERR Cookies
	 */

	ldx	[%o1 + PIU_COOKIE_ERRCOOKIE], %o2
	sub	%o2, %o0, %o2
	stx	%o2, [%o1 + PIU_COOKIE_ERRCOOKIE]
	ldx	[%o2 + PIU_ERR_COOKIE_PIU], %o4
	sub	%o4, %o0, %o4
	stx	%o4, [%o2 + PIU_ERR_COOKIE_PIU]

	ldx	[%o1 + PIU_COOKIE_MSICOOKIE], %o2
	sub	%o2, %o0, %o2
	stx	%o2, [%o1 + PIU_COOKIE_MSICOOKIE]
	ldx	[%o2 + PIU_MSI_COOKIE_PIU], %o4
	sub	%o4, %o0, %o4
	stx	%o4, [%o2 + PIU_MSI_COOKIE_PIU]

	setx	piu_msi, %o2, %o1
	sub	%o1, %o0, %o1

	mov	PIU_NEQS, %o3
	add	%o1, PIU_MSI_COOKIE_EQ, %o2
0:
	ldx	[%o2 + PIU_MSIEQ_BASE], %o4
	sub	%o4, %o0, %o4
	stx	%o4, [%o2 + PIU_MSIEQ_BASE]
	add	%o2, PIU_MSIEQ_SIZE, %o2
	subcc	%o3, 1, %o3
	bnz	0b
	nop

	ba	piu_init
	mov	%l7, %g7
	SET_SIZE(setup_piu)
#endif	/* CONFIG_PIU */

/*
 * dummy tsb for the hypervisor to use
 */
BSS_GLOBAL(dummytsb, DUMMYTSB_SIZE, DUMMYTSB_ALIGN)

/*
 * setup_ncu
 *
 * in:
 *	%i0 - global config pointer
 *	%i1 - base of guests
 *	%i2 - base of cpus
 *	%g7 - return address
 *
 * volatile:
 *	%locals
 */
	ENTRY_NP(setup_ncu)
	ldx	[CONFIG + CONFIG_INTRTGT], %g1
	setx	NCU_BASE, %g3, %g2
	!! %g1 = intrtgt CPUID array (8-bits per INT_MAN target)
	!! %g2 = NCU Base address

	/*
	 * setup the map registers for the SSI
	 */

	/* SSI Error interrupt */
	srl	%g1, INTRTGT_DEVSHIFT, %g1 ! get dev1 bits in bottom
	and	%g1, INTRTGT_CPUMASK, %g3
	sllx	%g3, INT_MAN_CPU_SHIFT, %g3 ! int_man.cpu
	or	%g3, VECINTR_SSIERR, %g3 ! int_man.vecnum
	stx	%g3, [%g2 + INT_MAN + INT_MAN_DEV_OFF(NCUDEV_SSIERR)]

	/* SSI Interrupt */
	srl	%g1, INTRTGT_DEVSHIFT, %g1 ! get dev2 bits in bottom
	and	%g1, INTRTGT_CPUMASK, %g3
	sllx	%g3, INT_MAN_CPU_SHIFT, %g3 ! int_man.cpu
	or	%g3, VECINTR_FPGA, %g3 ! int_man.vecnum
	stx	%g3, [%g2 + INT_MAN + INT_MAN_DEV_OFF(NCUDEV_SSI)]

	/* PIU Interrupt */
	setx	NCU_BASE + MONDO_INT_VEC, %g2, %g1
	mov	VECINTR_DEV, %g2
	stx	%g2, [%g1]

	setx	DEV_MONDO_INT + DEV_MONDO_INT_BUSY, %g2, %g1
	set	NSTRANDS * 8, %g3
	/* Clear the INT_BUSY bits */
1:	deccc	8, %g3
	bg,pt	%xcc, 1b
	stx	%g0, [%g1 + %g3]

	jmp	%g7 + 4
	nop
	SET_SIZE(setup_ncu)


#ifdef CONFIG_SVC /* { */

/*
 * c_svc_register() requires that we have these 2 null functions
 * declared here.
 */
/*
 * error_svc_rx
 *
 * %g1 callback cookie
 * %g2 svc pointer
 * %g7 return address
 */
        ENTRY(error_svc_rx)
	/*
	 * Done with this packet
	 */
	ld	[%g2 + SVC_CTRL_STATE], %g5
	andn	%g5, SVC_FLAGS_RI, %g5
	st	%g5, [%g2 + SVC_CTRL_STATE]	! clear RECV pending

        mov     %g7, %g6
	PRINT("error_svc_rx\r\n")
        mov	%g6, %g7

        jmp     %g7 + 4
        nop
        SET_SIZE(error_svc_rx)

/*
 * cn_svc_tx - error report transmission completion interrupt
 *
 * While sram was busy an other error may have occurred. In such case, we
 * increase the send pkt counter and mark such packet for delivery.
 * In this function, we check to see if there are any packets to be transmitted.
 *
 * We search in the following way:
 * Look at PIU jbi err buffer XXXX
 * Look at PIU pcie err buffer
 * For each cpu in NCPUS
 *   Look at CE err buffer
 *   Look at UE err buffer
 *
 * We only send a packet at a time, and in the previously described order.
 * Since we are running in the intr completion routing, the svc_internal_send
 * has already adquire the locks. For such reason, this routing needs to use
 * send_diag_buf_noblock.
 *
 * %g1 callback cookie
 * %g2 packet
 * %g7 return address
 */
        ENTRY(error_svc_tx)
	STRAND_PUSH(%g7, %g1, %g2)
#if 0
	PRINT("error_svc_tx\r\n")
#endif

	VCPU_STRUCT(%g1)
	ldx	[%g1 + CPU_ROOT], %g1
	stx	%g0, [%g1 + CONFIG_SRAM_ERPT_BUF_INUSE] ! clear the inuse flag

	/*
	 * See if we need to send more packets
	 */
	ldx	[%g1 + CONFIG_ERRS_TO_SEND], %g2
	brz	%g2, 4f
	nop


	/* Now look at the cpu erpts */
	HVCALL(transmit_diag_reports)
4:
	! Pop return pc. Done
	STRAND_POP(%g7, %g1)
	HVRET
        SET_SIZE(error_svc_tx)

#endif /* } CONFIG_SVC */

/*
 * setup_niu:
 *
 * in:
 *	%i0 - global config pointer
 *	%i1 - base of guests
 *	%i2 - base of cpus
 *	%g7 - return address
 *
 * volatile:
 *	%globals, %locals
 */
	ENTRY_NP(setup_niu)
	mov	%g7, %l7	! save return address

	/*
	 * Relocate vector to logical device group table
	 */
	ldx	[%i0 + CONFIG_RELOC], %g1
	setx	niu_dev, %g3, %g2
	sub	%g2, %g1, %g2
	ldx	[%g2 + NIU_LDG2LDN_TABLE], %g3
	sub	%g3, %g1, %g3
	stx	%g3, [%g2 + NIU_LDG2LDN_TABLE]
	/*
	 * Relocate vector to logical device group table
	 */
	ldx	[%g2 + NIU_VEC2LDG_TABLE], %g3
	sub	%g3, %g1, %g3
	stx	%g3, [%g2 + NIU_VEC2LDG_TABLE]

	ba,pt	%xcc, niu_intr_init
	mov	%l7, %g7	! N.B: tail call
	/*NOTREACHED*/
	SET_SIZE(setup_niu)

#ifdef CONFIG_FPGA
	/*
	 * The FPGA interrupt output is an active-low level interrupt.
	 * The Niagara SSI interrupt input is falling-edge-triggered.
	 * We can lose an interrupt across a warm reset so workaround
	 * that by injecting a fake SSI interrupt at start-up time.
	*/
	ENTRY(fake_ssiirq)

        setx    INT_MAN_BASE, %g1, %g2
        ldx     [%g2 + INT_MAN + INT_MAN_DEV_OFF(NCUDEV_SSI)], %g1
        stxa    %g1, [%g0]ASI_INTR_UDB_W
	HVRET

	SET_SIZE(fake_ssiirq)

	ENTRY(setup_fpga_ldc)
	! clear the FPGA MASK registers
	setx	FPGA_LDCIN_BASE, %g6, %g1
	st	%g0, [%g1 + FPGA_LDC_MASK_REG]

	setx	FPGA_LDCOUT_BASE, %g6, %g1
	st	%g0, [%g1 + FPGA_LDC_MASK_REG]

	HVRET
	SET_SIZE(setup_fpga_ldc)
#endif
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* Hypervisor Software File: setup.s
	5	*
	6	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	7	*
	8	* - Do no alter or remove copyright notices
	9	*
	10	* - Redistribution and use of this software in source and binary forms, with
	11	* or without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistribution of source code must retain the above copyright notice,
	15	* this list of conditions and the following disclaimer.
	16	*
	17	* - Redistribution in binary form must reproduce the above copyright notice,
	18	* this list of conditions and the following disclaimer in the
	19	* documentation and/or other materials provided with the distribution.
	20	*
	21	* Neither the name of Sun Microsystems, Inc. or the names of contributors
	22	* may be used to endorse or promote products derived from this software
	23	* without specific prior written permission.
	24	*
	25	* This software is provided "AS IS," without a warranty of any kind.
	26	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
	27	* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
	28	* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
	29	* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
	30	* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
	31	* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
	32	* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
	33	* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
	34	* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
	35	* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
	36	* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
	37	*
	38	* You acknowledge that this software is not designed, licensed or
	39	* intended for use in the design, construction, operation or maintenance of
	40	* any nuclear facility.
	41	*
	42	* ========== Copyright Header End ============================================
	43	*/
	44	/*
	45	* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
	46	* Use is subject to license terms.
	47	*/
	48
	49	.ident "@(#)setup.s 1.5 07/07/25 SMI"
	50
	51	.file "setup.s"
	52
	53	/*
	54	* Routines that configure the hypervisor
	55	*/
	56
	57	#include <sys/asm_linkage.h>
	58	#include <sys/htypes.h>
	59	#include <hprivregs.h>
	60	#include <asi.h>
	61	#include <fpga.h>
	62	#include <intr.h>
	63	#include <sun4v/traps.h>
	64	#include <sun4v/mmu.h>
65	#include <sun4v/asi.h>
66	#include <sun4v/queue.h>
67	#include <devices/pc16550.h>
68
69	#include <guest.h>
70	#include <offsets.h>
71	#include <md.h>
72	#include <svc.h>
73	#include <vdev_intr.h>
74	#include <abort.h>
75	#include <vcpu.h>
76	#include <util.h>
77	#include <debug.h>
78	#include <error_asm.h>
79	#include <cmp.h>
80
81
82	#define HVALLOC(root, size, ptr, tmp) \
83	ldx [root + CONFIG_BRK], ptr ;\
84	add ptr, size, tmp ;\
85	stx tmp, [root + CONFIG_BRK]
86
87	#define CPUID_2_MAUID(cpu, mau) \
88	srlx cpu, CPUID_2_COREID_SHIFT, mau
89	#define CPUID_2_CWQID(cpu, cwq) \
90	srlx cpu, CPUID_2_COREID_SHIFT, cwq
91
92	#define CONFIG %i0
93	#define GUESTS %i1
94	#define CPUS %i2
95
96
97	#if defined(CONFIG_PIU)
98	/*
99	* setup_piu: Initialize PIU
100	*
101	* in:
102	* %i0 - global config pointer
103	* %i1 - base of guests
104	* %i2 - base of cpus
105	* %g7 - return address
106	*
107	* volatile:
108	* %locals
109	* %outs
110	* %globals
111	*/
112	ENTRY_NP(setup_piu)
113
114	mov %g7, %l7 /* save return address */
115	PRINT("HV:setup_piu \r\n")
116	/*
117	* Relocate PIU TSB base pointers
118	*/
119	ldx [%i0 + CONFIG_RELOC], %o0
120	setx piu_dev, %o2, %o1
121	sub %o1, %o0, %o1
122	ldx [%o1 + PIU_COOKIE_IOTSB0], %o2
123	sub %o2, %o0, %o2
124	stx %o2, [%o1 + PIU_COOKIE_IOTSB0]
125	ldx [%o1 + PIU_COOKIE_IOTSB1], %o2
126	sub %o2, %o0, %o2
127	stx %o2, [%o1 + PIU_COOKIE_IOTSB1]
128
129	/*
130	* Relocate PIU MSI EQ base pointers
131	*/
132	ldx [%o1 + PIU_COOKIE_MSIEQBASE], %o2
133	sub %o2, %o0, %o2
134	stx %o2, [%o1 + PIU_COOKIE_MSIEQBASE]
135
136	/*
137	* Relocate PIU Virtual Interrupt pointer
138	*/
139	ldx [%o1 + PIU_COOKIE_VIRTUAL_INTMAP], %o2
140	sub %o2, %o0, %o2
141	stx %o2, [%o1 + PIU_COOKIE_VIRTUAL_INTMAP]
142
143	/*
144	* Relocate PIU MSI and ERR Cookies
145	*/
146
147	ldx [%o1 + PIU_COOKIE_ERRCOOKIE], %o2
148	sub %o2, %o0, %o2
149	stx %o2, [%o1 + PIU_COOKIE_ERRCOOKIE]
150	ldx [%o2 + PIU_ERR_COOKIE_PIU], %o4
151	sub %o4, %o0, %o4
152	stx %o4, [%o2 + PIU_ERR_COOKIE_PIU]
153
154	ldx [%o1 + PIU_COOKIE_MSICOOKIE], %o2
155	sub %o2, %o0, %o2
156	stx %o2, [%o1 + PIU_COOKIE_MSICOOKIE]
157	ldx [%o2 + PIU_MSI_COOKIE_PIU], %o4
158	sub %o4, %o0, %o4
159	stx %o4, [%o2 + PIU_MSI_COOKIE_PIU]
160
161	setx piu_msi, %o2, %o1
162	sub %o1, %o0, %o1
163
164	mov PIU_NEQS, %o3
165	add %o1, PIU_MSI_COOKIE_EQ, %o2
166	0:
167	ldx [%o2 + PIU_MSIEQ_BASE], %o4
168	sub %o4, %o0, %o4
169	stx %o4, [%o2 + PIU_MSIEQ_BASE]
170	add %o2, PIU_MSIEQ_SIZE, %o2
171	subcc %o3, 1, %o3
172	bnz 0b
173	nop
174
175	ba piu_init
176	mov %l7, %g7
177	SET_SIZE(setup_piu)
178	#endif /* CONFIG_PIU */
179
180	/*
181	* dummy tsb for the hypervisor to use
182	*/
183	BSS_GLOBAL(dummytsb, DUMMYTSB_SIZE, DUMMYTSB_ALIGN)
184
185	/*
186	* setup_ncu
187	*
188	* in:
189	* %i0 - global config pointer
190	* %i1 - base of guests
191	* %i2 - base of cpus
192	* %g7 - return address
193	*
194	* volatile:
195	* %locals
196	*/
197	ENTRY_NP(setup_ncu)
198	ldx [CONFIG + CONFIG_INTRTGT], %g1
199	setx NCU_BASE, %g3, %g2
200	!! %g1 = intrtgt CPUID array (8-bits per INT_MAN target)
201	!! %g2 = NCU Base address
202
203	/*
204	* setup the map registers for the SSI
205	*/
206
207	/* SSI Error interrupt */
208	srl %g1, INTRTGT_DEVSHIFT, %g1 ! get dev1 bits in bottom
209	and %g1, INTRTGT_CPUMASK, %g3
210	sllx %g3, INT_MAN_CPU_SHIFT, %g3 ! int_man.cpu
211	or %g3, VECINTR_SSIERR, %g3 ! int_man.vecnum
212	stx %g3, [%g2 + INT_MAN + INT_MAN_DEV_OFF(NCUDEV_SSIERR)]
213
214	/* SSI Interrupt */
215	srl %g1, INTRTGT_DEVSHIFT, %g1 ! get dev2 bits in bottom
216	and %g1, INTRTGT_CPUMASK, %g3
217	sllx %g3, INT_MAN_CPU_SHIFT, %g3 ! int_man.cpu
218	or %g3, VECINTR_FPGA, %g3 ! int_man.vecnum
219	stx %g3, [%g2 + INT_MAN + INT_MAN_DEV_OFF(NCUDEV_SSI)]
220
221	/* PIU Interrupt */
222	setx NCU_BASE + MONDO_INT_VEC, %g2, %g1
223	mov VECINTR_DEV, %g2
224	stx %g2, [%g1]
225
226	setx DEV_MONDO_INT + DEV_MONDO_INT_BUSY, %g2, %g1
227	set NSTRANDS * 8, %g3
228	/* Clear the INT_BUSY bits */
229	1: deccc 8, %g3
230	bg,pt %xcc, 1b
231	stx %g0, [%g1 + %g3]
232
233	jmp %g7 + 4
234	nop
235	SET_SIZE(setup_ncu)
236
237
238	#ifdef CONFIG_SVC /* { */
239
240	/*
241	* c_svc_register() requires that we have these 2 null functions
242	* declared here.
243	*/
244	/*
245	* error_svc_rx
246	*
247	* %g1 callback cookie
248	* %g2 svc pointer
249	* %g7 return address
250	*/
251	ENTRY(error_svc_rx)
252	/*
253	* Done with this packet
254	*/
255	ld [%g2 + SVC_CTRL_STATE], %g5
256	andn %g5, SVC_FLAGS_RI, %g5
257	st %g5, [%g2 + SVC_CTRL_STATE] ! clear RECV pending
258
259	mov %g7, %g6
260	PRINT("error_svc_rx\r\n")
261	mov %g6, %g7
262
263	jmp %g7 + 4
264	nop
265	SET_SIZE(error_svc_rx)
266
267	/*
268	* cn_svc_tx - error report transmission completion interrupt
269	*
270	* While sram was busy an other error may have occurred. In such case, we
271	* increase the send pkt counter and mark such packet for delivery.
272	* In this function, we check to see if there are any packets to be transmitted.
273	*
274	* We search in the following way:
275	* Look at PIU jbi err buffer XXXX
276	* Look at PIU pcie err buffer
277	* For each cpu in NCPUS
278	* Look at CE err buffer
279	* Look at UE err buffer
280	*
281	* We only send a packet at a time, and in the previously described order.
282	* Since we are running in the intr completion routing, the svc_internal_send
283	* has already adquire the locks. For such reason, this routing needs to use
284	* send_diag_buf_noblock.
285	*
286	* %g1 callback cookie
287	* %g2 packet
288	* %g7 return address
289	*/
290	ENTRY(error_svc_tx)
291	STRAND_PUSH(%g7, %g1, %g2)
292	#if 0
293	PRINT("error_svc_tx\r\n")
294	#endif
295
296	VCPU_STRUCT(%g1)
297	ldx [%g1 + CPU_ROOT], %g1
298	stx %g0, [%g1 + CONFIG_SRAM_ERPT_BUF_INUSE] ! clear the inuse flag
299
300	/*
301	* See if we need to send more packets
302	*/
303	ldx [%g1 + CONFIG_ERRS_TO_SEND], %g2
304	brz %g2, 4f
305	nop
306
307
308	/* Now look at the cpu erpts */
309	HVCALL(transmit_diag_reports)
310	4:
311	! Pop return pc. Done
312	STRAND_POP(%g7, %g1)
313	HVRET
314	SET_SIZE(error_svc_tx)
315
316	#endif /* } CONFIG_SVC */
317
318	/*
319	* setup_niu:
320	*
321	* in:
322	* %i0 - global config pointer
323	* %i1 - base of guests
324	* %i2 - base of cpus
325	* %g7 - return address
326	*
327	* volatile:
328	* %globals, %locals
329	*/
330	ENTRY_NP(setup_niu)
331	mov %g7, %l7 ! save return address
332
333	/*
334	* Relocate vector to logical device group table
335	*/
336	ldx [%i0 + CONFIG_RELOC], %g1
337	setx niu_dev, %g3, %g2
338	sub %g2, %g1, %g2
339	ldx [%g2 + NIU_LDG2LDN_TABLE], %g3
340	sub %g3, %g1, %g3
341	stx %g3, [%g2 + NIU_LDG2LDN_TABLE]
342	/*
343	* Relocate vector to logical device group table
344	*/
345	ldx [%g2 + NIU_VEC2LDG_TABLE], %g3
346	sub %g3, %g1, %g3
347	stx %g3, [%g2 + NIU_VEC2LDG_TABLE]
348
349	ba,pt %xcc, niu_intr_init
350	mov %l7, %g7 ! N.B: tail call
351	/NOTREACHED/
352	SET_SIZE(setup_niu)
353
354	#ifdef CONFIG_FPGA
355	/*
356	* The FPGA interrupt output is an active-low level interrupt.
357	* The Niagara SSI interrupt input is falling-edge-triggered.
358	* We can lose an interrupt across a warm reset so workaround
359	* that by injecting a fake SSI interrupt at start-up time.
360	*/
361	ENTRY(fake_ssiirq)
362
363	setx INT_MAN_BASE, %g1, %g2
364	ldx [%g2 + INT_MAN + INT_MAN_DEV_OFF(NCUDEV_SSI)], %g1
365	stxa %g1, [%g0]ASI_INTR_UDB_W
366	HVRET
367
368	SET_SIZE(fake_ssiirq)
369
370	ENTRY(setup_fpga_ldc)
371	! clear the FPGA MASK registers
372	setx FPGA_LDCIN_BASE, %g6, %g1
373	st %g0, [%g1 + FPGA_LDC_MASK_REG]
374
375	setx FPGA_LDCOUT_BASE, %g6, %g1
376	st %g0, [%g1 + FPGA_LDC_MASK_REG]
377
378	HVRET
379	SET_SIZE(setup_fpga_ldc)
380	#endif