[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / ontario / dumbreset / reset.s

/*
* ========== Copyright Header Begin ==========================================
*
* Hypervisor Software File: reset.s
* 
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* 
*  - Do no alter or remove copyright notices
* 
*  - Redistribution and use of this software in source and binary forms, with 
*    or without modification, are permitted provided that the following 
*    conditions are met: 
* 
*  - Redistribution of source code must retain the above copyright notice, 
*    this list of conditions and the following disclaimer.
* 
*  - Redistribution in binary form must reproduce the above copyright notice,
*    this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution. 
* 
*    Neither the name of Sun Microsystems, Inc. or the names of contributors 
* may be used to endorse or promote products derived from this software 
* without specific prior written permission. 
* 
*     This software is provided "AS IS," without a warranty of any kind. 
* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, 
* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN 
* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR 
* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR 
* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN 
* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR 
* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE 
* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, 
* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF 
* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* 
* You acknowledge that this software is not designed, licensed or
* intended for use in the design, construction, operation or maintenance of
* any nuclear facility. 
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

	.ident	"@(#)reset.s	1.18	07/05/03 SMI"

	.file	"reset.s"

/*
 * dumbreset - a minimal Niagara reset sequence with the same
 * hypervisor invocation as the real reset/config.  This is useful
 * when running the hypervisor with Legion, Simics, RTL simulation,
 * Axis, etc.
 */

#include <sys/asm_linkage.h>
#include <sparcv9/asi.h>
#include <hprivregs.h>
#include <sun4v/traps.h>
#include <asi.h>

#if !FOR_ZEUS
#define	MEMBASE		(4 * 1024 * 1024)
#define	MEMSIZE		(60 * 1024 * 1024)
#define	LOCK_ADDR	(MEMBASE + MEMSIZE - 16)
#define	HVPD		0x1f12080000
#define	HV		0xfff0010000
#endif

#ifdef DEBUG_LEGION
#define	CPU_START_SET	0x3
#endif

#define	LOCK_SIZE	64

/*
 * Niagara reset trap tables
 */

#define	TRAP_ALIGN_SIZE		32
#define	TRAP_ALIGN		.align TRAP_ALIGN_SIZE
#define	TRAP_ALIGN_BIG		.align (TRAP_ALIGN_SIZE * 4)

#define	TT_TRACE(label)
#define	TT_TRACE_L(label)

#define	TRAP(ttnum, action) \
	.global	r/**/ttnum	;\
	r/**/ttnum:		;\
	action			;\
	TRAP_ALIGN

#define	BIGTRAP(ttnum, action) \
	.global	r/**/ttnum	;\
	r/**/ttnum:		;\
	action			;\
	TRAP_ALIGN_BIG

#define	GOTO(label)		\
	TT_TRACE(trace_gen)	;\
	.global	label		;\
	ba,a	label		;\
	.empty

/* revector to hypervisor */
#define	HREVEC(ttnum)		\
	TT_TRACE(trace_gen)	;\
	mov	ttnum, %g1	;\
	ba,a	revec		;\
	.empty
	

#define NOT	GOTO(rtrap)
#define	NOT_BIG	NOT NOT NOT NOT
#define	RED	NOT


/*
 * The basic hypervisor trap table
 */

	.section ".text"
	.align	0x8000
	.global	rtraptable
	.type	rtraptable, #function
rtraptable:
	/* hardware traps */
	TRAP(tt0_000, NOT)		/* reserved */
	TRAP(tt0_001, GOTO(start_reset)) /* power-on reset */
	TRAP(tt0_002, HREVEC(0x2))	/* watchdog reset */
	TRAP(tt0_003, HREVEC(0x3))	/* externally initiated reset */
	TRAP(tt0_004, NOT)		/* software initiated reset */
	TRAP(tt0_005, NOT)		/* red mode exception */
	TRAP(tt0_006, NOT)		/* reserved */
	TRAP(tt0_007, NOT)		/* reserved */
ertraptable:
	.size	rtraptable, (.-rtraptable)
	.global	rtraptable
	.type	rtraptable, #function

#if FOR_ZEUS
	.align 8
	.global	hv_info
hv_info:
	.xword 0		/* membase */
	.xword 0		/* memsize */
	.xword 0		/* hv addr */
	.xword 0		/* hv md addr */
	.size	hv_info, (.-hv_info)
#endif

	ENTRY_NP(start_reset)
#ifdef CONFIG_SAS
	! tick needs to be initialized, this is a hack for SAS
	wrpr	%g0, 0, %tick
#endif
	wrpr	%g0, 1, %gl
	wrpr	%g0, 1, %tl
	wrpr	%g0, 0, %cwp

	! set ENB bit
	set	HPSTATE_ENB, %g1
	rdhpr	%hpstate, %g2
	or	%g1, %g2, %g1
	wrhpr	%g1, %hpstate

#ifdef CONFIG_SAS
	! Enable L2 cache prior to enabling L1 caches
	setx	L2_CONTROL_REG, %g2, %g1
	stx	%g0, [%g1 + 0x00]
	stx	%g0, [%g1 + 0x40]
	stx	%g0, [%g1 + 0x80]
	stx	%g0, [%g1 + 0xc0]
#endif

	set	(LSUCR_DC | LSUCR_IC), %g1
	stxa	%g1, [%g0]ASI_LSUCR

	set	((PSTATE_PRIV | PSTATE_MM_TSO) << TSTATE_PSTATE_SHIFT), %g2
	wrpr	%g2, %pstate	! gl=0 ccr=0 asi=0
	! before exiting RED state, setup htba
	setx	0xfff0000000, %g3, %g2	! XXXQ correct value?
	wrhpr	%g2, %htba
	set	(HPSTATE_HPRIV | HPSTATE_ENB), %g2
	wrhpr	%g2, %hpstate

	rd	%asr26, %g1
	srlx	%g1, 8, %g1
	and	%g1, 0x1f, %g5	! %g5 - current cpu id
	inc	%g5		! number from 1..32

#if FOR_ZEUS /* { */
local1:
	rd	%pc, %g6
	add	%g6, hv_info - local1, %g6
	ldx	[%g6], %g1	! Mem base
	ldx	[%g6+8], %g2	! Mem size
	ldx	[%g6+16], %g3	! Machine description location
	ldx	[%g6+24], %g4	! Hypervisor ROM location
#else	/* } { */
	setx	MEMBASE, %g6, %g1 ! Mem base XXX
	setx	MEMSIZE, %g6, %g2 ! Mem size XXX
	setx	HVPD, %g6, %g3	! Partition Description
	setx	HV, %g6, %g4

#endif	/* } */

	sub	%g2, LOCK_SIZE, %g2	! Hide lock location from HV
	add	%g1, %g2, %g7		! Addr of lock location

	ldx	[%g7], %g6
	brnz	%g6, .slave_entry
	  nop

	casxa	[%g7]ASI_N, %g6, %g5
	cmp	%g6, %g5
	be,pt	%xcc, .master_entry
	  nop


	/*
	 * Slave
	 */

.slave_entry:
1:	ldx	[%g7], %g5
	cmp	%g5, -1
	bne,pn	%xcc, 1b	! wait for copy to complete
	  nop

	add	%g4, 0x30, %g4	! Slave entry point
	jmp	%g4
	  nop


	/*
	 * Master
	 */

.master_entry:
		/* IDLE all of the other strands */
	rd	%asr26, %g6
	srlx	%g6, 8, %g6
	and	%g6, 0x1f, %g6	! %g6 - current strand id

	setx	0x9800000800, %g4, %g5 ! int_vec_dis address
	mov	31, %g1
1:	cmp	%g1, %g6
	be,pn	%xcc, 2f	! skip our strand
	nop

	mov	2, %g2		! IDLE command
	sllx	%g2, 16, %g2
	sllx	%g1, 8, %g3	! target strand
	or	%g2, %g3, %g2	! int_vec_dis value
	stx	%g2, [%g5]

2:	deccc	%g1
	bgeu,pt	%xcc, 1b
	nop

		/* Allow them to continue when they wake up */
	mov	-1, %g1
	stx	%g1, [%g7]

		/*
		 * re-init parameters
		 */

#if FOR_ZEUS /* { */
local2:
	rd	%pc, %g6
	add	%g6, hv_info - local2, %g6
	ldx	[%g6], %g1	! Mem base
	ldx	[%g6+8], %g2	! Mem size
	ldx	[%g6+16], %g3	! Machine description location
	ldx	[%g6+24], %g6	! Hypervisor ROM location
#else	/* } { */
	setx	MEMBASE, %g6, %g1 ! Mem base XXX
	setx	MEMSIZE, %g6, %g2 ! Mem size XXX
	setx	HVPD, %g6, %g3	! Partition Description
	setx	HV, %g4, %g6
#endif	/* } */

	! %g4 = cpustartset
	mov     -1, %g4
	srl     %g4, 0, %g4     ! %g4 now contains 0xffff.ffff

	! %g5 = phys mem - only used for scrubbing on real HW so we can use 0x0
	mov     %g0, %g5

        sub     %g2, LOCK_SIZE, %g2     ! Hide lock

	add	%g6, 0x20, %g6
	jmp	%g6
	nop
	SET_SIZE(start_reset)


	ENTRY_NP(rtrap)
	ta	0x1
	SET_SIZE(rtrap)


	! %g1 contains trap# to revector to 
	ENTRY_NP(revec)
	rdhpr	%htba, %g2
	sllx	%g1, 5, %g1
	add	%g2, %g1, %g2
	jmp	%g2
	wrhpr	%g0, (HPSTATE_HPRIV | HPSTATE_ENB), %hpstate
	SET_SIZE(revec)

	!! KEEP THIS AT THE END
	.align	0x100
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* Hypervisor Software File: reset.s
	5	*
	6	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	7	*
	8	* - Do no alter or remove copyright notices
	9	*
	10	* - Redistribution and use of this software in source and binary forms, with
	11	* or without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistribution of source code must retain the above copyright notice,
	15	* this list of conditions and the following disclaimer.
	16	*
	17	* - Redistribution in binary form must reproduce the above copyright notice,
	18	* this list of conditions and the following disclaimer in the
	19	* documentation and/or other materials provided with the distribution.
	20	*
	21	* Neither the name of Sun Microsystems, Inc. or the names of contributors
	22	* may be used to endorse or promote products derived from this software
	23	* without specific prior written permission.
	24	*
	25	* This software is provided "AS IS," without a warranty of any kind.
	26	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
	27	* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
	28	* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
	29	* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
	30	* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
	31	* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
	32	* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
	33	* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
	34	* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
	35	* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
	36	* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
	37	*
	38	* You acknowledge that this software is not designed, licensed or
	39	* intended for use in the design, construction, operation or maintenance of
	40	* any nuclear facility.
	41	*
	42	* ========== Copyright Header End ============================================
	43	*/
	44	/*
	45	* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
	46	* Use is subject to license terms.
	47	*/
	48
	49	.ident "@(#)reset.s 1.18 07/05/03 SMI"
	50
	51	.file "reset.s"
	52
	53	/*
	54	* dumbreset - a minimal Niagara reset sequence with the same
	55	* hypervisor invocation as the real reset/config. This is useful
	56	* when running the hypervisor with Legion, Simics, RTL simulation,
	57	* Axis, etc.
	58	*/
	59
	60	#include <sys/asm_linkage.h>
	61	#include <sparcv9/asi.h>
	62	#include <hprivregs.h>
	63	#include <sun4v/traps.h>
	64	#include <asi.h>
65
66	#if !FOR_ZEUS
67	#define MEMBASE (4 * 1024 * 1024)
68	#define MEMSIZE (60 * 1024 * 1024)
69	#define LOCK_ADDR (MEMBASE + MEMSIZE - 16)
70	#define HVPD 0x1f12080000
71	#define HV 0xfff0010000
72	#endif
73
74	#ifdef DEBUG_LEGION
75	#define CPU_START_SET 0x3
76	#endif
77
78	#define LOCK_SIZE 64
79
80	/*
81	* Niagara reset trap tables
82	*/
83
84	#define TRAP_ALIGN_SIZE 32
85	#define TRAP_ALIGN .align TRAP_ALIGN_SIZE
86	#define TRAP_ALIGN_BIG .align (TRAP_ALIGN_SIZE * 4)
87
88	#define TT_TRACE(label)
89	#define TT_TRACE_L(label)
90
91	#define TRAP(ttnum, action) \
92	.global r/**/ttnum ;\
93	r/**/ttnum: ;\
94	action ;\
95	TRAP_ALIGN
96
97	#define BIGTRAP(ttnum, action) \
98	.global r/**/ttnum ;\
99	r/**/ttnum: ;\
100	action ;\
101	TRAP_ALIGN_BIG
102
103	#define GOTO(label) \
104	TT_TRACE(trace_gen) ;\
105	.global label ;\
106	ba,a label ;\
107	.empty
108
109	/* revector to hypervisor */
110	#define HREVEC(ttnum) \
111	TT_TRACE(trace_gen) ;\
112	mov ttnum, %g1 ;\
113	ba,a revec ;\
114	.empty
115
116
117	#define NOT GOTO(rtrap)
118	#define NOT_BIG NOT NOT NOT NOT
119	#define RED NOT
120
121
122	/*
123	* The basic hypervisor trap table
124	*/
125
126	.section ".text"
127	.align 0x8000
128	.global rtraptable
129	.type rtraptable, #function
130	rtraptable:
131	/* hardware traps */
132	TRAP(tt0_000, NOT) /* reserved */
133	TRAP(tt0_001, GOTO(start_reset)) /* power-on reset */
134	TRAP(tt0_002, HREVEC(0x2)) /* watchdog reset */
135	TRAP(tt0_003, HREVEC(0x3)) /* externally initiated reset */
136	TRAP(tt0_004, NOT) /* software initiated reset */
137	TRAP(tt0_005, NOT) /* red mode exception */
138	TRAP(tt0_006, NOT) /* reserved */
139	TRAP(tt0_007, NOT) /* reserved */
140	ertraptable:
141	.size rtraptable, (.-rtraptable)
142	.global rtraptable
143	.type rtraptable, #function
144
145	#if FOR_ZEUS
146	.align 8
147	.global hv_info
148	hv_info:
149	.xword 0 /* membase */
150	.xword 0 /* memsize */
151	.xword 0 /* hv addr */
152	.xword 0 /* hv md addr */
153	.size hv_info, (.-hv_info)
154	#endif
155
156	ENTRY_NP(start_reset)
157	#ifdef CONFIG_SAS
158	! tick needs to be initialized, this is a hack for SAS
159	wrpr %g0, 0, %tick
160	#endif
161	wrpr %g0, 1, %gl
162	wrpr %g0, 1, %tl
163	wrpr %g0, 0, %cwp
164
165	! set ENB bit
166	set HPSTATE_ENB, %g1
167	rdhpr %hpstate, %g2
168	or %g1, %g2, %g1
169	wrhpr %g1, %hpstate
170
171	#ifdef CONFIG_SAS
172	! Enable L2 cache prior to enabling L1 caches
173	setx L2_CONTROL_REG, %g2, %g1
174	stx %g0, [%g1 + 0x00]
175	stx %g0, [%g1 + 0x40]
176	stx %g0, [%g1 + 0x80]
177	stx %g0, [%g1 + 0xc0]
178	#endif
179
180	set (LSUCR_DC \| LSUCR_IC), %g1
181	stxa %g1, [%g0]ASI_LSUCR
182
183	set ((PSTATE_PRIV \| PSTATE_MM_TSO) << TSTATE_PSTATE_SHIFT), %g2
184	wrpr %g2, %pstate ! gl=0 ccr=0 asi=0
185	! before exiting RED state, setup htba
186	setx 0xfff0000000, %g3, %g2 ! XXXQ correct value?
187	wrhpr %g2, %htba
188	set (HPSTATE_HPRIV \| HPSTATE_ENB), %g2
189	wrhpr %g2, %hpstate
190
191	rd %asr26, %g1
192	srlx %g1, 8, %g1
193	and %g1, 0x1f, %g5 ! %g5 - current cpu id
194	inc %g5 ! number from 1..32
195
196	#if FOR_ZEUS /* { */
197	local1:
198	rd %pc, %g6
199	add %g6, hv_info - local1, %g6
200	ldx [%g6], %g1 ! Mem base
201	ldx [%g6+8], %g2 ! Mem size
202	ldx [%g6+16], %g3 ! Machine description location
203	ldx [%g6+24], %g4 ! Hypervisor ROM location
204	#else /* } { */
205	setx MEMBASE, %g6, %g1 ! Mem base XXX
206	setx MEMSIZE, %g6, %g2 ! Mem size XXX
207	setx HVPD, %g6, %g3 ! Partition Description
208	setx HV, %g6, %g4
209
210	#endif /* } */
211
212	sub %g2, LOCK_SIZE, %g2 ! Hide lock location from HV
213	add %g1, %g2, %g7 ! Addr of lock location
214
215	ldx [%g7], %g6
216	brnz %g6, .slave_entry
217	nop
218
219	casxa [%g7]ASI_N, %g6, %g5
220	cmp %g6, %g5
221	be,pt %xcc, .master_entry
222	nop
223
224
225	/*
226	* Slave
227	*/
228
229	.slave_entry:
230	1: ldx [%g7], %g5
231	cmp %g5, -1
232	bne,pn %xcc, 1b ! wait for copy to complete
233	nop
234
235	add %g4, 0x30, %g4 ! Slave entry point
236	jmp %g4
237	nop
238
239
240	/*
241	* Master
242	*/
243
244	.master_entry:
245	/* IDLE all of the other strands */
246	rd %asr26, %g6
247	srlx %g6, 8, %g6
248	and %g6, 0x1f, %g6 ! %g6 - current strand id
249
250	setx 0x9800000800, %g4, %g5 ! int_vec_dis address
251	mov 31, %g1
252	1: cmp %g1, %g6
253	be,pn %xcc, 2f ! skip our strand
254	nop
255
256	mov 2, %g2 ! IDLE command
257	sllx %g2, 16, %g2
258	sllx %g1, 8, %g3 ! target strand
259	or %g2, %g3, %g2 ! int_vec_dis value
260	stx %g2, [%g5]
261
262	2: deccc %g1
263	bgeu,pt %xcc, 1b
264	nop
265
266	/* Allow them to continue when they wake up */
267	mov -1, %g1
268	stx %g1, [%g7]
269
270	/*
271	* re-init parameters
272	*/
273
274	#if FOR_ZEUS /* { */
275	local2:
276	rd %pc, %g6
277	add %g6, hv_info - local2, %g6
278	ldx [%g6], %g1 ! Mem base
279	ldx [%g6+8], %g2 ! Mem size
280	ldx [%g6+16], %g3 ! Machine description location
281	ldx [%g6+24], %g6 ! Hypervisor ROM location
282	#else /* } { */
283	setx MEMBASE, %g6, %g1 ! Mem base XXX
284	setx MEMSIZE, %g6, %g2 ! Mem size XXX
285	setx HVPD, %g6, %g3 ! Partition Description
286	setx HV, %g4, %g6
287	#endif /* } */
288
289	! %g4 = cpustartset
290	mov -1, %g4
291	srl %g4, 0, %g4 ! %g4 now contains 0xffff.ffff
292
293	! %g5 = phys mem - only used for scrubbing on real HW so we can use 0x0
294	mov %g0, %g5
295
296	sub %g2, LOCK_SIZE, %g2 ! Hide lock
297
298	add %g6, 0x20, %g6
299	jmp %g6
300	nop
301	SET_SIZE(start_reset)
302
303
304
305	ENTRY_NP(rtrap)
306	ta 0x1
307	SET_SIZE(rtrap)
308
309
310
311	! %g1 contains trap# to revector to
312	ENTRY_NP(revec)
313	rdhpr %htba, %g2
314	sllx %g1, 5, %g1
315	add %g2, %g1, %g2
316	jmp %g2
317	wrhpr %g0, (HPSTATE_HPRIV \| HPSTATE_ENB), %hpstate
318	SET_SIZE(revec)
319
320	!! KEEP THIS AT THE END
321	.align 0x100