[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / ontario / include / fire / fire.h

/*
* ========== Copyright Header Begin ==========================================
*
* Hypervisor Software File: fire.h
* 
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* 
*  - Do no alter or remove copyright notices
* 
*  - Redistribution and use of this software in source and binary forms, with 
*    or without modification, are permitted provided that the following 
*    conditions are met: 
* 
*  - Redistribution of source code must retain the above copyright notice, 
*    this list of conditions and the following disclaimer.
* 
*  - Redistribution in binary form must reproduce the above copyright notice,
*    this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution. 
* 
*    Neither the name of Sun Microsystems, Inc. or the names of contributors 
* may be used to endorse or promote products derived from this software 
* without specific prior written permission. 
* 
*     This software is provided "AS IS," without a warranty of any kind. 
* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, 
* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN 
* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR 
* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR 
* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN 
* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR 
* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE 
* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, 
* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF 
* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* 
* You acknowledge that this software is not designed, licensed or
* intended for use in the design, construction, operation or maintenance of
* any nuclear facility. 
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _FIRE_FIRE_H
#define	_FIRE_FIRE_H

#pragma ident	"@(#)fire.h	1.9	07/07/17 SMI"


#ifdef __cplusplus
extern "C" {
#endif

#include <support.h>

#define	FIRE_A_AID	(0x1e)
#define	FIRE_B_AID	(FIRE_A_AID+1)

#define	FIRE_VINO_MIN	(FIRE_A_AID << FIRE_DEVINO_SHIFT)
#define	FIRE_VINO_MAX	((FIRE_B_AID << FIRE_DEVINO_SHIFT) | FIRE_DEVINO_MASK)

#define	NFIREDEVINO		(64)
#define	FIRE_DEVINO_MASK	(NFIREDEVINO - 1)
#define	FIRE_DEVINO_SHIFT	6

#define	FIRE_EQ2INO(n)	(24+n)
#define	FIRE_NEQS	36

#define	FIRE_MAX_MSIS	256
#define	FIRE_MSI_MASK	(FIRE_MAX_MSIS - 1)

#define	FIRE_MSIEQNUM_MASK	((1 << 6) - 1)

#define	FIRE_EQREC_SHIFT	MSIEQ_REC_SHIFT
#define	FIRE_EQREC_SIZE		MSIEQ_REC_SIZE
#define	FIRE_NEQRECORDS		128

#define	FIRE_EQSIZE	(FIRE_NEQRECORDS * FIRE_EQREC_SIZE)
#define	FIRE_EQMASK	(FIRE_EQSIZE - 1)

#define	NFIREINTRCONTROLLERS 4
#define	FIRE_INTR_CNTLR_MASK	((1 << NFIREINTRCONTROLLERS) - 1)
#define	FIRE_INTR_CNTLR_SHIFT	6

#define	INTRSTATE_MASK	0x1

#define	JPID_MASK	0x1f
#define	JPID_SHIFT	26

#define	PCI_CFG_OFFSET_MASK	((1 << 12) - 1)
#define	PCI_CFG_SIZE_MASK	7
#define	PCI_DEV_MASK		(((1 << 24) - 1)^((1 << 8) -1))
#define	PCI_DEV_SHIFT		4

#define	JBUS_PA_SHIFT		43
#define	FIRE_PAGESIZE_8K_SHIFT	13

#define	FIRE_TSB_1K		0
#define	FIRE_TSB_2K		1
#define	FIRE_TSB_4K		2
#define	FIRE_TSB_8K		3
#define	FIRE_TSB_16K		4
#define	FIRE_TSB_32K		5
#define	FIRE_TSB_64K		6
#define	FIRE_TSB_128K		7
#define	FIRE_TSB_256K		8
#define	FIRE_TSB_512K		9

#define	FIRE_TSB_SIZE		FIRE_TSB_256K

#define	FIRE_IOMMU_SIZE(n)	(xULL(1) << ((n) + 10))

#define	IOTTE_SIZE		8
#define	IOTTE_SHIFT		3	/* log2(IOTTE_SIZE) */
#define	IOMMU_PAGESHIFT		13	/* 2K */
#define	IOMMU_PAGESIZE		(xULL(1) << IOMMU_PAGESHIFT)

#define	EQALIGN			(xULL(512) * xULL(1024))	/* 512K Align */
#define	EQ_MAX_SIZE		(FIRE_NEQS * FIRE_EQSIZE)
#define	IOMMU_EQ_RESERVE	((EQ_MAX_SIZE + EQALIGN - 1) & ~(EQALIGN - 1))

#define	IOMMU_SPACE		(FIRE_IOMMU_SIZE(FIRE_TSB_SIZE) << \
				    IOMMU_PAGESHIFT)
/*
 * We carve out a 512K aligned chunk (IOMMU_EQ_RESERVE) of the DVMA range
 * for MSI Event Queues. So we make sure the max idx a guest can pass for
 * a map call doesn't trample on the event queues.
 */
#define	IOTSB_INDEX_MAX		(((IOMMU_SPACE - IOMMU_EQ_RESERVE) >> \
				    IOMMU_PAGESHIFT) - 1)
#define	IOTSB_SIZE		((IOMMU_SPACE/IOMMU_PAGESIZE) * IOTTE_SIZE)

#define	FIRE_IOTTE_V_SHIFT	63
#define	FIRE_IOTTE_W_SHIFT	1
#define	FIRE_INTMR_V_SHIFT	31
#define	FIRE_INTMR_MDO_MODE_SHIFT 63
#define	FIRE_MSIMR_V_SHIFT	63
#define	FIRE_MSIMR_EQWR_N_SHIFT	62
#define	FIRE_MSGMR_V_SHIFT	63
#define	FIRE_EQREC_TYPE_SHIFT	56
#define	FIRE_EQCCR_E2I_SHIFT	47
#define	FIRE_EQCCR_COVERR	57
#define	FIRE_EQCSR_EN_SHIFT	44
#define	FIRE_EQCSR_ENOVERR	57

#define	FIRE_IO_TTE(x)	 ((x) | (1ull << FIRE_IOTTE_V_SHIFT)	\
			    | (1ull << FIRE_IOTTE_W_SHIFT))
#define	FIRE_DVMA_RANGE_MAX	(xULL(1) << 32)

#define	MSI_EQ_BASE_BYPASS_ADDR	(0xfffc000000000000LL)

#define	FIRE_INTR_IDLE		0
#define	FIRE_INTR_RECEIVED	3


#define	MSIEQ_RID_SHIFT	16
#define	MSIEQ_RID_SIZE_BITS 16

#define	MSIEQ_TID_SHIFT	16
#define	MSIEQ_TID_SIZE_BITS 8

#define	MSIEQ_MSG_RT_CODE_SHIFT 56
#define	MSIEQ_MSG_RT_CODE_SIZE_BITS 3

#define	MSIEQ_DATA_SHIFT	16
#define	MSIEQ_DATA_SIZE_BITS 16

#define	MSIEQ_MSG_CODE_SHIFT	0
#define	MSIEQ_MSG_CODE_SIZE_BITS 8

#define	PCIE_PME_MSG		0x18
#define	PCIE_PME_ACK_MSG	0x1b
#define	PCIE_CORR_MSG		0x30
#define	PCIE_NONFATAL_MSG	0x31
#define	PCIE_FATAL_MSG		0x33

#define	FIRE_CORR_OFF		0x00
#define	FIRE_NONFATAL_OFF	0x08
#define	FIRE_FATAL_OFF		0x10
#define	FIRE_PME_OFF		0x18
#define	FIRE_PME_ACK_OFF	0x20

#define	FIRE_MMU_CSR_TE		(1 << 0)	/* Translation Enable */
#define	FIRE_MMU_CSR_BE		(1 << 1)	/* Bypass Enable */
#define	FIRE_MMU_CSR_CM		(3 << 8)	/* Cache Mode */
#define	FIRE_MMU_CSR_SE		(1 << 10)	/* Snoop Enable */

#define	FIRE_MMU_CSR_VALUE	(FIRE_MMU_CSR_TE |\
				FIRE_MMU_CSR_BE |\
				FIRE_MMU_CSR_CM |\
				FIRE_MMU_CSR_SE)

#define	FIRE_IOMMU_BYPASS_BASE	(0xffffc000000000000LL)
#define	FIRE_JBUS_ID_MR_MASK	0xf
#define	FIRE_REV_1		0x1
#define	FIRE_REV_2_0		0x3
#define	FIRE_REV_2_1		0x4

#define	FIRE_TLU_CTL_NPWR_EN	0x100000
#define	FIRE_TLU_STS_STATUS_MASK	0xf
#define	FIRE_TLU_STS_STATUS_DATA_LINK_ACTIVE	0x4

#ifdef __cplusplus
}
#endif

#endif /* _FIRE_FIRE_H */
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* Hypervisor Software File: fire.h
	5	*
	6	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	7	*
	8	* - Do no alter or remove copyright notices
	9	*
	10	* - Redistribution and use of this software in source and binary forms, with
	11	* or without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistribution of source code must retain the above copyright notice,
	15	* this list of conditions and the following disclaimer.
	16	*
	17	* - Redistribution in binary form must reproduce the above copyright notice,
	18	* this list of conditions and the following disclaimer in the
	19	* documentation and/or other materials provided with the distribution.
	20	*
	21	* Neither the name of Sun Microsystems, Inc. or the names of contributors
	22	* may be used to endorse or promote products derived from this software
	23	* without specific prior written permission.
	24	*
	25	* This software is provided "AS IS," without a warranty of any kind.
	26	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
	27	* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
	28	* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
	29	* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
	30	* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
	31	* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
	32	* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
	33	* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
	34	* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
	35	* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
	36	* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
	37	*
	38	* You acknowledge that this software is not designed, licensed or
	39	* intended for use in the design, construction, operation or maintenance of
	40	* any nuclear facility.
	41	*
	42	* ========== Copyright Header End ============================================
	43	*/
	44	/*
	45	* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
	46	* Use is subject to license terms.
	47	*/
	48
	49	#ifndef _FIRE_FIRE_H
	50	#define _FIRE_FIRE_H
	51
	52	#pragma ident "@(#)fire.h 1.9 07/07/17 SMI"
	53
	54
	55	#ifdef __cplusplus
	56	extern "C" {
	57	#endif
	58
	59	#include <support.h>
	60
	61	#define FIRE_A_AID (0x1e)
	62	#define FIRE_B_AID (FIRE_A_AID+1)
	63
	64	#define FIRE_VINO_MIN (FIRE_A_AID << FIRE_DEVINO_SHIFT)
65	#define FIRE_VINO_MAX ((FIRE_B_AID << FIRE_DEVINO_SHIFT) \| FIRE_DEVINO_MASK)
66
67	#define NFIREDEVINO (64)
68	#define FIRE_DEVINO_MASK (NFIREDEVINO - 1)
69	#define FIRE_DEVINO_SHIFT 6
70
71	#define FIRE_EQ2INO(n) (24+n)
72	#define FIRE_NEQS 36
73
74	#define FIRE_MAX_MSIS 256
75	#define FIRE_MSI_MASK (FIRE_MAX_MSIS - 1)
76
77	#define FIRE_MSIEQNUM_MASK ((1 << 6) - 1)
78
79	#define FIRE_EQREC_SHIFT MSIEQ_REC_SHIFT
80	#define FIRE_EQREC_SIZE MSIEQ_REC_SIZE
81	#define FIRE_NEQRECORDS 128
82
83	#define FIRE_EQSIZE (FIRE_NEQRECORDS * FIRE_EQREC_SIZE)
84	#define FIRE_EQMASK (FIRE_EQSIZE - 1)
85
86	#define NFIREINTRCONTROLLERS 4
87	#define FIRE_INTR_CNTLR_MASK ((1 << NFIREINTRCONTROLLERS) - 1)
88	#define FIRE_INTR_CNTLR_SHIFT 6
89
90	#define INTRSTATE_MASK 0x1
91
92	#define JPID_MASK 0x1f
93	#define JPID_SHIFT 26
94
95	#define PCI_CFG_OFFSET_MASK ((1 << 12) - 1)
96	#define PCI_CFG_SIZE_MASK 7
97	#define PCI_DEV_MASK (((1 << 24) - 1)^((1 << 8) -1))
98	#define PCI_DEV_SHIFT 4
99
100	#define JBUS_PA_SHIFT 43
101	#define FIRE_PAGESIZE_8K_SHIFT 13
102
103	#define FIRE_TSB_1K 0
104	#define FIRE_TSB_2K 1
105	#define FIRE_TSB_4K 2
106	#define FIRE_TSB_8K 3
107	#define FIRE_TSB_16K 4
108	#define FIRE_TSB_32K 5
109	#define FIRE_TSB_64K 6
110	#define FIRE_TSB_128K 7
111	#define FIRE_TSB_256K 8
112	#define FIRE_TSB_512K 9
113
114	#define FIRE_TSB_SIZE FIRE_TSB_256K
115
116	#define FIRE_IOMMU_SIZE(n) (xULL(1) << ((n) + 10))
117
118	#define IOTTE_SIZE 8
119	#define IOTTE_SHIFT 3 /* log2(IOTTE_SIZE) */
120	#define IOMMU_PAGESHIFT 13 /* 2K */
121	#define IOMMU_PAGESIZE (xULL(1) << IOMMU_PAGESHIFT)
122
123	#define EQALIGN (xULL(512) * xULL(1024)) /* 512K Align */
124	#define EQ_MAX_SIZE (FIRE_NEQS * FIRE_EQSIZE)
125	#define IOMMU_EQ_RESERVE ((EQ_MAX_SIZE + EQALIGN - 1) & ~(EQALIGN - 1))
126
127	#define IOMMU_SPACE (FIRE_IOMMU_SIZE(FIRE_TSB_SIZE) << \
128	IOMMU_PAGESHIFT)
129	/*
130	* We carve out a 512K aligned chunk (IOMMU_EQ_RESERVE) of the DVMA range
131	* for MSI Event Queues. So we make sure the max idx a guest can pass for
132	* a map call doesn't trample on the event queues.
133	*/
134	#define IOTSB_INDEX_MAX (((IOMMU_SPACE - IOMMU_EQ_RESERVE) >> \
135	IOMMU_PAGESHIFT) - 1)
136	#define IOTSB_SIZE ((IOMMU_SPACE/IOMMU_PAGESIZE) * IOTTE_SIZE)
137
138	#define FIRE_IOTTE_V_SHIFT 63
139	#define FIRE_IOTTE_W_SHIFT 1
140	#define FIRE_INTMR_V_SHIFT 31
141	#define FIRE_INTMR_MDO_MODE_SHIFT 63
142	#define FIRE_MSIMR_V_SHIFT 63
143	#define FIRE_MSIMR_EQWR_N_SHIFT 62
144	#define FIRE_MSGMR_V_SHIFT 63
145	#define FIRE_EQREC_TYPE_SHIFT 56
146	#define FIRE_EQCCR_E2I_SHIFT 47
147	#define FIRE_EQCCR_COVERR 57
148	#define FIRE_EQCSR_EN_SHIFT 44
149	#define FIRE_EQCSR_ENOVERR 57
150
151	#define FIRE_IO_TTE(x) ((x) \| (1ull << FIRE_IOTTE_V_SHIFT) \
152	\| (1ull << FIRE_IOTTE_W_SHIFT))
153	#define FIRE_DVMA_RANGE_MAX (xULL(1) << 32)
154
155	#define MSI_EQ_BASE_BYPASS_ADDR (0xfffc000000000000LL)
156
157	#define FIRE_INTR_IDLE 0
158	#define FIRE_INTR_RECEIVED 3
159
160
161	#define MSIEQ_RID_SHIFT 16
162	#define MSIEQ_RID_SIZE_BITS 16
163
164	#define MSIEQ_TID_SHIFT 16
165	#define MSIEQ_TID_SIZE_BITS 8
166
167	#define MSIEQ_MSG_RT_CODE_SHIFT 56
168	#define MSIEQ_MSG_RT_CODE_SIZE_BITS 3
169
170	#define MSIEQ_DATA_SHIFT 16
171	#define MSIEQ_DATA_SIZE_BITS 16
172
173	#define MSIEQ_MSG_CODE_SHIFT 0
174	#define MSIEQ_MSG_CODE_SIZE_BITS 8
175
176	#define PCIE_PME_MSG 0x18
177	#define PCIE_PME_ACK_MSG 0x1b
178	#define PCIE_CORR_MSG 0x30
179	#define PCIE_NONFATAL_MSG 0x31
180	#define PCIE_FATAL_MSG 0x33
181
182	#define FIRE_CORR_OFF 0x00
183	#define FIRE_NONFATAL_OFF 0x08
184	#define FIRE_FATAL_OFF 0x10
185	#define FIRE_PME_OFF 0x18
186	#define FIRE_PME_ACK_OFF 0x20
187
188	#define FIRE_MMU_CSR_TE (1 << 0) /* Translation Enable */
189	#define FIRE_MMU_CSR_BE (1 << 1) /* Bypass Enable */
190	#define FIRE_MMU_CSR_CM (3 << 8) /* Cache Mode */
191	#define FIRE_MMU_CSR_SE (1 << 10) /* Snoop Enable */
192
193	#define FIRE_MMU_CSR_VALUE (FIRE_MMU_CSR_TE \|\
194	FIRE_MMU_CSR_BE \|\
195	FIRE_MMU_CSR_CM \|\
196	FIRE_MMU_CSR_SE)
197
198	#define FIRE_IOMMU_BYPASS_BASE (0xffffc000000000000LL)
199	#define FIRE_JBUS_ID_MR_MASK 0xf
200	#define FIRE_REV_1 0x1
201	#define FIRE_REV_2_0 0x3
202	#define FIRE_REV_2_1 0x4
203
204	#define FIRE_TLU_CTL_NPWR_EN 0x100000
205	#define FIRE_TLU_STS_STATUS_MASK 0xf
206	#define FIRE_TLU_STS_STATUS_DATA_LINK_ACTIVE 0x4
207
208	#ifdef __cplusplus
209	}
210	#endif
211
212	#endif /* _FIRE_FIRE_H */