Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / ontario / include / platform / asi.h
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1/*
2* ========== Copyright Header Begin ==========================================
3*
4* Hypervisor Software File: asi.h
5*
6* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
7*
8* - Do no alter or remove copyright notices
9*
10* - Redistribution and use of this software in source and binary forms, with
11* or without modification, are permitted provided that the following
12* conditions are met:
13*
14* - Redistribution of source code must retain the above copyright notice,
15* this list of conditions and the following disclaimer.
16*
17* - Redistribution in binary form must reproduce the above copyright notice,
18* this list of conditions and the following disclaimer in the
19* documentation and/or other materials provided with the distribution.
20*
21* Neither the name of Sun Microsystems, Inc. or the names of contributors
22* may be used to endorse or promote products derived from this software
23* without specific prior written permission.
24*
25* This software is provided "AS IS," without a warranty of any kind.
26* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
27* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
28* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
29* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
30* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
31* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
32* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
33* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
34* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
35* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
36* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
37*
38* You acknowledge that this software is not designed, licensed or
39* intended for use in the design, construction, operation or maintenance of
40* any nuclear facility.
41*
42* ========== Copyright Header End ============================================
43*/
44/*
45 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
46 * Use is subject to license terms.
47 */
48
49#ifndef _PLATFORM_ASI_H
50#define _PLATFORM_ASI_H
51
52#pragma ident "@(#)asi.h 1.1 07/05/03 SMI"
53
54/*
55 * Niagara1 ASI definitions
56 */
57
58#ifdef __cplusplus
59extern "C" {
60#endif
61
62#define ASI_SPARC_ERR_EN 0x4b /* Sparc Error enable */
63#define ASI_SPARC_ERR_STATUS 0x4c /* Sparc Error status */
64#define ASI_SPARC_ERR_ADDR 0x4d /* Sparc Error address */
65#define ASI_DTSBBASE_CTX0_PS0 0x31
66#define ASI_DTSBBASE_CTX0_PS1 0x32
67#define ASI_DTSB_CONFIG_CTX0 0x33
68#define ASI_ITSBBASE_CTX0_PS0 0x35
69#define ASI_ITSBBASE_CTX0_PS1 0x36
70#define ASI_ITSB_CONFIG_CTX0 0x37
71#define ASI_DTSBBASE_CTXN_PS0 0x39
72#define ASI_DTSBBASE_CTXN_PS1 0x3a
73#define ASI_DTSB_CONFIG_CTXN 0x3b
74#define ASI_ITSBBASE_CTXN_PS0 0x3d
75#define ASI_ITSBBASE_CTXN_PS1 0x3e
76#define ASI_ITSB_CONFIG_CTXN 0x3f
77
78#define ASI_IMMU_TSB_PS0 0x51 /* IMMU TSB PS0 */
79#define ASI_IMMU_TSB_PS1 0x52 /* IMMU TSB PS1 */
80
81#define ASI_DMMU_TSB_PS0 0x59 /* DMMU TSB PS0 */
82#define ASI_DMMU_TSB_PS1 0x5a /* DMMU TSB PS1 */
83#define ASI_DTLB_DIRECTPTR 0x5b /* DMMU direct pointer */
84
85#ifdef __cplusplus
86}
87#endif
88
89#endif /* _PLATFORM_ASI_H */