[OpenSPARC-T2-SAM] / legion / src / include / xicache.h

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: xicache.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
* 
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
* 
* The above named program is distributed in the hope that it will be 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
* 
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef	_XICACHE_H_
#define	_XICACHE_H_

#pragma ident	"@(#)xicache.h	1.24	06/12/07 SMI"

#ifdef	__cplusplus
extern "C" {
#endif

/*
 * xicache.h
 *
 * The Xicache holds pre-decoded instructions for the
 * core of the simulator, for future eXecution, it
 * is also used as the core support for breakpoints
 * and other code insertion events. Ultimately
 * other tracing tools etc. may also be inserted as
 * functions to be interposed via the e-cache
 * between the decoded instruction form and the
 * main execution routine.
 *
 * In this way a call path for a certain instruction
 * might look like;
 *
 * stat_gather() ->
 *		breakpoint_check()->
 *				instruction();
 *
 * Thus augmentation can be done on a per-instruction
 * basis, but without having to pay the test cost
 * in the main execution loop.
 *
 */

#if 0 /* } in simcore.h instead */
typedef struct XICACHE_INSTN xicache_instn_t;
typedef struct XICACHE_LINE xicache_line_t;
typedef struct XICACHE xicache_t;
typedef	union DECODED_INSTN decoded_instn_t;
#endif	/* } */

#include "basics.h"


#if PERFORMANCE_CHECK /* { */
/* No XIC_HIT - inferred using (ICOUNT - xic_misses). */
#define	XIC_MISS(sp)	do { (sp)->xic_misses++; } while (0)
#define	XIC_FLUSH(sp)	do { (sp)->xic_flushes++; } while (0)
#else
#define	XIC_MISS(sp)	do { } while (0)
#define	XIC_FLUSH(sp)	do { } while (0)
#endif	/* } */

union DECODED_INSTN {
	struct {
		uint16_t	rs1o;
		sint16_t	simm16;
		uint16_t	rdo;
	} rri;		/* register + immediate -> register */

	struct {
		uint16_t	rs1o;
		uint16_t	rs2o;
		uint16_t	rdo;  /* several MACROs expect rdo to be here */
		uint16_t	rs3o; /* for 'reg + reg + reg -> reg' cases */
	} rrr;		/* register + register (and maybe + register) -> register */

	struct {
		sint32_t	simm32;
		uint16_t	rdo;
	} rsimm32;

	struct {
		uint32_t	uimm32;
		uint16_t	rdo;
	} ruimm32;

	struct {
		uint16_t	rs1o;
		sint32_t	offset32;
	} breg;		/* branch on register value */

	struct	{
		sint32_t	offset32;
		uint8_t		fcc;	/* fcc number for FBPfcc */
	} brcond;

	struct {
		uint16_t	rs1o;
		sint16_t	simm16;
		uint8_t		rd_num;
		uint8_t		asi_num;
		uint8_t		op;
	} sp_asi_imm;	/* format for sparc asi ld/st/cas imm form instns */

	struct {
		uint16_t	rs1o;
		uint16_t	rs2o;
		uint8_t		rd_num;
		uint8_t		asi_num;
		uint8_t		op;
	} sp_asi_rrr;	/* format for sparc asi ld/st/cas rrr form instns */


	struct {
		uint16_t	rs1o;
		uint16_t	rs2o;
		uint8_t		cond;	/* 4 bits */
		uint8_t		cc;	/* =0 for icc, 1 for xcc */
	} sp_trap_rrr;	/* format for sparc trap instn */

	struct {
		uint16_t	rs1o;
		sint16_t	simm16;
		uint8_t		cond;	/* 4 bits */
		uint8_t		cc;	/* =0 for icc, 1 for xcc */
	} sp_trap_imm;	/* format for sparc trap instn */

	struct {
		uint8_t		cond;	/* 4 bits */
		uint8_t		cc;	/* =0 for icc, 1 for xcc */
		uint16_t	rs2o;
		uint16_t	rdo;
	} sp_movcc_rr;	/* format for sparc movcc instn */

	struct {
		uint8_t		cond;	/* 4 bits */
		uint8_t		cc;	/* =0 for icc, 1 for xcc */
		sint16_t	simm16;
		uint16_t	rdo;
	} sp_movcc_imm;	/* format for sparc movcc instn */

	sint32_t	call_off32;	/* offset for call instn - NOTE: must be signed !*/

	uint32_t	ill_reason;	/* coded reason for why instruction is illegal*/

	uint32_t	misc_bits;	/* for all those other instns which need additional stuff */
};


	/*
	 * String decoding for why instruction is illegal (xcip->ill_reason)
	 *
	 * Needs to go away - FIXME
	 */

extern char * illegal_reason_str[];


struct XICACHE_INSTN {
	void 	        (*exec_funcp)(simcpu_t * sp, xicache_instn_t *);
	uint32_t	rawi;	/* FIXME: raw instruction encoding ?! */
	decoded_instn_t	di;
};


	/**/
	/* The non-dynamic E-cache versions - far far more efficient*/
	/**/
#define	XICACHE_SIZE_BITS		20	/* 1MB of decoded instructions */

#define	XICACHE_LINE_SIZE_BITS		13	/* allow each chunk to be 8K */
#define	XICACHE_LINE_SIZE		(1ULL<<XICACHE_LINE_SIZE_BITS)
#define	XICACHE_LINE_OFFSET_MASK	(XICACHE_LINE_SIZE-1)
#define	XICACHE_LINES_BITS		(XICACHE_SIZE_BITS-XICACHE_LINE_SIZE_BITS)
#define	XICACHE_NUM_LINES		(1ULL<<XICACHE_LINES_BITS)
#define	XICACHE_LINE_MASK		(XICACHE_NUM_LINES-1)
#define	XICACHE_LINE_INSTRS		(XICACHE_LINE_SIZE >> 2)

	/* define the instruction cache to match the same number of lines */
#define	XICACHE_INSTR_SHIFT_BITS	2
#define	XICACHE_INSTR_ALIGN_MASK	((1ULL<<XICACHE_INSTR_SHIFT_BITS)-1ULL)
#define	XICACHE_NUM_INSTRS		(1ULL<<(XICACHE_LINE_SIZE_BITS-XICACHE_INSTR_SHIFT_BITS+XICACHE_LINES_BITS))
#define	XICACHE_NUM_INSTR_MASK		(XICACHE_NUM_INSTRS-1)

#define	XICACHE_TAG_PURE_MASK		(~XICACHE_LINE_OFFSET_MASK)

	/* FIXME: presumes RISC architectures with fixed alignment requirements */
#define	XICACHE_TAG_MASK		(XICACHE_TAG_PURE_MASK|XICACHE_INSTR_ALIGN_MASK)


struct XICACHE_LINE {
	tvaddr_t	tag;
#define	XC_INVALID_TAG	(~(uint64_t)0)
	uint64_t	memoryoffset;
};


struct XICACHE {
	xicache_instn_t	instn[ XICACHE_NUM_INSTRS ];
	xicache_line_t	line[ XICACHE_NUM_LINES ];
};


#define	XICACHE_DEAD_MEMOFF	1ull
/* Pick a real illegal instruction!! */
#define	XICACHE_DEAD_INSTN	0x02000000


	/*
	 * X cache support functions
	 */

extern xicache_t * xicache_alloc(simcpu_t * sp);
extern void xicache_instn_flush(simcpu_t * sp);
extern void xicache_trans_flush(simcpu_t * sp);
extern void xicache_clobber_line_decodes(simcpu_t * sp, tvaddr_t tagva);


	/*
	 * Macros for setting and using the decoded
	 * instruction form types
	 */


#define	RegPtr(_sp,_off)	(((uint8_t*)&(_sp->intreg[0])) + (_off))
#define	UReg(_sp,_off)		(*(uint64_t*)RegPtr(_sp, _off))
#define	SReg(_sp,_off)		(*(sint64_t*)RegPtr(_sp, _off))
#define FP32Reg(_sp,_off)	(*(uint32_t*)RegPtr(_sp, _off))

	/* Simple version for when real register numbers are required */
#define	IReg(_n)		(sp->intreg[_n])


	/* Macros for the decoded instruction implementations */
	/* assumes simcpu_t * sp, and xicache_instn_t * xcip */

#define	Rpc	(sp->pc)
#define	Rnpc	(sp->npc)

#define	Rdest	UReg( sp, xcip->di.rri.rdo )
#define	Rsrc1	UReg( sp, xcip->di.rri.rs1o )
#define	Rsrc2	UReg( sp, xcip->di.rrr.rs2o )
#define	Rsrc3	UReg( sp, xcip->di.rrr.rs3o )
#define	SRdest	SReg( sp, xcip->di.rri.rdo )
#define	SRsrc1	SReg( sp, xcip->di.rri.rs1o )
#define	SRsrc2	SReg( sp, xcip->di.rrr.rs2o )
#define	F32src1	FP32Reg( sp, xcip->di.rri.rs1o )
#define	F32src2	FP32Reg( sp, xcip->di.rrr.rs2o )
#define	F32src3	FP32Reg( sp, xcip->di.rrr.rs3o )

#define	F64src1	Rsrc1
#define	F64src2	Rsrc2
#define	F64src3	Rsrc3
#define	F32dest	FP32Reg( sp, xcip->di.rri.rdo )
#define	F64dest	Rdest

#define	Simm16	((sint64_t)(xcip->di.rri.simm16))
#define	Simm32	((sint64_t)(xcip->di.rsimm32.simm32))
#define	Uimm32	((uint64_t)(xcip->di.ruimm32.uimm32))

#define	SBRoffset32	((sint64_t)(xcip->di.brcond.offset32))
#define	SBRfcc		((sint64_t)(xcip->di.brcond.fcc))

		/* Offset for branch on reg value */
#define	SBRreg_off32	((sint64_t)(xcip->di.breg.offset32))

	/* Annoyingly undo the pointer encodings for raw reg nums */

#define	Zero_Reg(_offset)	((_offset)==0)

#define	Rdest_num	(xcip->di.rri.rdo / sizeof(sp->intreg[0]))
#define	Rsrc1_num	(xcip->di.rri.rs1o / sizeof(sp->intreg[0]))
#define	Rsrc2_num	(xcip->di.rri.rs2o / sizeof(sp->intreg[0]))

#define	Misc32		(xcip->di.misc_bits)


	/*
	 * Macros for the decoder to write to the xicache
	 * decoded forms of instructions.
	 */

#define	IReg_Offset(_rn)	((unsigned)(uint64_t)&(((simcpu_t *)0)->intreg[(_rn)]))

#define	SET_OP_RD(_n)		do { xcip->di.rri.rdo = IReg_Offset( _n ); } while (0)
#define	SET_OP_RS1(_n)		do { xcip->di.rri.rs1o = IReg_Offset( _n ); } while (0)
#define	SET_OP_RS2(_n)		do { xcip->di.rrr.rs2o = IReg_Offset( _n ); } while (0)
#define	SET_OP_RS3(_n)		do { xcip->di.rrr.rs3o = IReg_Offset( _n ); } while (0)

	/* Index value is for smallest FP register size */
#define	FPReg_Offset(_rn)	((unsigned)(uint64_t)&(((simcpu_t *)0)->fpreg.s32[(_rn)]))

#define	SET_OP_FPRD(_n)		do { xcip->di.rri.rdo = FPReg_Offset( _n ); } while (0)
#define	SET_OP_FPRS1(_n)	do { xcip->di.rri.rs1o = FPReg_Offset( _n ); } while (0)
#define	SET_OP_FPRS2(_n)	do { xcip->di.rrr.rs2o = FPReg_Offset( _n ); } while (0)
#define	SET_OP_FPRS3(_n)	do { xcip->di.rrr.rs3o = FPReg_Offset( _n ); } while (0)

#define	SET_OP_SIMM16(_n)	do { xcip->di.rri.simm16 = _n; } while (0)
#define	SET_OP_SIMM32(_n)	do { xcip->di.rsimm32.simm32 = _n; } while (0)
#define	SET_OP_UIMM32(_n)	do { xcip->di.ruimm32.uimm32 = _n; } while (0)

#define	SET_OP_BREGOFF32(_n)	do { xcip->di.breg.offset32 = (_n); } while (0)
#define	SET_OP_BROFF32(_n)	do { xcip->di.brcond.offset32 = (_n); } while (0)
#define	SET_OP_BR_FCC(_n)	do { xcip->di.brcond.fcc = (_n); } while (0)

#define	SET_OP_ASI_OP(_n)	do { xcip->di.sp_asi_imm.op = (_n) ; } while (0)
#define	SET_OP_ASI_RD(_n)	do { xcip->di.sp_asi_imm.rd_num = (_n) ; } while (0)
#define	SET_OP_ASI_FPRD(_n)	do { xcip->di.sp_asi_imm.rd_num = (_n) ; } while (0)
#define	SET_OP_ASI_NUM(_n)	do { xcip->di.sp_asi_imm.asi_num = (_n) ; } while (0)

#define	ASI_Rdest	(xcip->di.sp_asi_imm.rd_num)
#define	ASI_num		(xcip->di.sp_asi_imm.asi_num)
#define	ASI_op		(xcip->di.sp_asi_imm.op)

#define	SET_OP_TRAP_CC(_cc)	do { xcip->di.sp_trap_rrr.cc = (_cc); } while (0)
#define	SET_OP_TRAP_COND(_c)	do { xcip->di.sp_trap_rrr.cond = (_c); } while (0)

#define	TRAP_cc			(xcip->di.sp_trap_rrr.cc)
#define	TRAP_cond		(xcip->di.sp_trap_rrr.cond)

#define	SET_OP_MOVCC_CC(_cc)	do { xcip->di.sp_movcc_rr.cc = (_cc); } while (0)
#define	SET_OP_MOVCC_COND(_c)	do { xcip->di.sp_movcc_rr.cond = (_c); } while (0)

#define	MOVCC_cc		(xcip->di.sp_movcc_rr.cc)
#define	MOVCC_cond		(xcip->di.sp_movcc_rr.cond)

	/*
	 * When an illegal instruction is encountered we set an internal
	 * code to give ourselves a clue as to why the decoder thought it
	 * was illegal
	 */

#define	SET_OP_ILL_REASON(_r)	do { xcip->di.ill_reason = (uint32_t)(_r); } while (0)

	/*
	 * Instructions for which we have no other obvious encoding
	 * get to have a custom 32 bit field for their own bit encodings
	 */

#define	SET_OP_MISC_BITS(_b)	do { xcip->di.misc_bits = (uint32_t)(_b); } while (0)

#ifdef	__cplusplus
}
#endif

#endif	/* _XICACHE_H_ */
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: xicache.h
	5	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	6	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
	7	*
	8	* The above named program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public
	10	* License version 2 as published by the Free Software Foundation.
	11	*
	12	* The above named program is distributed in the hope that it will be
	13	* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public
	18	* License along with this work; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
	20	*
	21	* ========== Copyright Header End ============================================
	22	*/
	23	/*
	24	* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
	25	* Use is subject to license terms.
	26	*/
	27
	28	#ifndef _XICACHE_H_
	29	#define _XICACHE_H_
	30
	31	#pragma ident "@(#)xicache.h 1.24 06/12/07 SMI"
	32
	33	#ifdef __cplusplus
	34	extern "C" {
	35	#endif
	36
	37	/*
	38	* xicache.h
	39	*
	40	* The Xicache holds pre-decoded instructions for the
	41	* core of the simulator, for future eXecution, it
	42	* is also used as the core support for breakpoints
	43	* and other code insertion events. Ultimately
	44	* other tracing tools etc. may also be inserted as
	45	* functions to be interposed via the e-cache
	46	* between the decoded instruction form and the
	47	* main execution routine.
	48	*
	49	* In this way a call path for a certain instruction
	50	* might look like;
	51	*
	52	* stat_gather() ->
	53	* breakpoint_check()->
	54	* instruction();
	55	*
	56	* Thus augmentation can be done on a per-instruction
	57	* basis, but without having to pay the test cost
	58	* in the main execution loop.
	59	*
	60	*/
	61
	62	#if 0 /* } in simcore.h instead */
	63	typedef struct XICACHE_INSTN xicache_instn_t;
	64	typedef struct XICACHE_LINE xicache_line_t;
65	typedef struct XICACHE xicache_t;
66	typedef union DECODED_INSTN decoded_instn_t;
67	#endif /* } */
68
69	#include "basics.h"
70
71
72	#if PERFORMANCE_CHECK /* { */
73	/* No XIC_HIT - inferred using (ICOUNT - xic_misses). */
74	#define XIC_MISS(sp) do { (sp)->xic_misses++; } while (0)
75	#define XIC_FLUSH(sp) do { (sp)->xic_flushes++; } while (0)
76	#else
77	#define XIC_MISS(sp) do { } while (0)
78	#define XIC_FLUSH(sp) do { } while (0)
79	#endif /* } */
80
81	union DECODED_INSTN {
82	struct {
83	uint16_t rs1o;
84	sint16_t simm16;
85	uint16_t rdo;
86	} rri; /* register + immediate -> register */
87
88	struct {
89	uint16_t rs1o;
90	uint16_t rs2o;
91	uint16_t rdo; /* several MACROs expect rdo to be here */
92	uint16_t rs3o; /* for 'reg + reg + reg -> reg' cases */
93	} rrr; /* register + register (and maybe + register) -> register */
94
95	struct {
96	sint32_t simm32;
97	uint16_t rdo;
98	} rsimm32;
99
100	struct {
101	uint32_t uimm32;
102	uint16_t rdo;
103	} ruimm32;
104
105	struct {
106	uint16_t rs1o;
107	sint32_t offset32;
108	} breg; /* branch on register value */
109
110	struct {
111	sint32_t offset32;
112	uint8_t fcc; /* fcc number for FBPfcc */
113	} brcond;
114
115	struct {
116	uint16_t rs1o;
117	sint16_t simm16;
118	uint8_t rd_num;
119	uint8_t asi_num;
120	uint8_t op;
121	} sp_asi_imm; /* format for sparc asi ld/st/cas imm form instns */
122
123	struct {
124	uint16_t rs1o;
125	uint16_t rs2o;
126	uint8_t rd_num;
127	uint8_t asi_num;
128	uint8_t op;
129	} sp_asi_rrr; /* format for sparc asi ld/st/cas rrr form instns */
130
131
132	struct {
133	uint16_t rs1o;
134	uint16_t rs2o;
135	uint8_t cond; /* 4 bits */
136	uint8_t cc; /* =0 for icc, 1 for xcc */
137	} sp_trap_rrr; /* format for sparc trap instn */
138
139	struct {
140	uint16_t rs1o;
141	sint16_t simm16;
142	uint8_t cond; /* 4 bits */
143	uint8_t cc; /* =0 for icc, 1 for xcc */
144	} sp_trap_imm; /* format for sparc trap instn */
145
146	struct {
147	uint8_t cond; /* 4 bits */
148	uint8_t cc; /* =0 for icc, 1 for xcc */
149	uint16_t rs2o;
150	uint16_t rdo;
151	} sp_movcc_rr; /* format for sparc movcc instn */
152
153	struct {
154	uint8_t cond; /* 4 bits */
155	uint8_t cc; /* =0 for icc, 1 for xcc */
156	sint16_t simm16;
157	uint16_t rdo;
158	} sp_movcc_imm; /* format for sparc movcc instn */
159
160	sint32_t call_off32; /* offset for call instn - NOTE: must be signed !*/
161
162	uint32_t ill_reason; /* coded reason for why instruction is illegal*/
163
164	uint32_t misc_bits; /* for all those other instns which need additional stuff */
165	};
166
167
168	/*
169	* String decoding for why instruction is illegal (xcip->ill_reason)
170	*
171	* Needs to go away - FIXME
172	*/
173
174	extern char * illegal_reason_str[];
175
176
177	struct XICACHE_INSTN {
178	void (exec_funcp)(simcpu_t sp, xicache_instn_t *);
179	uint32_t rawi; /* FIXME: raw instruction encoding ?! */
180	decoded_instn_t di;
181	};
182
183
184
185
186	/**/
187	/* The non-dynamic E-cache versions - far far more efficient*/
188	/**/
189	#define XICACHE_SIZE_BITS 20 /* 1MB of decoded instructions */
190
191	#define XICACHE_LINE_SIZE_BITS 13 /* allow each chunk to be 8K */
192	#define XICACHE_LINE_SIZE (1ULL<<XICACHE_LINE_SIZE_BITS)
193	#define XICACHE_LINE_OFFSET_MASK (XICACHE_LINE_SIZE-1)
194	#define XICACHE_LINES_BITS (XICACHE_SIZE_BITS-XICACHE_LINE_SIZE_BITS)
195	#define XICACHE_NUM_LINES (1ULL<<XICACHE_LINES_BITS)
196	#define XICACHE_LINE_MASK (XICACHE_NUM_LINES-1)
197	#define XICACHE_LINE_INSTRS (XICACHE_LINE_SIZE >> 2)
198
199	/* define the instruction cache to match the same number of lines */
200	#define XICACHE_INSTR_SHIFT_BITS 2
201	#define XICACHE_INSTR_ALIGN_MASK ((1ULL<<XICACHE_INSTR_SHIFT_BITS)-1ULL)
202	#define XICACHE_NUM_INSTRS (1ULL<<(XICACHE_LINE_SIZE_BITS-XICACHE_INSTR_SHIFT_BITS+XICACHE_LINES_BITS))
203	#define XICACHE_NUM_INSTR_MASK (XICACHE_NUM_INSTRS-1)
204
205	#define XICACHE_TAG_PURE_MASK (~XICACHE_LINE_OFFSET_MASK)
206
207	/* FIXME: presumes RISC architectures with fixed alignment requirements */
208	#define XICACHE_TAG_MASK (XICACHE_TAG_PURE_MASK\|XICACHE_INSTR_ALIGN_MASK)
209
210
211	struct XICACHE_LINE {
212	tvaddr_t tag;
213	#define XC_INVALID_TAG (~(uint64_t)0)
214	uint64_t memoryoffset;
215	};
216
217
218
219	struct XICACHE {
220	xicache_instn_t instn[ XICACHE_NUM_INSTRS ];
221	xicache_line_t line[ XICACHE_NUM_LINES ];
222	};
223
224
225	#define XICACHE_DEAD_MEMOFF 1ull
226	/* Pick a real illegal instruction!! */
227	#define XICACHE_DEAD_INSTN 0x02000000
228
229
230	/*
231	* X cache support functions
232	*/
233
234	extern xicache_t * xicache_alloc(simcpu_t * sp);
235	extern void xicache_instn_flush(simcpu_t * sp);
236	extern void xicache_trans_flush(simcpu_t * sp);
237	extern void xicache_clobber_line_decodes(simcpu_t * sp, tvaddr_t tagva);
238
239
240
241
242	/*
243	* Macros for setting and using the decoded
244	* instruction form types
245	*/
246
247
248
249	#define RegPtr(_sp,_off) (((uint8_t*)&(_sp->intreg[0])) + (_off))
250	#define UReg(_sp,_off) ((uint64_t)RegPtr(_sp, _off))
251	#define SReg(_sp,_off) ((sint64_t)RegPtr(_sp, _off))
252	#define FP32Reg(_sp,_off) ((uint32_t)RegPtr(_sp, _off))
253
254	/* Simple version for when real register numbers are required */
255	#define IReg(_n) (sp->intreg[_n])
256
257
258	/* Macros for the decoded instruction implementations */
259	/* assumes simcpu_t * sp, and xicache_instn_t * xcip */
260
261	#define Rpc (sp->pc)
262	#define Rnpc (sp->npc)
263
264	#define Rdest UReg( sp, xcip->di.rri.rdo )
265	#define Rsrc1 UReg( sp, xcip->di.rri.rs1o )
266	#define Rsrc2 UReg( sp, xcip->di.rrr.rs2o )
267	#define Rsrc3 UReg( sp, xcip->di.rrr.rs3o )
268	#define SRdest SReg( sp, xcip->di.rri.rdo )
269	#define SRsrc1 SReg( sp, xcip->di.rri.rs1o )
270	#define SRsrc2 SReg( sp, xcip->di.rrr.rs2o )
271	#define F32src1 FP32Reg( sp, xcip->di.rri.rs1o )
272	#define F32src2 FP32Reg( sp, xcip->di.rrr.rs2o )
273	#define F32src3 FP32Reg( sp, xcip->di.rrr.rs3o )
274
275	#define F64src1 Rsrc1
276	#define F64src2 Rsrc2
277	#define F64src3 Rsrc3
278	#define F32dest FP32Reg( sp, xcip->di.rri.rdo )
279	#define F64dest Rdest
280
281	#define Simm16 ((sint64_t)(xcip->di.rri.simm16))
282	#define Simm32 ((sint64_t)(xcip->di.rsimm32.simm32))
283	#define Uimm32 ((uint64_t)(xcip->di.ruimm32.uimm32))
284
285	#define SBRoffset32 ((sint64_t)(xcip->di.brcond.offset32))
286	#define SBRfcc ((sint64_t)(xcip->di.brcond.fcc))
287
288	/* Offset for branch on reg value */
289	#define SBRreg_off32 ((sint64_t)(xcip->di.breg.offset32))
290
291	/* Annoyingly undo the pointer encodings for raw reg nums */
292
293	#define Zero_Reg(_offset) ((_offset)==0)
294
295	#define Rdest_num (xcip->di.rri.rdo / sizeof(sp->intreg[0]))
296	#define Rsrc1_num (xcip->di.rri.rs1o / sizeof(sp->intreg[0]))
297	#define Rsrc2_num (xcip->di.rri.rs2o / sizeof(sp->intreg[0]))
298
299	#define Misc32 (xcip->di.misc_bits)
300
301
302	/*
303	* Macros for the decoder to write to the xicache
304	* decoded forms of instructions.
305	*/
306
307	#define IReg_Offset(_rn) ((unsigned)(uint64_t)&(((simcpu_t *)0)->intreg[(_rn)]))
308
309	#define SET_OP_RD(_n) do { xcip->di.rri.rdo = IReg_Offset( _n ); } while (0)
310	#define SET_OP_RS1(_n) do { xcip->di.rri.rs1o = IReg_Offset( _n ); } while (0)
311	#define SET_OP_RS2(_n) do { xcip->di.rrr.rs2o = IReg_Offset( _n ); } while (0)
312	#define SET_OP_RS3(_n) do { xcip->di.rrr.rs3o = IReg_Offset( _n ); } while (0)
313
314	/* Index value is for smallest FP register size */
315	#define FPReg_Offset(_rn) ((unsigned)(uint64_t)&(((simcpu_t *)0)->fpreg.s32[(_rn)]))
316
317	#define SET_OP_FPRD(_n) do { xcip->di.rri.rdo = FPReg_Offset( _n ); } while (0)
318	#define SET_OP_FPRS1(_n) do { xcip->di.rri.rs1o = FPReg_Offset( _n ); } while (0)
319	#define SET_OP_FPRS2(_n) do { xcip->di.rrr.rs2o = FPReg_Offset( _n ); } while (0)
320	#define SET_OP_FPRS3(_n) do { xcip->di.rrr.rs3o = FPReg_Offset( _n ); } while (0)
321
322	#define SET_OP_SIMM16(_n) do { xcip->di.rri.simm16 = _n; } while (0)
323	#define SET_OP_SIMM32(_n) do { xcip->di.rsimm32.simm32 = _n; } while (0)
324	#define SET_OP_UIMM32(_n) do { xcip->di.ruimm32.uimm32 = _n; } while (0)
325
326	#define SET_OP_BREGOFF32(_n) do { xcip->di.breg.offset32 = (_n); } while (0)
327	#define SET_OP_BROFF32(_n) do { xcip->di.brcond.offset32 = (_n); } while (0)
328	#define SET_OP_BR_FCC(_n) do { xcip->di.brcond.fcc = (_n); } while (0)
329
330	#define SET_OP_ASI_OP(_n) do { xcip->di.sp_asi_imm.op = (_n) ; } while (0)
331	#define SET_OP_ASI_RD(_n) do { xcip->di.sp_asi_imm.rd_num = (_n) ; } while (0)
332	#define SET_OP_ASI_FPRD(_n) do { xcip->di.sp_asi_imm.rd_num = (_n) ; } while (0)
333	#define SET_OP_ASI_NUM(_n) do { xcip->di.sp_asi_imm.asi_num = (_n) ; } while (0)
334
335	#define ASI_Rdest (xcip->di.sp_asi_imm.rd_num)
336	#define ASI_num (xcip->di.sp_asi_imm.asi_num)
337	#define ASI_op (xcip->di.sp_asi_imm.op)
338
339	#define SET_OP_TRAP_CC(_cc) do { xcip->di.sp_trap_rrr.cc = (_cc); } while (0)
340	#define SET_OP_TRAP_COND(_c) do { xcip->di.sp_trap_rrr.cond = (_c); } while (0)
341
342	#define TRAP_cc (xcip->di.sp_trap_rrr.cc)
343	#define TRAP_cond (xcip->di.sp_trap_rrr.cond)
344
345	#define SET_OP_MOVCC_CC(_cc) do { xcip->di.sp_movcc_rr.cc = (_cc); } while (0)
346	#define SET_OP_MOVCC_COND(_c) do { xcip->di.sp_movcc_rr.cond = (_c); } while (0)
347
348	#define MOVCC_cc (xcip->di.sp_movcc_rr.cc)
349	#define MOVCC_cond (xcip->di.sp_movcc_rr.cond)
350
351	/*
352	* When an illegal instruction is encountered we set an internal
353	* code to give ourselves a clue as to why the decoder thought it
354	* was illegal
355	*/
356
357	#define SET_OP_ILL_REASON(_r) do { xcip->di.ill_reason = (uint32_t)(_r); } while (0)
358
359	/*
360	* Instructions for which we have no other obvious encoding
361	* get to have a custom 32 bit field for their own bit encodings
362	*/
363
364	#define SET_OP_MISC_BITS(_b) do { xcip->di.misc_bits = (uint32_t)(_b); } while (0)
365
366	#ifdef __cplusplus
367	}
368	#endif
369
370	#endif /* _XICACHE_H_ */