Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / obp / obp / cpu / sparc / ultra4v / savecpu.fth
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1\ ========== Copyright Header Begin ==========================================
2\
3\ Hypervisor Software File: savecpu.fth
4\
5\ Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
6\
7\ - Do no alter or remove copyright notices
8\
9\ - Redistribution and use of this software in source and binary forms, with
10\ or without modification, are permitted provided that the following
11\ conditions are met:
12\
13\ - Redistribution of source code must retain the above copyright notice,
14\ this list of conditions and the following disclaimer.
15\
16\ - Redistribution in binary form must reproduce the above copyright notice,
17\ this list of conditions and the following disclaimer in the
18\ documentation and/or other materials provided with the distribution.
19\
20\ Neither the name of Sun Microsystems, Inc. or the names of contributors
21\ may be used to endorse or promote products derived from this software
22\ without specific prior written permission.
23\
24\ This software is provided "AS IS," without a warranty of any kind.
25\ ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
26\ INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
27\ PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
28\ MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
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30\ DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
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33\ DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
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35\ SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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37\ You acknowledge that this software is not designed, licensed or
38\ intended for use in the design, construction, operation or maintenance of
39\ any nuclear facility.
40\
41\ ========== Copyright Header End ============================================
42id: @(#)savecpu.fth 1.1 06/02/16
43purpose:
44copyright: Copyright 2006 Sun Microsystems, Inc. All Rights Reserved
45copyright: Use is subject to license terms.
46
47transient
48also assembler definitions
49: save-reg ( reg offset -- ) \ where?
50 postpone offset-of %asi stxa
51;
52: load-reg ( area reg -- ) \ where?
53 >r postpone offset-of %asi r> ldxa
54;
55: write-reg ( reg area offset -- ) %asi stxa ;
56: read-reg ( area offset reg -- ) >r %asi r> ldxa ;
57previous definitions
58resident
59
60headers
61\ %g5 = save area
62\ %g4 = <exit type>
63\ = 0, restore, retry
64\ = 1, restore, done
65\ else, restore, jmpl %g7
66\
67label restore-cpu-state ( -- )
68 %g0 memory-asi wrasi
69 %g5 %g1 load-reg %cwp %g1 0 wrcwp \ EARLY!!!
70 %g5 %l5 move
71 %g4 %l4 move
72 %g7 %l7 move
73
74 %g0 2 wrtl
75 %l5 %g1 load-reg %tpc-2 %g1 0 wrtpc
76 %l5 %g1 load-reg %tnpc-2 %g1 0 wrtnpc
77 %l5 %g1 load-reg %tstate-2 %g1 0 wrtstate
78 %l5 %g1 load-reg %tt-2 %g1 0 wrtt
79
80 %g0 1 wrtl
81 %l5 %g1 load-reg %tpc-1 %g1 0 wrtpc
82 %l5 %g1 load-reg %tnpc-1 %g1 0 wrtnpc
83 %l5 %g1 load-reg %tstate-1 %g1 0 wrtstate
84 %l5 %g1 load-reg %tt-1 %g1 0 wrtt
85
86 \ Now restore original state..
87 %l5 %g1 load-reg %tl-c %g1 0 cmp \ TL=0??
88 0= if
89 %g1 0 wrtl \ Restore
90 %g0 1 wrtl \ Force to 1.
91 then
92 %l5 %g1 load-reg %pc %g1 0 wrtpc
93 %l5 %g1 load-reg %npc %g1 0 wrtnpc
94 %l5 %g1 load-reg %tstate-c %g1 0 wrtstate
95 %l5 %g1 load-reg %y %g1 0 wry
96 %l5 %g1 load-reg %pil %g1 0 wrpil
97 %l5 %g1 load-reg %cansave %g1 0 wrcansave
98 %l5 %g1 load-reg %canrestore %g1 0 wrcanrestore
99 %l5 %g1 load-reg %cleanwin %g1 0 wrcleanwin
100 %l5 %g1 load-reg %otherwin %g1 0 wrotherwin
101 %l5 %g1 load-reg %wstate %g1 0 wrwstate
102 %l5 %g1 load-reg %fprs %g1 0 wrfprs
103
104[ifdef] SUN4V
105 %g0 0 wrgl 8 0 do %l5 offset-of %g0 i /x* + %g0 i + read-reg loop
106 %g0 1 wrgl 8 0 do %l5 offset-of %a0 i /x* + %g0 i + read-reg loop
107 %g0 2 wrgl
108[then]
109
110 %l5 %g5 move
111 %l4 %g4 move
112 %l7 %g7 move
113
114 \ Restore locals, Ins Outs
115 \ Address of window regs.
116 %l5 window-registers %g6 add
117 8 0 do %g6 i /x* %o0 i + read-reg loop \ %o0-%o7
118 %g6 8 /n* %g6 add
119
120 %g5 %g1 load-reg full-save?
121 %g1 %g0 cmp
122 0<> if
123 nop
124 %g5 %g1 load-reg %pcontext
125 %g0 h# 08 %g2 add
126 %g1 %g0 %g2 h# 21 stxa
127 %g5 %g1 load-reg %scontext
128 %g0 h# 10 %g2 add
129 %g1 %g0 %g2 h# 21 stxa
130 #sync membar
131 %g5 %g1 load-reg %tba
132 %g1 0 wrtba
133
134 \ recover how many we saved
135 %g5 %g1 load-reg %nwins
136 %g2 rdcwp
137 begin
138 %g2 0 wrcwp
139 8 0 do %g6 i /x* %l0 i + read-reg loop \ %l0-%l7
140 %g6 8 /n* %g6 add
141 8 0 do %g6 i /x* %i0 i + read-reg loop \ %i0-%i7
142 %g6 8 /n* %g6 add
143 %g2 1 %g2 sub
144 %g2 0 wrcwp
145 %g1 1 %g1 subcc
146 0= until
147 %g2 rdcwp
148 %g5 %g1 load-reg %cwp
149 %g1 0 wrcwp
150 else
151 nop
152 8 0 do %g6 i /x* %l0 i + read-reg loop \ %l0-%l7
153 %g6 8 /n* %g6 add
154 8 0 do %g6 i /x* %i0 i + read-reg loop \ %i0-%i7
155 %g6 8 /n* %g6 add
156 then
157
158 %g4 %g0 cmp
159 0<> if
160 %g4 1 cmp
161 0= if
162 nop
163 done
164 then
165 \ copy the state we destroy into TL=2 equivs.
166 %g0 1 wrtl
167 %g7 4 %g7 add
168 %g7 0 wrtpc
169 %g7 4 %g7 add
170 %g7 0 wrtnpc
171 then
172 retry
173end-code
174
175\ In: any GL
176\ %g4 = <preserved>
177\ %g5 = save area
178\ %g6 = full_save?
179\ %g7 = pc to jump to after save, cwp=0, gl=0, tl=0, ie=1
180\
181\ %g1 trashed
182\ %g2 trashed
183\ %g3 trashed
184\ %g6 trashed once used
185\
186\ Out: GL=0, run (%g7)
187\
188label save-cpu-state ( -- )
189 %g0 memory-asi wrasi
190 %g1 rdtl %g1 %g5 save-reg %tl-c
191 %g1 rdtpc %g1 %g5 save-reg %tpc-c
192 %g1 %g5 save-reg %pc
193 %g1 rdtnpc %g1 %g5 save-reg %tnpc-c
194 %g1 %g5 save-reg %npc
195 %g1 rdtstate %g1 %g5 save-reg %tstate-c
196 %g1 rdy %g1 %g5 save-reg %y
197 %g1 rdpil %g1 %g5 save-reg %pil
198 %g1 rdcwp %g1 %g5 save-reg %cwp
199 %g1 rdcansave %g1 %g5 save-reg %cansave
200 %g1 rdcanrestore %g1 %g5 save-reg %canrestore
201 %g1 rdcleanwin %g1 %g5 save-reg %cleanwin
202 %g1 rdotherwin %g1 %g5 save-reg %otherwin
203 %g1 rdwstate %g1 %g5 save-reg %wstate
204 %g1 rdfprs %g1 %g5 save-reg %fprs
205 %g6 %g5 save-reg full-save?
206[ifdef] SUN4V
207 %g1 rdgl %g1 %g5 save-reg %gl
208[then]
209 %g1 rdtt %g1 %g5 save-reg %tt-c
210
211 %g0 2 wrtl
212 %g1 rdtpc %g1 %g5 save-reg %tpc-2
213 %g1 rdtnpc %g1 %g5 save-reg %tnpc-2
214 %g1 rdtstate %g1 %g5 save-reg %tstate-2
215 %g1 rdtt %g1 %g5 save-reg %tt-2
216
217 %g0 1 wrtl
218 %g1 rdtpc %g1 %g5 save-reg %tpc-1
219 %g1 rdtnpc %g1 %g5 save-reg %tnpc-1
220 %g1 rdtstate %g1 %g5 save-reg %tstate-1
221 %g1 rdtt %g1 %g5 save-reg %tt-1
222
223 \ Address of window regs.
224 %g5 window-registers %g6 add
225 8 0 do %o0 i + %g6 i /x* write-reg loop \ %o0-%o7
226 %g6 8 /n* %g6 add
227
228 \ Full save or partial?
229 %g5 %g1 load-reg full-save?
230 %g1 %g0 cmp
231 0<> if
232 %g1 rdtba
233 %g1 %g5 save-reg %tba
234 %g0 h# 08 %g2 add
235 %g0 %g2 h# 21 %g1 ldxa
236 %g1 %g5 save-reg %pcontext
237 %g0 h# 10 %g1 add
238 %g0 %g1 h# 21 %g1 ldxa
239 %g1 %g5 save-reg %scontext
240 %g0 %g0 %g2 h# 21 stxa \ Set Primary context to 0
241 #sync membar
242
243 \ Rebuild %PSTATE, %CCR, %ASI from %TSTATE and save them
244 %g1 rdtstate
245 %g1 d# 08 %g2 sll
246 %g2 d# 16 %g2 srl
247 %g2 %g5 save-reg %pstate
248 %g1 d# 63 d# 39 - %g2 sllx
249 %g2 d# 32 %g2 srlx
250 %g2 %g5 save-reg %ccr
251 %g1 d# 24 %g2 srl
252 %g2 %g5 save-reg %asi
253
254 %g2 rdcwp
255 %g2 %g3 move
256 %g0 %g1 move
257 begin
258 %g3 0 wrcwp
259 8 0 do %l0 i + %g6 i /x* write-reg loop \ %l0-%l7
260 %g6 8 /n* %g6 add
261 8 0 do %i0 i + %g6 i /x* write-reg loop \ %i0-%i7
262
263 %g3 1 %g3 sub
264 %g3 0 wrcwp
265 %g3 rdcwp
266 %g2 %g3 %g0 subcc
267 %g1 1 %g1 add
268 = until
269 %g6 8 /n* %g6 add
270 %g1 %g5 save-reg %nwins \ How many?
271 else
272 nop
273 8 0 do %l0 i + %g6 i /x* write-reg loop \ %l0-%l7
274 %g6 8 /n* %g6 add
275 8 0 do %i0 i + %g6 i /x* write-reg loop \ %i0-%i7
276 %g6 8 /n* %g6 add
277 then
278
279 %g5 %g1 load-reg %cwp %g1 0 wrcwp
280 %g4 %l4 move
281 %g5 %l5 move
282 %g7 %l7 move
283
284[ifdef] SUN4V
285 \ Save current GLs
286 %g0 1 wrgl 8 0 do %g0 i + %l5 offset-of %a0 i /x* + write-reg loop
287 %g0 0 wrgl 8 0 do %g0 i + %l5 offset-of %g0 i /x* + write-reg loop
288[then]
289
290 %g1 rdpstate
291 %g1 2 %g1 andn
292 %g1 0 wrpstate
293 %l7 4 %g0 jmpl
294 %g0 0 wrtl
295end-code
296
297\ %l0 = stack base
298\ %l4 = TOS (VA)
299\ %l7 = IP to run
300label setup-small-forth-engine
301 prom-main-task %g5 up setx \ Set User Pointer
302 up sp %g1 get-cpu-struct
303 %g1 %l0 %g1 add \ CPU Save Area VA
304 %g1 /min-cpu-save %g1 add
305 %g1 /fth-exception-stack sp add \ Data Stack set
306 %g1 /fth-exception-stack 2/ rp add
307 rombase base set \ set base
308 %l7 base ip add
309 %l4 tos move \ VA
310 next
311end-code
312
313[ifdef] WOULD-BE-NICE-TO-HAVE-HERE
314\
315\ We cant put this here because it has a fwd ref to save state
316\ we also depends upon this code. So its [ifdef]d out and left for
317\ reference.
318\
319
320\ %gl = 2
321\ %g1 is the structure offset
322label small-forth-save-state
323 \ OK, we have to switch to the original fault-tl and tpc, tnpc
324 \ we got here from the restore which does a retry at tl=1 having
325 \ setup the tpc, tnpc to 'return', everything else should be restored
326 %g0 2 wrtl
327 %g0 h# 38 %g2 add
328 %g2 %g0 h# 20 %g5 ldxa \ CPU struct PA
329 %g5 %g1 %g5 add \ CPU save area
330 %g7 rdasi
331 %g0 memory-asi wrasi
332 %g5 %g1 load-reg %tpc-1
333 %g5 %g2 load-reg %tnpc-1
334 %g5 %g3 load-reg %tl-c
335 %g0 1 wrtl
336 %g0 %g1 wrtpc
337 %g0 %g2 wrtnpc
338 %g0 %g7 wrasi
339 save-state always brif
340 %g0 %g3 wrtl
341end-code
342[then]