[OpenSPARC-T2-SAM] / obp / obp / fm / kernel / sparc / divrem.fth

\ ========== Copyright Header Begin ==========================================
\ 
\ Hypervisor Software File: divrem.fth
\ 
\ Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
\ 
\  - Do no alter or remove copyright notices
\ 
\  - Redistribution and use of this software in source and binary forms, with 
\    or without modification, are permitted provided that the following 
\    conditions are met: 
\ 
\  - Redistribution of source code must retain the above copyright notice, 
\    this list of conditions and the following disclaimer.
\ 
\  - Redistribution in binary form must reproduce the above copyright notice,
\    this list of conditions and the following disclaimer in the
\    documentation and/or other materials provided with the distribution. 
\ 
\    Neither the name of Sun Microsystems, Inc. or the names of contributors 
\ may be used to endorse or promote products derived from this software 
\ without specific prior written permission. 
\ 
\     This software is provided "AS IS," without a warranty of any kind. 
\ ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, 
\ INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
\ PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN 
\ MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR 
\ ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR 
\ DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN 
\ OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR 
\ FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE 
\ DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, 
\ ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF 
\ SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
\ 
\ You acknowledge that this software is not designed, licensed or
\ intended for use in the design, construction, operation or maintenance of
\ any nuclear facility. 
\ 
\ ========== Copyright Header End ============================================
id: @(#)divrem.fth 1.5 96/03/01
purpose: 
copyright: Copyright 1992 Sun Microsystems, Inc.  All Rights Reserved

\ Translated directly from forthlang/kernel/sparc/divrem.s
\ It generates exactly the same code as divrem.s
code u/mod  (s u.dividend u.divisor -- u.remainder u.quotient )
   sp   0 /n* sc6  nget     \ dividend in  %l6
   %g0  tos  sc1  add    \ divisor in   %l1
   %l1  %g0  %l1  orcc
   %g0 h# 3e  =   trapif
   sc6  sc1  %g0 subcc
   u>=  if
      %g0 %g0     %l5  or
      h# 800.0000 %l3  sethi
64\   %l3  d# 32 %l3   slln
      %l6  %l3    %g0  subcc
      u>=  if  %g0 %g0  %l0  or  ( Delay slot )
	 begin
	    %l1  %l3  %g0  subcc
	    0 F: u>=  brif   %g0  1  %l4  or  ( Delay slot )
	    %l1  4  %l1  sll
	 again   %l0  1  %l0  add
	 begin
	    %l1 %l1  %l1  addcc
	    u<  if   %l4 1  %l4  add  ( Delay slot )
	       %l3  4    %l3  slln
	       %l1  1    %l1  srln
	       %l1  %l3  %l1  add
	       1 F: bra   %l4  1   %l4  sub  ( Delay slot )
	    then
0 L:
            %l1  %l6  %g0  subcc
         u>=  until  nop  ( Delay slot )

	 <>  if  nop  then  \ XXXX Don't really need this !!!
1 L:

         %l4  1   %l4  subcc
	 3  F: <  brif  nop  ( Delay slot )

	 %l6  %l1   %l6  sub
	 %g0  1     %l5  or
	 2 F:  bra  annul

	 begin
	    %l5  1  %l5  slln
	    >=  if   %l1  1  %l1  srln  ( Delay slot )
	       %l6  %l1  %l6  sub
	       2 F:  bra   %l5 1  %l5  add  ( Delay slot )
	    then

	    %l6  %l1   %l6  add
	    %l5  1     %l5  sub
2 L:
	    %l4  1   %l4  subcc
	 <  until  %g0  %l6   %g0  orcc  ( Delay slot )

	 3  F:  bra  annul
      then

      begin
	 %l1  4  %l1  slln
	 %l1  %l6  %g0  subcc
      u>  until   %l0  1  %l0 addcc  ( Delay slot )

      <>  if    %l0  1   %l0  sub  ( Delay slot )
	 %g0  %l6   %g0  orcc

	 begin
	    %l5  4  %l5  slln
	    >=  if  %l1  1   %l1  srln  ( Delay slot )
	       %l6  %l1  %l6  subcc
	       >=  if  %l1  1   %l1  srln  ( Delay slot )
		  %l6  %l1  %l6  subcc
		  >=  if  %l1  1   %l1  srln  ( Delay slot )
		     %l6  %l1  %l6  subcc
		     >=  if  %l1  1   %l1  srln  ( Delay slot )
			%l6  %l1  %l6  subcc
			3  F:  bra   %l5  h# 0f  %l5 add  ( Delay slot )
		     then
		     %l6  %l1  %l6  addcc
		     3  F:  bra   %l5  h# 0d  %l5 add  ( Delay slot )
		  then
		  %l6  %l1   %l6  addcc
		  >=  if  %l1  1   %l1  srln  ( Delay slot )
		     %l6  %l1  %l6 subcc
		     3  F:  bra   %l5  h# 0b  %l5 add  ( Delay slot )
		  then
		  %l6  %l1  %l6  addcc
		  3  F:  bra   %l5  h# 09  %l5 add  ( Delay slot )
	       then

	       %l6  %l1   %l6  addcc
	       >=  if  %l1  1   %l1  srln  ( Delay slot )
		  %l6  %l1  %l6 subcc
		  >=  if  %l1  1   %l1  srln  ( Delay slot )
		     %l6  %l1  %l6 subcc
		     3  F:  bra   %l5  h# 07  %l5 add  ( Delay slot )
		  then
		  %l6  %l1   %l6  addcc
		  3  F:  bra   %l5  h# 05  %l5 add  ( Delay slot )
	       then
	       %l6  %l1   %l6  addcc
	       >=  if  %l1  1   %l1  srln  ( Delay slot )
		  %l6  %l1  %l6 subcc
		  3  F:  bra   %l5  h# 03  %l5 add  ( Delay slot )
	       then
	       %l6  %l1   %l6  addcc
	       3  F:  bra   %l5  h# 01  %l5 add  ( Delay slot )
	    then
	    %l6  %l1   %l6  addcc
	    >=  if  %l1  1   %l1  srln  ( Delay slot )
	       %l6  %l1  %l6 subcc
	       >=  if  %l1  1   %l1  srln  ( Delay slot )
		  %l6  %l1  %l6 subcc
		  >=  if  %l1  1   %l1  srln  ( Delay slot )
		     %l6  %l1  %l6 subcc
		     3  F:  bra   %l5  h# -1  %l5 add  ( Delay slot )
		  then
		  %l6  %l1   %l6  addcc
		  3  F:  bra   %l5  h# -3  %l5 add  ( Delay slot )
	       then
	       %l6  %l1   %l6  addcc
	       >=  if  %l1  1   %l1  srln  ( Delay slot )
		  %l6  %l1  %l6 subcc
		  3  F:  bra   %l5  h# -5  %l5 add  ( Delay slot )
	       then
	       %l6  %l1   %l6  addcc
	       3  F:  bra   %l5  h# -7  %l5 add  ( Delay slot )
	    then
	    %l6  %l1   %l6  addcc
	    >=  if  %l1  1   %l1  srln  ( Delay slot )
	       %l6  %l1   %l6  subcc
	       >=  if  %l1  1   %l1  srln  ( Delay slot )
		  %l6  %l1  %l6 subcc
		  3  F:  bra   %l5  h# -9  %l5 add  ( Delay slot )
	       then
	       %l6  %l1   %l6  addcc
	       3  F:  bra   %l5  h# -0b  %l5 add  ( Delay slot )
	    then
	    %l6  %l1   %l6  addcc
	    >=  if  %l1  1   %l1  srln  ( Delay slot )
	       %l6  %l1  %l6 subcc
	       3  F:  bra   %l5  h# -0d  %l5 add  ( Delay slot )
	    then
	    %l6  %l1   %l6  addcc

	    \ XXXX Don't really need the following 3 F:  bra !!!
	    3  F:  bra   %l5  h# -0f  %l5 add  ( Delay slot )

3 L:
	    %l0  1  %l0  subcc
	    < until  %g0 %l6  %g0  orcc  ( Delay slot )
	 <  if  nop  ( Delay slot )
	    %l5  1    %l5  sub
	    %l6  tos  %l6  add
	 then
      then
   then
   nop	\ XXXX Don't really need this !!!

   sc6  sp 0 /n*  nput    \ remainder
   %g0 sc5  tos  add      \ quotient

c;
Commit	Line	Data
920dae64 AT	1	\ ========== Copyright Header Begin ==========================================
	2	\
	3	\ Hypervisor Software File: divrem.fth
	4	\
	5	\ Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	6	\
	7	\ - Do no alter or remove copyright notices
	8	\
	9	\ - Redistribution and use of this software in source and binary forms, with
	10	\ or without modification, are permitted provided that the following
	11	\ conditions are met:
	12	\
	13	\ - Redistribution of source code must retain the above copyright notice,
	14	\ this list of conditions and the following disclaimer.
	15	\
	16	\ - Redistribution in binary form must reproduce the above copyright notice,
	17	\ this list of conditions and the following disclaimer in the
	18	\ documentation and/or other materials provided with the distribution.
	19	\
	20	\ Neither the name of Sun Microsystems, Inc. or the names of contributors
	21	\ may be used to endorse or promote products derived from this software
	22	\ without specific prior written permission.
	23	\
	24	\ This software is provided "AS IS," without a warranty of any kind.
	25	\ ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
	26	\ INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
	27	\ PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
	28	\ MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
	29	\ ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
	30	\ DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
	31	\ OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
	32	\ FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
	33	\ DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
	34	\ ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
	35	\ SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
	36	\
	37	\ You acknowledge that this software is not designed, licensed or
	38	\ intended for use in the design, construction, operation or maintenance of
	39	\ any nuclear facility.
	40	\
	41	\ ========== Copyright Header End ============================================
	42	id: @(#)divrem.fth 1.5 96/03/01
	43	purpose:
	44	copyright: Copyright 1992 Sun Microsystems, Inc. All Rights Reserved
	45
	46	\ Translated directly from forthlang/kernel/sparc/divrem.s
	47	\ It generates exactly the same code as divrem.s
	48	code u/mod (s u.dividend u.divisor -- u.remainder u.quotient )
	49	sp 0 /n* sc6 nget \ dividend in %l6
	50	%g0 tos sc1 add \ divisor in %l1
	51	%l1 %g0 %l1 orcc
	52	%g0 h# 3e = trapif
	53	sc6 sc1 %g0 subcc
	54	u>= if
	55	%g0 %g0 %l5 or
	56	h# 800.0000 %l3 sethi
	57	64\ %l3 d# 32 %l3 slln
	58	%l6 %l3 %g0 subcc
	59	u>= if %g0 %g0 %l0 or ( Delay slot )
	60	begin
	61	%l1 %l3 %g0 subcc
	62	0 F: u>= brif %g0 1 %l4 or ( Delay slot )
	63	%l1 4 %l1 sll
	64	again %l0 1 %l0 add
65	begin
66	%l1 %l1 %l1 addcc
67	u< if %l4 1 %l4 add ( Delay slot )
68	%l3 4 %l3 slln
69	%l1 1 %l1 srln
70	%l1 %l3 %l1 add
71	1 F: bra %l4 1 %l4 sub ( Delay slot )
72	then
73	0 L:
74	%l1 %l6 %g0 subcc
75	u>= until nop ( Delay slot )
76
77	<> if nop then \ XXXX Don't really need this !!!
78	1 L:
79
80	%l4 1 %l4 subcc
81	3 F: < brif nop ( Delay slot )
82
83	%l6 %l1 %l6 sub
84	%g0 1 %l5 or
85	2 F: bra annul
86
87	begin
88	%l5 1 %l5 slln
89	>= if %l1 1 %l1 srln ( Delay slot )
90	%l6 %l1 %l6 sub
91	2 F: bra %l5 1 %l5 add ( Delay slot )
92	then
93
94	%l6 %l1 %l6 add
95	%l5 1 %l5 sub
96	2 L:
97	%l4 1 %l4 subcc
98	< until %g0 %l6 %g0 orcc ( Delay slot )
99
100	3 F: bra annul
101	then
102
103	begin
104	%l1 4 %l1 slln
105	%l1 %l6 %g0 subcc
106	u> until %l0 1 %l0 addcc ( Delay slot )
107
108	<> if %l0 1 %l0 sub ( Delay slot )
109	%g0 %l6 %g0 orcc
110
111	begin
112	%l5 4 %l5 slln
113	>= if %l1 1 %l1 srln ( Delay slot )
114	%l6 %l1 %l6 subcc
115	>= if %l1 1 %l1 srln ( Delay slot )
116	%l6 %l1 %l6 subcc
117	>= if %l1 1 %l1 srln ( Delay slot )
118	%l6 %l1 %l6 subcc
119	>= if %l1 1 %l1 srln ( Delay slot )
120	%l6 %l1 %l6 subcc
121	3 F: bra %l5 h# 0f %l5 add ( Delay slot )
122	then
123	%l6 %l1 %l6 addcc
124	3 F: bra %l5 h# 0d %l5 add ( Delay slot )
125	then
126	%l6 %l1 %l6 addcc
127	>= if %l1 1 %l1 srln ( Delay slot )
128	%l6 %l1 %l6 subcc
129	3 F: bra %l5 h# 0b %l5 add ( Delay slot )
130	then
131	%l6 %l1 %l6 addcc
132	3 F: bra %l5 h# 09 %l5 add ( Delay slot )
133	then
134
135	%l6 %l1 %l6 addcc
136	>= if %l1 1 %l1 srln ( Delay slot )
137	%l6 %l1 %l6 subcc
138	>= if %l1 1 %l1 srln ( Delay slot )
139	%l6 %l1 %l6 subcc
140	3 F: bra %l5 h# 07 %l5 add ( Delay slot )
141	then
142	%l6 %l1 %l6 addcc
143	3 F: bra %l5 h# 05 %l5 add ( Delay slot )
144	then
145	%l6 %l1 %l6 addcc
146	>= if %l1 1 %l1 srln ( Delay slot )
147	%l6 %l1 %l6 subcc
148	3 F: bra %l5 h# 03 %l5 add ( Delay slot )
149	then
150	%l6 %l1 %l6 addcc
151	3 F: bra %l5 h# 01 %l5 add ( Delay slot )
152	then
153	%l6 %l1 %l6 addcc
154	>= if %l1 1 %l1 srln ( Delay slot )
155	%l6 %l1 %l6 subcc
156	>= if %l1 1 %l1 srln ( Delay slot )
157	%l6 %l1 %l6 subcc
158	>= if %l1 1 %l1 srln ( Delay slot )
159	%l6 %l1 %l6 subcc
160	3 F: bra %l5 h# -1 %l5 add ( Delay slot )
161	then
162	%l6 %l1 %l6 addcc
163	3 F: bra %l5 h# -3 %l5 add ( Delay slot )
164	then
165	%l6 %l1 %l6 addcc
166	>= if %l1 1 %l1 srln ( Delay slot )
167	%l6 %l1 %l6 subcc
168	3 F: bra %l5 h# -5 %l5 add ( Delay slot )
169	then
170	%l6 %l1 %l6 addcc
171	3 F: bra %l5 h# -7 %l5 add ( Delay slot )
172	then
173	%l6 %l1 %l6 addcc
174	>= if %l1 1 %l1 srln ( Delay slot )
175	%l6 %l1 %l6 subcc
176	>= if %l1 1 %l1 srln ( Delay slot )
177	%l6 %l1 %l6 subcc
178	3 F: bra %l5 h# -9 %l5 add ( Delay slot )
179	then
180	%l6 %l1 %l6 addcc
181	3 F: bra %l5 h# -0b %l5 add ( Delay slot )
182	then
183	%l6 %l1 %l6 addcc
184	>= if %l1 1 %l1 srln ( Delay slot )
185	%l6 %l1 %l6 subcc
186	3 F: bra %l5 h# -0d %l5 add ( Delay slot )
187	then
188	%l6 %l1 %l6 addcc
189
190	\ XXXX Don't really need the following 3 F: bra !!!
191	3 F: bra %l5 h# -0f %l5 add ( Delay slot )
192
193	3 L:
194	%l0 1 %l0 subcc
195	< until %g0 %l6 %g0 orcc ( Delay slot )
196	< if nop ( Delay slot )
197	%l5 1 %l5 sub
198	%l6 tos %l6 add
199	then
200	then
201	then
202	nop \ XXXX Don't really need this !!!
203
204	sc6 sp 0 /n* nput \ remainder
205	%g0 sc5 tos add \ quotient
206
207	c;