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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / exe / nas / src / n2_common.conf
CommitLineData
920dae64
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_common.conf
5* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
6* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
7*
8* The above named program is free software; you can redistribute it and/or
9* modify it under the terms of the GNU General Public
10* License version 2 as published by the Free Software Foundation.
11*
12* The above named program is distributed in the hope that it will be
13* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
14* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15* General Public License for more details.
16*
17* You should have received a copy of the GNU General Public
18* License along with this work; if not, write to the Free Software
19* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
20*
21* ========== Copyright Header End ============================================
22*/
23// ========== Copyright Header Begin ==========================================
24//
25// OpenSPARC T2 Processor File: n2_common.conf
26// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
27// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
28//
29// The above named program is free software; you can redistribute it and/or
30// modify it under the terms of the GNU General Public
31// License version 2 as published by the Free Software Foundation.
32//
33// The above named program is distributed in the hope that it will be
34// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
35// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
36// General Public License for more details.
37//
38// You should have received a copy of the GNU General Public
39// License along with this work; if not, write to the Free Software
40// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
41//
42// ========== Copyright Header End ============================================
43//
44// pli-socket options
45//
46#define XSTR(M) STR(M)
47#define STR(M) #M
48
49//#if defined(RTL) || defined(PLI_REPLAY)
50OBJECT socket0 TYPE pli-socket {
51#if defined(FORCE_PC)
52 force_pc: 1
53#else
54 force_pc: 0
55#endif
56#if !defined(NOINT_SYNC) && (defined(RTL) || defined(PLI_REPLAY))
57 // int_sync is enabled
58 int_model: 1
59#else
60 int_model: 0
61#endif
62#if !defined(NOLDST_SYNC) && (defined(RTL) || defined(PLI_REPLAY))
63 // msync is enabled
64 mem_model: 1
65#else
66 mem_model: 0
67#endif
68#ifdef VERA_SOCKET
69 cmd_intf: 0
70#else
71 cmd_intf: 1
72#endif
73#ifdef PLI_REPLAY
74 replay_log: PLI_REPLAY
75 socket: 0
76 open: 0
77#elif defined(CSOCKET)
78 replay_log: 0
79 socket: CSOCKET
80 open: 1
81#else
82 replay_log: 0
83 socket: 0
84 open: 0
85#endif
86 close: 0
87 test: 0
88#ifdef PLI_LOG
89 pli_log: PLI_LOG
90#else
91 pli_log: 0
92#endif
93#if defined(NO_REG_CMP)
94 reg_cmp: 0
95#elif defined(REG_CMP)
96 reg_cmp: REG_CMP
97#else
98 reg_cmp: 1
99#endif
100#if defined(PLI_RTL_DEBUG)
101 debug_level: 9
102#elif defined(PLI_DEBUG)
103 debug_level: PLI_DEBUG
104#else
105 // default shows trap & instructions
106 debug_level: 2
107#endif
108#if !defined(NOTLB_SYNC)
109 tlb_sync: 1
110#else
111 tlb_sync: 0
112#endif
113#if defined(TLB_SYNC_DEBUG)
114 tlb_debug: TLB_SYNC_DEBUG
115#else
116 tlb_debug: 0
117#endif
118#if defined(TLB_SYNC_SIZE)
119 tlb_sync_size: TLB_SYNC_SIZE
120#endif
121#if defined(CMP_REG_CMP)
122 cmp_cmp: CMP_REG_CMP
123#endif
124#if defined(MMU_REG_CMP)
125 mmu_cmp: MMU_REG_CMP
126#endif
127#if defined(ENABLE_RAS)
128 enable_ras: ENABLE_RAS
129#else
130 enable_ras: 0
131#endif
132#if defined(RSTV_MASK)
133 rstv_mask: 1
134#endif
135#if defined(DUMP_REGS)
136 dump_regs: 1
137#endif
138// list of registers to be compared, e.g., -sas_run_args=-DCMPR_LIST=G/W/F/PC.
139// To exclude a list of registers from the default comparison list, add a '-'
140// to the front of the list, e.g., -sas_run_args=-DCMPR_LIST=-/G/W/F/PC.
141#if defined(CMPR_LIST)
142 cmpr_list: XSTR(CMPR_LIST)
143#endif
144}
145
146//#endif // defined(RTL) || defined(PLI_REPLAY)
147
148//
149// swvmem0: msync, tsoChecker, and pmask related options
150//
151#if defined(MOM)
152
153OBJECT mom0 TYPE mom {
154 queue: th00
155 enable_sim: 1
156 wait-mode: 0
157#if defined(MOM_DEBUG)
158 DEBUG: 1
159#endif
160#if defined(MOM_SO_PATH)
161 so_path: MOM_SO_PATH
162#endif
163}
164
165#else // if defined(MOM)
166
167OBJECT swvmem0 TYPE swerver-memory {
168#if defined(RTL) || defined(PLI_REPLAY)
169 irq: irq0
170#endif
171#if defined(MEM_DISABLE) && !defined(PLI_REPLAY)
172 snoop: 0
173#else
174 snoop: 1
175#endif
176#if defined(TSO_CHECKER) && !defined(NO_TSO_CHECKER)
177 tso_checker: 1
178#else
179 tso_checker: 0
180#endif
181#if defined(DIS_DEBUG)
182 debug_level: 0
183#elif defined(TSO_DEBUG)
184 debug_level: 2
185#elif defined(MEM_DEBUG)
186 debug_level: MEM_DEBUG
187#else
188 debug_level: 0
189#endif
190#if defined(MEM_IFETCH) && !defined(NO_MEM_IFETCH)
191 ifetch: 1
192#else
193 ifetch: 0
194#endif
195 queue: th00
196#if defined(CPU)
197 cpu: CPU
198#else
199// CMP masking, each mask is at most 64-bit, N2 needs one to cover 64 strands.
200// Every bit in a masking represents a strand. Do not prefix
201// mask value with '0x', 'x' has a special meaning in masking, it means the
202// corresponding core is not available. For example,
203// -sas_run_args=-DTHREAD_MASK0=f and -sas_run_args=-DTHREAD_MASK0=0xf.
204// A mask of 'f' means core-0 is available, with strand-0 to 3 enabled.
205// A mask of '0xf' means core-1 is available, with strand-0 to 3 enabled. But
206// because core-0 is not available, it ends up no strand is enabled.
207// THREAD_MASK is for backward compatability.
208#if defined(THREAD_MASK0)
209 thread_mask0: XSTR(THREAD_MASK0)
210#elif defined(THREAD_MASK)
211 thread_mask0: XSTR(THREAD_MASK)
212#else
213 thread_mask0: "01"
214#endif
215#endif // if defined(CPU)
216}
217
218#endif // if defined(MOM)
219
220//=================== the following OBJECTs are not used ====================//
221
222OBJECT sim TYPE sim {
223 cpu_switch_time: 1
224 time_model: "on"
225 continue_disabled: 0
226#if !defined(NOLDST_SYNC)
227 instruction_profile_mode: instruction-cache-access-trace
228 instruction_profile_line_size: 4
229#endif
230}
231
232#ifdef CIOP0
233############################################# chip 0 IO devices
234OBJECT irq0 TYPE swerver-interrupt {
235 thread_base: 0
236 queue: th00
237}
238
239OBJECT ciop0 TYPE swerver-io-device {
240 physical_memory: phys_mem0
241 irq: irq0
242 queue: th00
243}
244OBJECT bsc0 TYPE bsc-device {
245 queue: th00
246}
247OBJECT egress0 TYPE egress-device {
248 queue: th00
249}
250OBJECT ingress0 TYPE ingress-device {
251 queue: th00
252}
253OBJECT rdma0 TYPE rdma-device {
254 queue: th00
255}
256OBJECT echo0 TYPE echo-device {
257 queue: th00
258}
259#else
260OBJECT memory_ciop TYPE ram {
261 image: memory_ciop_image
262}
263OBJECT memory_ciop_image TYPE image {
264 size: 0x7f00000000
265 queue: th00
266}
267#endif
268
269#undef sparc
270
271OBJECT irqbus0 TYPE sparc-irq-bus {
272}
273
274#if defined(RTL) || defined(PLI_REPLAY)
275OBJECT irq0 TYPE swerver-interrupt {
276 thread_base: 0
277 need_ssi: 1
278 queue: th00
279}
280#endif
281
282#ifdef SP0
283OBJECT swvp0 TYPE swerver-processor {
284 thread0: th00
285 thread1: th01
286 thread2: th02
287 thread3: th03
288 thread4: th04
289 thread5: th05
290 thread6: th06
291 thread7: th07
292 mmu:swmmu0
293}
294OBJECT swmmu0 TYPE swerver-proc-mmu {
295}
296
297OBJECT th00 TYPE niagara2 {
298 freq_mhz: 800
299 mmu: stmmu00
300 max-trap-levels: 6
301 va_bits: 48
302 physical_memory: phys_mem0
303 control_registers: (("mid", 0))
304 irq_bus: irqbus0
305 thread_id: 0
306 other_threads: (th01, th02, th03, th04, th05, th06, th07)
307 queue: th00
308#if defined(RTL) || defined(PLI_REPLAY)
309 extra_irq_enable: 0
310#endif
311}
312
313OBJECT stmmu00 TYPE swerver-thread-mmu {
314 thread-status: 1
315 full-swerver-decode: 1
316 niagara-mmu: 1
317 disable-sun4u-interrupts: 1
318 intr_trap_type: 0x60
319 stream_cmpl_trap_type: 0x70
320 ma_cmpl_trap_type: 0x74
321 model-real-sfar: 1
322#if defined(N1_ASI)
323 n2-legacy-asi: 1
324#endif
325#if defined(RTL) || defined(PLI_REPLAY)
326 ignore_asi_0x73: 1
327 match_rtl: 1
328#endif
329#if defined(MOM)
330 mom_intf: 1
331#endif
332}
333
334OBJECT th01 TYPE niagara2 {
335 freq_mhz: 800
336 mmu: stmmu01
337 max-trap-levels: 6
338 va_bits: 48
339 physical_memory: phys_mem0
340 control_registers: (("mid", 1))
341 irq_bus: irqbus0
342 queue: th01
343 thread_id: 1
344 other_threads: (
345 th00,
346 th02,
347 th03,
348 th04,
349 th05,
350 th06,
351 th07
352 )
353#if defined(RTL) || defined(PLI_REPLAY)
354 extra_irq_enable: 0
355#endif
356}
357
358OBJECT stmmu01 TYPE swerver-thread-mmu {
359 full-swerver-decode: 1
360 niagara-mmu: 1
361 disable-sun4u-interrupts: 1
362 model-real-sfar: 1
363}
364
365OBJECT th02 TYPE niagara2 {
366 freq_mhz: 800
367 mmu: stmmu02
368 max-trap-levels: 6
369 va_bits: 48
370 physical_memory: phys_mem0
371 control_registers: (("mid", 2))
372 irq_bus: irqbus0
373 queue: th02
374 thread_id: 2
375 other_threads: (
376 th00,
377 th01,
378 th03,
379 th04,
380 th05,
381 th06,
382 th07
383 )
384#if defined(RTL) || defined(PLI_REPLAY)
385 extra_irq_enable: 0
386#endif
387}
388
389OBJECT stmmu02 TYPE swerver-thread-mmu {
390 full-swerver-decode: 1
391 niagara-mmu: 1
392 disable-sun4u-interrupts: 1
393 model-real-sfar: 1
394}
395
396OBJECT th03 TYPE niagara2 {
397 freq_mhz: 800
398 mmu: stmmu03
399 max-trap-levels: 6
400 va_bits: 48
401 physical_memory: phys_mem0
402 control_registers: (("mid", 3))
403 irq_bus: irqbus0
404 queue: th03
405 thread_id: 3
406 other_threads: (
407 th00,
408 th01,
409 th02,
410 th04,
411 th05,
412 th06,
413 th07
414 )
415#if defined(RTL) || defined(PLI_REPLAY)
416 extra_irq_enable: 0
417#endif
418}
419
420OBJECT stmmu03 TYPE swerver-thread-mmu {
421 full-swerver-decode: 1
422 niagara-mmu: 1
423 disable-sun4u-interrupts: 1
424 model-real-sfar: 1
425}
426
427OBJECT th04 TYPE niagara2 {
428 freq_mhz: 800
429 mmu: stmmu04
430 max-trap-levels: 6
431 va_bits: 48
432 physical_memory: phys_mem0
433 control_registers: (("mid", 4))
434 irq_bus: irqbus0
435 queue: th04
436 thread_id: 4
437 other_threads: (
438 th00,
439 th01,
440 th02,
441 th03,
442 th05,
443 th06,
444 th07
445 )
446#if defined(RTL) || defined(PLI_REPLAY)
447 extra_irq_enable: 0
448#endif
449}
450
451OBJECT stmmu04 TYPE swerver-thread-mmu {
452 full-swerver-decode: 1
453 niagara-mmu: 1
454 disable-sun4u-interrupts: 1
455 model-real-sfar: 1
456}
457
458OBJECT th05 TYPE niagara2 {
459 freq_mhz: 800
460 mmu: stmmu05
461 max-trap-levels: 6
462 va_bits: 48
463 physical_memory: phys_mem0
464 control_registers: (("mid", 5))
465 irq_bus: irqbus0
466 queue: th05
467 thread_id: 5
468 other_threads: (
469 th00,
470 th01,
471 th02,
472 th03,
473 th04,
474 th06,
475 th07
476 )
477#if defined(RTL) || defined(PLI_REPLAY)
478 extra_irq_enable: 0
479#endif
480}
481
482OBJECT stmmu05 TYPE swerver-thread-mmu {
483 full-swerver-decode: 1
484 niagara-mmu: 1
485 disable-sun4u-interrupts: 1
486 model-real-sfar: 1
487}
488
489OBJECT th06 TYPE niagara2 {
490 freq_mhz: 800
491 mmu: stmmu06
492 max-trap-levels: 6
493 va_bits: 48
494 physical_memory: phys_mem0
495 control_registers: (("mid", 6))
496 irq_bus: irqbus0
497 queue: th06
498 thread_id: 6
499 other_threads: (
500 th00,
501 th01,
502 th02,
503 th03,
504 th04,
505 th05,
506 th07
507 )
508#if defined(RTL) || defined(PLI_REPLAY)
509 extra_irq_enable: 0
510#endif
511}
512
513OBJECT stmmu06 TYPE swerver-thread-mmu {
514 full-swerver-decode: 1
515 niagara-mmu: 1
516 disable-sun4u-interrupts: 1
517 model-real-sfar: 1
518}
519
520OBJECT th07 TYPE niagara2 {
521 freq_mhz: 800
522 mmu: stmmu07
523 max-trap-levels: 6
524 va_bits: 48
525 physical_memory: phys_mem0
526 control_registers: (("mid", 7))
527 irq_bus: irqbus0
528 queue: th07
529 thread_id: 7
530 other_threads: (
531 th00,
532 th01,
533 th02,
534 th03,
535 th04,
536 th05,
537 th06
538 )
539#if defined(RTL) || defined(PLI_REPLAY)
540 extra_irq_enable: 0
541#endif
542}
543
544OBJECT stmmu07 TYPE swerver-thread-mmu {
545 full-swerver-decode: 1
546 niagara-mmu: 1
547 disable-sun4u-interrupts: 1
548 model-real-sfar: 1
549}
550
551#endif // SP0
552
553
554#ifdef SP1
555
556OBJECT swvp1 TYPE swerver-processor {
557 thread0: th08
558 thread1: th09
559 thread2: th10
560 thread3: th11
561 thread4: th12
562 thread5: th13
563 thread6: th14
564 thread7: th15
565 mmu:swmmu1
566}
567
568OBJECT swmmu1 TYPE swerver-proc-mmu {
569}
570
571OBJECT th08 TYPE niagara2 {
572 mmu: stmmu08
573 queue: th08
574 freq_mhz: 800
575 max-trap-levels: 6
576 va_bits: 48
577 physical_memory: phys_mem0
578 control_registers: (("mid", 8))
579 irq_bus: irqbus0
580 thread_id: 0
581 other_threads: (
582 th09,
583 th10,
584 th11,
585 th12,
586 th13,
587 th14,
588 th15
589 )
590#if defined(RTL) || defined(PLI_REPLAY)
591 extra_irq_enable: 0
592#endif
593}
594
595OBJECT stmmu08 TYPE swerver-thread-mmu {
596 full-swerver-decode: 1
597 niagara-mmu: 1
598 disable-sun4u-interrupts: 1
599 model-real-sfar: 1
600}
601
602OBJECT th09 TYPE niagara2 {
603 mmu: stmmu09
604 queue: th09
605 freq_mhz: 800
606 max-trap-levels: 6
607 va_bits: 48
608 physical_memory: phys_mem0
609 control_registers: (("mid", 9))
610 irq_bus: irqbus0
611 thread_id: 1
612 other_threads: (
613 th08,
614 th10,
615 th11,
616 th12,
617 th13,
618 th14,
619 th15
620 )
621#if defined(RTL) || defined(PLI_REPLAY)
622 extra_irq_enable: 0
623#endif
624}
625
626OBJECT stmmu09 TYPE swerver-thread-mmu {
627 full-swerver-decode: 1
628 niagara-mmu: 1
629 disable-sun4u-interrupts: 1
630 model-real-sfar: 1
631}
632
633OBJECT th10 TYPE niagara2 {
634 mmu: stmmu10
635 queue: th10
636 freq_mhz: 800
637 max-trap-levels: 6
638 va_bits: 48
639 physical_memory: phys_mem0
640 control_registers: (("mid", 10))
641 irq_bus: irqbus0
642 thread_id: 2
643 other_threads: (
644 th08,
645 th09,
646 th11,
647 th12,
648 th13,
649 th14,
650 th15
651 )
652#if defined(RTL) || defined(PLI_REPLAY)
653 extra_irq_enable: 0
654#endif
655}
656
657OBJECT stmmu10 TYPE swerver-thread-mmu {
658 full-swerver-decode: 1
659 niagara-mmu: 1
660 disable-sun4u-interrupts: 1
661 model-real-sfar: 1
662}
663
664OBJECT th11 TYPE niagara2 {
665 mmu: stmmu11
666 queue: th11
667 freq_mhz: 800
668 max-trap-levels: 6
669 va_bits: 48
670 physical_memory: phys_mem0
671 control_registers: (("mid", 11))
672 irq_bus: irqbus0
673 thread_id: 3
674 other_threads: (
675 th08,
676 th09,
677 th10,
678 th12,
679 th13,
680 th14,
681 th15
682 )
683#if defined(RTL) || defined(PLI_REPLAY)
684 extra_irq_enable: 0
685#endif
686}
687
688OBJECT stmmu11 TYPE swerver-thread-mmu {
689 full-swerver-decode: 1
690 niagara-mmu: 1
691 disable-sun4u-interrupts: 1
692 model-real-sfar: 1
693}
694
695OBJECT th12 TYPE niagara2 {
696 mmu: stmmu12
697 queue: th12
698 freq_mhz: 800
699 max-trap-levels: 6
700 va_bits: 48
701 physical_memory: phys_mem0
702 control_registers: (("mid", 12))
703 irq_bus: irqbus0
704 thread_id: 4
705 other_threads: (
706 th08,
707 th09,
708 th10,
709 th11,
710 th13,
711 th14,
712 th15
713 )
714#if defined(RTL) || defined(PLI_REPLAY)
715 extra_irq_enable: 0
716#endif
717}
718
719OBJECT stmmu12 TYPE swerver-thread-mmu {
720 full-swerver-decode: 1
721 niagara-mmu: 1
722 disable-sun4u-interrupts: 1
723 model-real-sfar: 1
724}
725
726OBJECT th13 TYPE niagara2 {
727 mmu: stmmu13
728 queue: th13
729 freq_mhz: 800
730 max-trap-levels: 6
731 va_bits: 48
732 physical_memory: phys_mem0
733 control_registers: (("mid", 13))
734 irq_bus: irqbus0
735 thread_id: 5
736 other_threads: (
737 th08,
738 th09,
739 th10,
740 th11,
741 th12,
742 th14,
743 th15
744 )
745#if defined(RTL) || defined(PLI_REPLAY)
746 extra_irq_enable: 0
747#endif
748}
749
750OBJECT stmmu13 TYPE swerver-thread-mmu {
751 full-swerver-decode: 1
752 niagara-mmu: 1
753 disable-sun4u-interrupts: 1
754 model-real-sfar: 1
755}
756
757OBJECT th14 TYPE niagara2 {
758 mmu: stmmu14
759 queue: th14
760 freq_mhz: 800
761 max-trap-levels: 6
762 va_bits: 48
763 physical_memory: phys_mem0
764 control_registers: (("mid", 14))
765 irq_bus: irqbus0
766 thread_id: 6
767 other_threads: (
768 th08,
769 th09,
770 th10,
771 th11,
772 th12,
773 th13,
774 th15
775 )
776#if defined(RTL) || defined(PLI_REPLAY)
777 extra_irq_enable: 0
778#endif
779}
780
781OBJECT stmmu14 TYPE swerver-thread-mmu {
782 full-swerver-decode: 1
783 niagara-mmu: 1
784 disable-sun4u-interrupts: 1
785 model-real-sfar: 1
786}
787
788OBJECT th15 TYPE niagara2 {
789 mmu: stmmu15
790 queue: th15
791 freq_mhz: 800
792 max-trap-levels: 6
793 va_bits: 48
794 physical_memory: phys_mem0
795 control_registers: (("mid", 15))
796 irq_bus: irqbus0
797 thread_id: 7
798 other_threads: (
799 th08,
800 th09,
801 th10,
802 th11,
803 th12,
804 th13,
805 th14
806 )
807#if defined(RTL) || defined(PLI_REPLAY)
808 extra_irq_enable: 0
809#endif
810}
811
812OBJECT stmmu15 TYPE swerver-thread-mmu {
813 full-swerver-decode: 1
814 niagara-mmu: 1
815 disable-sun4u-interrupts: 1
816 model-real-sfar: 1
817}
818
819#endif
820
821#ifdef SP2
822
823OBJECT swvp2 TYPE swerver-processor {
824 thread0: th16
825 thread1: th17
826 thread2: th18
827 thread3: th19
828 thread4: th20
829 thread5: th21
830 thread6: th22
831 thread7: th23
832 mmu:swmmu2
833}
834
835OBJECT swmmu2 TYPE swerver-proc-mmu {
836}
837
838OBJECT th16 TYPE niagara2 {
839 mmu: stmmu16
840 queue: th16
841 freq_mhz: 800
842 max-trap-levels: 6
843 va_bits: 48
844 physical_memory: phys_mem0
845 control_registers: (("mid", 16))
846 irq_bus: irqbus0
847 thread_id: 0
848 other_threads: (
849 th17,
850 th18,
851 th19,
852 th20,
853 th21,
854 th22,
855 th23
856 )
857#if defined(RTL) || defined(PLI_REPLAY)
858 extra_irq_enable: 0
859#endif
860}
861
862OBJECT stmmu16 TYPE swerver-thread-mmu {
863 full-swerver-decode: 1
864 niagara-mmu: 1
865 disable-sun4u-interrupts: 1
866 model-real-sfar: 1
867}
868
869OBJECT th17 TYPE niagara2 {
870 mmu: stmmu17
871 queue: th17
872 freq_mhz: 800
873 max-trap-levels: 6
874 va_bits: 48
875 physical_memory: phys_mem0
876 control_registers: (("mid", 17))
877 irq_bus: irqbus0
878 thread_id: 1
879 other_threads: (
880 th16,
881 th18,
882 th19,
883 th20,
884 th21,
885 th22,
886 th23
887 )
888#if defined(RTL) || defined(PLI_REPLAY)
889 extra_irq_enable: 0
890#endif
891}
892
893OBJECT stmmu17 TYPE swerver-thread-mmu {
894 full-swerver-decode: 1
895 niagara-mmu: 1
896 disable-sun4u-interrupts: 1
897 model-real-sfar: 1
898}
899
900OBJECT th18 TYPE niagara2 {
901 mmu: stmmu18
902 queue: th18
903 freq_mhz: 800
904 max-trap-levels: 6
905 va_bits: 48
906 physical_memory: phys_mem0
907 control_registers: (("mid", 18))
908 irq_bus: irqbus0
909 thread_id: 2
910 other_threads: (
911 th16,
912 th17,
913 th19,
914 th20,
915 th21,
916 th22,
917 th23
918 )
919#if defined(RTL) || defined(PLI_REPLAY)
920 extra_irq_enable: 0
921#endif
922}
923
924OBJECT stmmu18 TYPE swerver-thread-mmu {
925 full-swerver-decode: 1
926 niagara-mmu: 1
927 disable-sun4u-interrupts: 1
928 model-real-sfar: 1
929}
930
931OBJECT th19 TYPE niagara2 {
932 mmu: stmmu19
933 queue: th19
934 freq_mhz: 800
935 max-trap-levels: 6
936 va_bits: 48
937 physical_memory: phys_mem0
938 control_registers: (("mid", 19))
939 irq_bus: irqbus0
940 thread_id: 3
941 other_threads: (
942 th16,
943 th17,
944 th18,
945 th20,
946 th21,
947 th22,
948 th23
949 )
950#if defined(RTL) || defined(PLI_REPLAY)
951 extra_irq_enable: 0
952#endif
953}
954
955OBJECT stmmu19 TYPE swerver-thread-mmu {
956 full-swerver-decode: 1
957 niagara-mmu: 1
958 disable-sun4u-interrupts: 1
959 model-real-sfar: 1
960}
961
962OBJECT th20 TYPE niagara2 {
963 mmu: stmmu20
964 queue: th20
965 freq_mhz: 800
966 max-trap-levels: 6
967 va_bits: 48
968 physical_memory: phys_mem0
969 control_registers: (("mid", 20))
970 irq_bus: irqbus0
971 thread_id: 4
972 other_threads: (
973 th16,
974 th17,
975 th18,
976 th19,
977 th21,
978 th22,
979 th23
980 )
981#if defined(RTL) || defined(PLI_REPLAY)
982 extra_irq_enable: 0
983#endif
984}
985
986OBJECT stmmu20 TYPE swerver-thread-mmu {
987 full-swerver-decode: 1
988 niagara-mmu: 1
989 disable-sun4u-interrupts: 1
990 model-real-sfar: 1
991}
992
993OBJECT th21 TYPE niagara2 {
994 mmu: stmmu21
995 queue: th21
996 freq_mhz: 800
997 max-trap-levels: 6
998 va_bits: 48
999 physical_memory: phys_mem0
1000 control_registers: (("mid", 21))
1001 irq_bus: irqbus0
1002 thread_id: 5
1003 other_threads: (
1004 th16,
1005 th17,
1006 th18,
1007 th19,
1008 th20,
1009 th22,
1010 th23
1011 )
1012#if defined(RTL) || defined(PLI_REPLAY)
1013 extra_irq_enable: 0
1014#endif
1015}
1016
1017OBJECT stmmu21 TYPE swerver-thread-mmu {
1018 full-swerver-decode: 1
1019 niagara-mmu: 1
1020 disable-sun4u-interrupts: 1
1021 model-real-sfar: 1
1022}
1023
1024OBJECT th22 TYPE niagara2 {
1025 mmu: stmmu22
1026 queue: th22
1027 freq_mhz: 800
1028 max-trap-levels: 6
1029 va_bits: 48
1030 physical_memory: phys_mem0
1031 control_registers: (("mid", 22))
1032 irq_bus: irqbus0
1033 thread_id: 6
1034 other_threads: (
1035 th16,
1036 th17,
1037 th18,
1038 th19,
1039 th20,
1040 th21,
1041 th23
1042 )
1043#if defined(RTL) || defined(PLI_REPLAY)
1044 extra_irq_enable: 0
1045#endif
1046}
1047
1048OBJECT stmmu22 TYPE swerver-thread-mmu {
1049 full-swerver-decode: 1
1050 niagara-mmu: 1
1051 disable-sun4u-interrupts: 1
1052 model-real-sfar: 1
1053}
1054
1055OBJECT th23 TYPE niagara2 {
1056 mmu: stmmu23
1057 queue: th23
1058 freq_mhz: 800
1059 max-trap-levels: 6
1060 va_bits: 48
1061 physical_memory: phys_mem0
1062 control_registers: (("mid", 23))
1063 irq_bus: irqbus0
1064 thread_id: 7
1065 other_threads: (
1066 th16,
1067 th17,
1068 th18,
1069 th19,
1070 th20,
1071 th21,
1072 th22
1073 )
1074#if defined(RTL) || defined(PLI_REPLAY)
1075 extra_irq_enable: 0
1076#endif
1077}
1078
1079OBJECT stmmu23 TYPE swerver-thread-mmu {
1080 full-swerver-decode: 1
1081 niagara-mmu: 1
1082 disable-sun4u-interrupts: 1
1083 model-real-sfar: 1
1084}
1085
1086#endif
1087
1088#ifdef SP3
1089
1090OBJECT swvp3 TYPE swerver-processor {
1091 thread0: th24
1092 thread1: th25
1093 thread2: th26
1094 thread3: th27
1095 thread4: th28
1096 thread5: th29
1097 thread6: th30
1098 thread7: th31
1099 mmu:swmmu3
1100}
1101
1102OBJECT swmmu3 TYPE swerver-proc-mmu {
1103}
1104
1105OBJECT th24 TYPE niagara2 {
1106 mmu: stmmu24
1107 queue: th24
1108 freq_mhz: 800
1109 max-trap-levels: 6
1110 va_bits: 48
1111 physical_memory: phys_mem0
1112 control_registers: (("mid", 24))
1113 irq_bus: irqbus0
1114 thread_id: 0
1115 other_threads: (
1116 th25,
1117 th26,
1118 th27,
1119 th28,
1120 th29,
1121 th30,
1122 th31
1123 )
1124#if defined(RTL) || defined(PLI_REPLAY)
1125 extra_irq_enable: 0
1126#endif
1127}
1128
1129OBJECT stmmu24 TYPE swerver-thread-mmu {
1130 full-swerver-decode: 1
1131 niagara-mmu: 1
1132 disable-sun4u-interrupts: 1
1133 model-real-sfar: 1
1134}
1135
1136OBJECT th25 TYPE niagara2 {
1137 mmu: stmmu25
1138 queue: th25
1139 freq_mhz: 800
1140 max-trap-levels: 6
1141 va_bits: 48
1142 physical_memory: phys_mem0
1143 control_registers: (("mid", 25))
1144 irq_bus: irqbus0
1145 thread_id: 1
1146 other_threads: (
1147 th24,
1148 th26,
1149 th27,
1150 th28,
1151 th29,
1152 th30,
1153 th31
1154 )
1155#if defined(RTL) || defined(PLI_REPLAY)
1156 extra_irq_enable: 0
1157#endif
1158}
1159
1160OBJECT stmmu25 TYPE swerver-thread-mmu {
1161 full-swerver-decode: 1
1162 niagara-mmu: 1
1163 disable-sun4u-interrupts: 1
1164 model-real-sfar: 1
1165}
1166
1167OBJECT th26 TYPE niagara2 {
1168 mmu: stmmu26
1169 queue: th26
1170 freq_mhz: 800
1171 max-trap-levels: 6
1172 va_bits: 48
1173 physical_memory: phys_mem0
1174 control_registers: (("mid", 26))
1175 irq_bus: irqbus0
1176 thread_id: 2
1177 other_threads: (
1178 th24,
1179 th25,
1180 th27,
1181 th28,
1182 th29,
1183 th30,
1184 th31
1185 )
1186#if defined(RTL) || defined(PLI_REPLAY)
1187 extra_irq_enable: 0
1188#endif
1189}
1190
1191OBJECT stmmu26 TYPE swerver-thread-mmu {
1192 full-swerver-decode: 1
1193 niagara-mmu: 1
1194 disable-sun4u-interrupts: 1
1195 model-real-sfar: 1
1196}
1197
1198OBJECT th27 TYPE niagara2 {
1199 mmu: stmmu27
1200 queue: th27
1201 freq_mhz: 800
1202 max-trap-levels: 6
1203 va_bits: 48
1204 physical_memory: phys_mem0
1205 control_registers: (("mid", 27))
1206 irq_bus: irqbus0
1207 thread_id: 3
1208 other_threads: (
1209 th24,
1210 th25,
1211 th26,
1212 th28,
1213 th29,
1214 th30,
1215 th31
1216 )
1217#if defined(RTL) || defined(PLI_REPLAY)
1218 extra_irq_enable: 0
1219#endif
1220}
1221
1222OBJECT stmmu27 TYPE swerver-thread-mmu {
1223 full-swerver-decode: 1
1224 niagara-mmu: 1
1225 disable-sun4u-interrupts: 1
1226 model-real-sfar: 1
1227}
1228
1229OBJECT th28 TYPE niagara2 {
1230 mmu: stmmu28
1231 queue: th28
1232 freq_mhz: 800
1233 max-trap-levels: 6
1234 va_bits: 48
1235 physical_memory: phys_mem0
1236 control_registers: (("mid", 28))
1237 irq_bus: irqbus0
1238 thread_id: 4
1239 other_threads: (
1240 th24,
1241 th25,
1242 th26,
1243 th27,
1244 th29,
1245 th30,
1246 th31
1247 )
1248#if defined(RTL) || defined(PLI_REPLAY)
1249 extra_irq_enable: 0
1250#endif
1251}
1252
1253OBJECT stmmu28 TYPE swerver-thread-mmu {
1254 full-swerver-decode: 1
1255 niagara-mmu: 1
1256 disable-sun4u-interrupts: 1
1257 model-real-sfar: 1
1258}
1259
1260OBJECT th29 TYPE niagara2 {
1261 mmu: stmmu29
1262 queue: th29
1263 freq_mhz: 800
1264 max-trap-levels: 6
1265 va_bits: 48
1266 physical_memory: phys_mem0
1267 control_registers: (("mid", 29))
1268 irq_bus: irqbus0
1269 thread_id: 5
1270 other_threads: (
1271 th24,
1272 th25,
1273 th26,
1274 th27,
1275 th28,
1276 th30,
1277 th31
1278 )
1279#if defined(RTL) || defined(PLI_REPLAY)
1280 extra_irq_enable: 0
1281#endif
1282}
1283
1284OBJECT stmmu29 TYPE swerver-thread-mmu {
1285 full-swerver-decode: 1
1286 niagara-mmu: 1
1287 disable-sun4u-interrupts: 1
1288 model-real-sfar: 1
1289}
1290
1291OBJECT th30 TYPE niagara2 {
1292 mmu: stmmu30
1293 queue: th30
1294 freq_mhz: 800
1295 max-trap-levels: 6
1296 va_bits: 48
1297 physical_memory: phys_mem0
1298 control_registers: (("mid", 30))
1299 irq_bus: irqbus0
1300 thread_id: 6
1301 other_threads: (
1302 th24,
1303 th25,
1304 th26,
1305 th27,
1306 th28,
1307 th29,
1308 th31
1309 )
1310#if defined(RTL) || defined(PLI_REPLAY)
1311 extra_irq_enable: 0
1312#endif
1313}
1314
1315OBJECT stmmu30 TYPE swerver-thread-mmu {
1316 full-swerver-decode: 1
1317 niagara-mmu: 1
1318 disable-sun4u-interrupts: 1
1319 model-real-sfar: 1
1320}
1321
1322OBJECT th31 TYPE niagara2 {
1323 mmu: stmmu31
1324 queue: th31
1325 freq_mhz: 800
1326 max-trap-levels: 6
1327 va_bits: 48
1328 physical_memory: phys_mem0
1329 control_registers: (("mid", 31))
1330 irq_bus: irqbus0
1331 thread_id: 7
1332 other_threads: (
1333 th24,
1334 th25,
1335 th26,
1336 th27,
1337 th28,
1338 th29,
1339 th30
1340 )
1341#if defined(RTL) || defined(PLI_REPLAY)
1342 extra_irq_enable: 0
1343#endif
1344}
1345
1346OBJECT stmmu31 TYPE swerver-thread-mmu {
1347 full-swerver-decode: 1
1348 niagara-mmu: 1
1349 disable-sun4u-interrupts: 1
1350 model-real-sfar: 1
1351}
1352
1353#endif
1354
1355#ifdef SP4
1356
1357OBJECT swvp4 TYPE swerver-processor {
1358 thread0: th32
1359 thread1: th33
1360 thread2: th34
1361 thread3: th35
1362 thread4: th36
1363 thread5: th37
1364 thread6: th38
1365 thread7: th39
1366 mmu:swmmu4
1367}
1368
1369OBJECT swmmu4 TYPE swerver-proc-mmu {
1370}
1371
1372OBJECT th32 TYPE niagara2 {
1373 mmu: stmmu32
1374 queue: th32
1375 freq_mhz: 800
1376 max-trap-levels: 6
1377 va_bits: 48
1378 physical_memory: phys_mem0
1379 control_registers: (("mid", 32))
1380 irq_bus: irqbus0
1381 thread_id: 0
1382 other_threads: (
1383 th33,
1384 th34,
1385 th35,
1386 th36,
1387 th37,
1388 th38,
1389 th39
1390 )
1391#if defined(RTL) || defined(PLI_REPLAY)
1392 extra_irq_enable: 0
1393#endif
1394}
1395
1396OBJECT stmmu32 TYPE swerver-thread-mmu {
1397 full-swerver-decode: 1
1398 niagara-mmu: 1
1399 disable-sun4u-interrupts: 1
1400 model-real-sfar: 1
1401}
1402
1403OBJECT th33 TYPE niagara2 {
1404 mmu: stmmu33
1405 queue: th33
1406 freq_mhz: 800
1407 max-trap-levels: 6
1408 va_bits: 48
1409 physical_memory: phys_mem0
1410 control_registers: (("mid", 33))
1411 irq_bus: irqbus0
1412 thread_id: 1
1413 other_threads: (
1414 th32,
1415 th34,
1416 th35,
1417 th36,
1418 th37,
1419 th38,
1420 th39
1421 )
1422#if defined(RTL) || defined(PLI_REPLAY)
1423 extra_irq_enable: 0
1424#endif
1425}
1426
1427OBJECT stmmu33 TYPE swerver-thread-mmu {
1428 full-swerver-decode: 1
1429 niagara-mmu: 1
1430 disable-sun4u-interrupts: 1
1431 model-real-sfar: 1
1432}
1433
1434OBJECT th34 TYPE niagara2 {
1435 mmu: stmmu34
1436 queue: th34
1437 freq_mhz: 800
1438 max-trap-levels: 6
1439 va_bits: 48
1440 physical_memory: phys_mem0
1441 control_registers: (("mid", 34))
1442 irq_bus: irqbus0
1443 thread_id: 2
1444 other_threads: (
1445 th32,
1446 th33,
1447 th35,
1448 th36,
1449 th37,
1450 th38,
1451 th39
1452 )
1453#if defined(RTL) || defined(PLI_REPLAY)
1454 extra_irq_enable: 0
1455#endif
1456}
1457
1458OBJECT stmmu34 TYPE swerver-thread-mmu {
1459 full-swerver-decode: 1
1460 niagara-mmu: 1
1461 disable-sun4u-interrupts: 1
1462 model-real-sfar: 1
1463}
1464
1465OBJECT th35 TYPE niagara2 {
1466 mmu: stmmu35
1467 queue: th35
1468 freq_mhz: 800
1469 max-trap-levels: 6
1470 va_bits: 48
1471 physical_memory: phys_mem0
1472 control_registers: (("mid", 35))
1473 irq_bus: irqbus0
1474 thread_id: 3
1475 other_threads: (
1476 th32,
1477 th33,
1478 th34,
1479 th36,
1480 th37,
1481 th38,
1482 th39
1483 )
1484#if defined(RTL) || defined(PLI_REPLAY)
1485 extra_irq_enable: 0
1486#endif
1487}
1488
1489OBJECT stmmu35 TYPE swerver-thread-mmu {
1490 full-swerver-decode: 1
1491 niagara-mmu: 1
1492 disable-sun4u-interrupts: 1
1493 model-real-sfar: 1
1494}
1495
1496OBJECT th36 TYPE niagara2 {
1497 mmu: stmmu36
1498 queue: th36
1499 freq_mhz: 800
1500 max-trap-levels: 6
1501 va_bits: 48
1502 physical_memory: phys_mem0
1503 control_registers: (("mid", 36))
1504 irq_bus: irqbus0
1505 thread_id: 4
1506 other_threads: (
1507 th32,
1508 th33,
1509 th34,
1510 th35,
1511 th37,
1512 th38,
1513 th39
1514 )
1515#if defined(RTL) || defined(PLI_REPLAY)
1516 extra_irq_enable: 0
1517#endif
1518}
1519
1520OBJECT stmmu36 TYPE swerver-thread-mmu {
1521 full-swerver-decode: 1
1522 niagara-mmu: 1
1523 disable-sun4u-interrupts: 1
1524 model-real-sfar: 1
1525}
1526
1527OBJECT th37 TYPE niagara2 {
1528 mmu: stmmu37
1529 queue: th37
1530 freq_mhz: 800
1531 max-trap-levels: 6
1532 va_bits: 48
1533 physical_memory: phys_mem0
1534 control_registers: (("mid", 37))
1535 irq_bus: irqbus0
1536 thread_id: 5
1537 other_threads: (
1538 th32,
1539 th33,
1540 th34,
1541 th35,
1542 th36,
1543 th38,
1544 th39
1545 )
1546#if defined(RTL) || defined(PLI_REPLAY)
1547 extra_irq_enable: 0
1548#endif
1549}
1550
1551OBJECT stmmu37 TYPE swerver-thread-mmu {
1552 full-swerver-decode: 1
1553 niagara-mmu: 1
1554 disable-sun4u-interrupts: 1
1555 model-real-sfar: 1
1556}
1557
1558OBJECT th38 TYPE niagara2 {
1559 mmu: stmmu38
1560 queue: th38
1561 freq_mhz: 800
1562 max-trap-levels: 6
1563 va_bits: 48
1564 physical_memory: phys_mem0
1565 control_registers: (("mid", 38))
1566 irq_bus: irqbus0
1567 thread_id: 6
1568 other_threads: (
1569 th32,
1570 th33,
1571 th34,
1572 th35,
1573 th36,
1574 th37,
1575 th39
1576 )
1577#if defined(RTL) || defined(PLI_REPLAY)
1578 extra_irq_enable: 0
1579#endif
1580}
1581
1582OBJECT stmmu38 TYPE swerver-thread-mmu {
1583 full-swerver-decode: 1
1584 niagara-mmu: 1
1585 disable-sun4u-interrupts: 1
1586 model-real-sfar: 1
1587}
1588
1589OBJECT th39 TYPE niagara2 {
1590 mmu: stmmu39
1591 queue: th39
1592 freq_mhz: 800
1593 max-trap-levels: 6
1594 va_bits: 48
1595 physical_memory: phys_mem0
1596 control_registers: (("mid", 39))
1597 irq_bus: irqbus0
1598 thread_id: 7
1599 other_threads: (
1600 th32,
1601 th33,
1602 th34,
1603 th35,
1604 th36,
1605 th37,
1606 th38
1607 )
1608#if defined(RTL) || defined(PLI_REPLAY)
1609 extra_irq_enable: 0
1610#endif
1611}
1612
1613OBJECT stmmu39 TYPE swerver-thread-mmu {
1614 full-swerver-decode: 1
1615 niagara-mmu: 1
1616 disable-sun4u-interrupts: 1
1617 model-real-sfar: 1
1618}
1619
1620#endif
1621
1622#ifdef SP5
1623
1624OBJECT swvp5 TYPE swerver-processor {
1625 thread0: th40
1626 thread1: th41
1627 thread2: th42
1628 thread3: th43
1629 thread4: th44
1630 thread5: th45
1631 thread6: th46
1632 thread7: th47
1633 mmu:swmmu5
1634}
1635
1636OBJECT swmmu5 TYPE swerver-proc-mmu {
1637}
1638
1639OBJECT th40 TYPE niagara2 {
1640 mmu: stmmu40
1641 queue: th40
1642 freq_mhz: 800
1643 max-trap-levels: 6
1644 va_bits: 48
1645 physical_memory: phys_mem0
1646 control_registers: (("mid", 40))
1647 irq_bus: irqbus0
1648 thread_id: 0
1649 other_threads: (
1650 th41,
1651 th42,
1652 th43,
1653 th44,
1654 th45,
1655 th46,
1656 th47
1657 )
1658#if defined(RTL) || defined(PLI_REPLAY)
1659 extra_irq_enable: 0
1660#endif
1661}
1662
1663OBJECT stmmu40 TYPE swerver-thread-mmu {
1664 full-swerver-decode: 1
1665 niagara-mmu: 1
1666 disable-sun4u-interrupts: 1
1667 model-real-sfar: 1
1668}
1669
1670OBJECT th41 TYPE niagara2 {
1671 mmu: stmmu41
1672 queue: th41
1673 freq_mhz: 800
1674 max-trap-levels: 6
1675 va_bits: 48
1676 physical_memory: phys_mem0
1677 control_registers: (("mid", 41))
1678 irq_bus: irqbus0
1679 thread_id: 1
1680 other_threads: (
1681 th40,
1682 th42,
1683 th43,
1684 th44,
1685 th45,
1686 th46,
1687 th47
1688 )
1689#if defined(RTL) || defined(PLI_REPLAY)
1690 extra_irq_enable: 0
1691#endif
1692}
1693
1694OBJECT stmmu41 TYPE swerver-thread-mmu {
1695 full-swerver-decode: 1
1696 niagara-mmu: 1
1697 disable-sun4u-interrupts: 1
1698 model-real-sfar: 1
1699}
1700
1701OBJECT th42 TYPE niagara2 {
1702 mmu: stmmu42
1703 queue: th42
1704 freq_mhz: 800
1705 max-trap-levels: 6
1706 va_bits: 48
1707 physical_memory: phys_mem0
1708 control_registers: (("mid", 42))
1709 irq_bus: irqbus0
1710 thread_id: 2
1711 other_threads: (
1712 th40,
1713 th41,
1714 th43,
1715 th44,
1716 th45,
1717 th46,
1718 th47
1719 )
1720#if defined(RTL) || defined(PLI_REPLAY)
1721 extra_irq_enable: 0
1722#endif
1723}
1724
1725OBJECT stmmu42 TYPE swerver-thread-mmu {
1726 full-swerver-decode: 1
1727 niagara-mmu: 1
1728 disable-sun4u-interrupts: 1
1729 model-real-sfar: 1
1730}
1731
1732OBJECT th43 TYPE niagara2 {
1733 mmu: stmmu43
1734 queue: th43
1735 freq_mhz: 800
1736 max-trap-levels: 6
1737 va_bits: 48
1738 physical_memory: phys_mem0
1739 control_registers: (("mid", 43))
1740 irq_bus: irqbus0
1741 thread_id: 3
1742 other_threads: (
1743 th40,
1744 th41,
1745 th42,
1746 th44,
1747 th45,
1748 th46,
1749 th47
1750 )
1751#if defined(RTL) || defined(PLI_REPLAY)
1752 extra_irq_enable: 0
1753#endif
1754}
1755
1756OBJECT stmmu43 TYPE swerver-thread-mmu {
1757 full-swerver-decode: 1
1758 niagara-mmu: 1
1759 disable-sun4u-interrupts: 1
1760 model-real-sfar: 1
1761}
1762
1763OBJECT th44 TYPE niagara2 {
1764 mmu: stmmu44
1765 queue: th44
1766 freq_mhz: 800
1767 max-trap-levels: 6
1768 va_bits: 48
1769 physical_memory: phys_mem0
1770 control_registers: (("mid", 44))
1771 irq_bus: irqbus0
1772 thread_id: 4
1773 other_threads: (
1774 th40,
1775 th41,
1776 th42,
1777 th43,
1778 th45,
1779 th46,
1780 th47
1781 )
1782#if defined(RTL) || defined(PLI_REPLAY)
1783 extra_irq_enable: 0
1784#endif
1785}
1786
1787OBJECT stmmu44 TYPE swerver-thread-mmu {
1788 full-swerver-decode: 1
1789 niagara-mmu: 1
1790 disable-sun4u-interrupts: 1
1791 model-real-sfar: 1
1792}
1793
1794OBJECT th45 TYPE niagara2 {
1795 mmu: stmmu45
1796 queue: th45
1797 freq_mhz: 800
1798 max-trap-levels: 6
1799 va_bits: 48
1800 physical_memory: phys_mem0
1801 control_registers: (("mid", 45))
1802 irq_bus: irqbus0
1803 thread_id: 5
1804 other_threads: (
1805 th40,
1806 th41,
1807 th42,
1808 th43,
1809 th44,
1810 th46,
1811 th47
1812 )
1813#if defined(RTL) || defined(PLI_REPLAY)
1814 extra_irq_enable: 0
1815#endif
1816}
1817
1818OBJECT stmmu45 TYPE swerver-thread-mmu {
1819 full-swerver-decode: 1
1820 niagara-mmu: 1
1821 disable-sun4u-interrupts: 1
1822 model-real-sfar: 1
1823}
1824
1825OBJECT th46 TYPE niagara2 {
1826 mmu: stmmu46
1827 queue: th46
1828 freq_mhz: 800
1829 max-trap-levels: 6
1830 va_bits: 48
1831 physical_memory: phys_mem0
1832 control_registers: (("mid", 46))
1833 irq_bus: irqbus0
1834 thread_id: 6
1835 other_threads: (
1836 th40,
1837 th41,
1838 th42,
1839 th43,
1840 th44,
1841 th45,
1842 th47
1843 )
1844#if defined(RTL) || defined(PLI_REPLAY)
1845 extra_irq_enable: 0
1846#endif
1847}
1848
1849OBJECT stmmu46 TYPE swerver-thread-mmu {
1850 full-swerver-decode: 1
1851 niagara-mmu: 1
1852 disable-sun4u-interrupts: 1
1853 model-real-sfar: 1
1854}
1855
1856OBJECT th47 TYPE niagara2 {
1857 mmu: stmmu47
1858 queue: th47
1859 freq_mhz: 800
1860 max-trap-levels: 6
1861 va_bits: 48
1862 physical_memory: phys_mem0
1863 control_registers: (("mid", 47))
1864 irq_bus: irqbus0
1865 thread_id: 7
1866 other_threads: (
1867 th40,
1868 th41,
1869 th42,
1870 th43,
1871 th44,
1872 th45,
1873 th46
1874 )
1875#if defined(RTL) || defined(PLI_REPLAY)
1876 extra_irq_enable: 0
1877#endif
1878}
1879
1880OBJECT stmmu47 TYPE swerver-thread-mmu {
1881 full-swerver-decode: 1
1882 niagara-mmu: 1
1883 disable-sun4u-interrupts: 1
1884 model-real-sfar: 1
1885}
1886
1887#endif
1888
1889#ifdef SP6
1890
1891OBJECT swvp6 TYPE swerver-processor {
1892 thread0: th48
1893 thread1: th49
1894 thread2: th50
1895 thread3: th51
1896 thread4: th52
1897 thread5: th53
1898 thread6: th54
1899 thread7: th55
1900 mmu:swmmu6
1901}
1902
1903OBJECT swmmu6 TYPE swerver-proc-mmu {
1904}
1905
1906OBJECT th48 TYPE niagara2 {
1907 mmu: stmmu48
1908 queue: th48
1909 freq_mhz: 800
1910 max-trap-levels: 6
1911 va_bits: 48
1912 physical_memory: phys_mem0
1913 control_registers: (("mid", 48))
1914 irq_bus: irqbus0
1915 thread_id: 0
1916 other_threads: (
1917 th49,
1918 th50,
1919 th51,
1920 th52,
1921 th53,
1922 th54,
1923 th55
1924 )
1925#if defined(RTL) || defined(PLI_REPLAY)
1926 extra_irq_enable: 0
1927#endif
1928}
1929
1930OBJECT stmmu48 TYPE swerver-thread-mmu {
1931 full-swerver-decode: 1
1932 niagara-mmu: 1
1933 disable-sun4u-interrupts: 1
1934 model-real-sfar: 1
1935}
1936
1937OBJECT th49 TYPE niagara2 {
1938 mmu: stmmu49
1939 queue: th49
1940 freq_mhz: 800
1941 max-trap-levels: 6
1942 va_bits: 48
1943 physical_memory: phys_mem0
1944 control_registers: (("mid", 49))
1945 irq_bus: irqbus0
1946 thread_id: 1
1947 other_threads: (
1948 th48,
1949 th50,
1950 th51,
1951 th52,
1952 th53,
1953 th54,
1954 th55
1955 )
1956#if defined(RTL) || defined(PLI_REPLAY)
1957 extra_irq_enable: 0
1958#endif
1959}
1960
1961OBJECT stmmu49 TYPE swerver-thread-mmu {
1962 full-swerver-decode: 1
1963 niagara-mmu: 1
1964 disable-sun4u-interrupts: 1
1965 model-real-sfar: 1
1966}
1967
1968OBJECT th50 TYPE niagara2 {
1969 mmu: stmmu50
1970 queue: th50
1971 freq_mhz: 800
1972 max-trap-levels: 6
1973 va_bits: 48
1974 physical_memory: phys_mem0
1975 control_registers: (("mid", 50))
1976 irq_bus: irqbus0
1977 thread_id: 2
1978 other_threads: (
1979 th48,
1980 th49,
1981 th51,
1982 th52,
1983 th53,
1984 th54,
1985 th55
1986 )
1987#if defined(RTL) || defined(PLI_REPLAY)
1988 extra_irq_enable: 0
1989#endif
1990}
1991
1992OBJECT stmmu50 TYPE swerver-thread-mmu {
1993 full-swerver-decode: 1
1994 niagara-mmu: 1
1995 disable-sun4u-interrupts: 1
1996 model-real-sfar: 1
1997}
1998
1999OBJECT th51 TYPE niagara2 {
2000 mmu: stmmu51
2001 queue: th51
2002 freq_mhz: 800
2003 max-trap-levels: 6
2004 va_bits: 48
2005 physical_memory: phys_mem0
2006 control_registers: (("mid", 51))
2007 irq_bus: irqbus0
2008 thread_id: 3
2009 other_threads: (
2010 th48,
2011 th49,
2012 th50,
2013 th52,
2014 th53,
2015 th54,
2016 th55
2017 )
2018#if defined(RTL) || defined(PLI_REPLAY)
2019 extra_irq_enable: 0
2020#endif
2021}
2022
2023OBJECT stmmu51 TYPE swerver-thread-mmu {
2024 full-swerver-decode: 1
2025 niagara-mmu: 1
2026 disable-sun4u-interrupts: 1
2027 model-real-sfar: 1
2028}
2029
2030OBJECT th52 TYPE niagara2 {
2031 mmu: stmmu52
2032 queue: th52
2033 freq_mhz: 800
2034 max-trap-levels: 6
2035 va_bits: 48
2036 physical_memory: phys_mem0
2037 control_registers: (("mid", 52))
2038 irq_bus: irqbus0
2039 thread_id: 4
2040 other_threads: (
2041 th48,
2042 th49,
2043 th50,
2044 th51,
2045 th53,
2046 th54,
2047 th55
2048 )
2049#if defined(RTL) || defined(PLI_REPLAY)
2050 extra_irq_enable: 0
2051#endif
2052}
2053
2054OBJECT stmmu52 TYPE swerver-thread-mmu {
2055 full-swerver-decode: 1
2056 niagara-mmu: 1
2057 disable-sun4u-interrupts: 1
2058 model-real-sfar: 1
2059}
2060
2061OBJECT th53 TYPE niagara2 {
2062 mmu: stmmu53
2063 queue: th53
2064 freq_mhz: 800
2065 max-trap-levels: 6
2066 va_bits: 48
2067 physical_memory: phys_mem0
2068 control_registers: (("mid", 53))
2069 irq_bus: irqbus0
2070 thread_id: 5
2071 other_threads: (
2072 th48,
2073 th49,
2074 th50,
2075 th51,
2076 th52,
2077 th54,
2078 th55
2079 )
2080#if defined(RTL) || defined(PLI_REPLAY)
2081 extra_irq_enable: 0
2082#endif
2083}
2084
2085OBJECT stmmu53 TYPE swerver-thread-mmu {
2086 full-swerver-decode: 1
2087 niagara-mmu: 1
2088 disable-sun4u-interrupts: 1
2089 model-real-sfar: 1
2090}
2091
2092OBJECT th54 TYPE niagara2 {
2093 mmu: stmmu54
2094 queue: th54
2095 freq_mhz: 800
2096 max-trap-levels: 6
2097 va_bits: 48
2098 physical_memory: phys_mem0
2099 control_registers: (("mid", 54))
2100 irq_bus: irqbus0
2101 thread_id: 6
2102 other_threads: (
2103 th48,
2104 th49,
2105 th50,
2106 th51,
2107 th52,
2108 th53,
2109 th55
2110 )
2111#if defined(RTL) || defined(PLI_REPLAY)
2112 extra_irq_enable: 0
2113#endif
2114}
2115
2116OBJECT stmmu54 TYPE swerver-thread-mmu {
2117 full-swerver-decode: 1
2118 niagara-mmu: 1
2119 disable-sun4u-interrupts: 1
2120 model-real-sfar: 1
2121}
2122
2123OBJECT th55 TYPE niagara2 {
2124 mmu: stmmu55
2125 queue: th55
2126 freq_mhz: 800
2127 max-trap-levels: 6
2128 va_bits: 48
2129 physical_memory: phys_mem0
2130 control_registers: (("mid", 55))
2131 irq_bus: irqbus0
2132 thread_id: 7
2133 other_threads: (
2134 th48,
2135 th49,
2136 th50,
2137 th51,
2138 th52,
2139 th53,
2140 th54
2141 )
2142#if defined(RTL) || defined(PLI_REPLAY)
2143 extra_irq_enable: 0
2144#endif
2145}
2146
2147OBJECT stmmu55 TYPE swerver-thread-mmu {
2148 full-swerver-decode: 1
2149 niagara-mmu: 1
2150 disable-sun4u-interrupts: 1
2151 model-real-sfar: 1
2152}
2153
2154#endif
2155
2156#ifdef SP7
2157
2158OBJECT swvp7 TYPE swerver-processor {
2159 thread0: th56
2160 thread1: th57
2161 thread2: th58
2162 thread3: th59
2163 thread4: th60
2164 thread5: th61
2165 thread6: th62
2166 thread7: th63
2167 mmu:swmmu7
2168}
2169
2170OBJECT swmmu7 TYPE swerver-proc-mmu {
2171}
2172
2173OBJECT th56 TYPE niagara2 {
2174 mmu: stmmu56
2175 queue: th56
2176 freq_mhz: 800
2177 max-trap-levels: 6
2178 va_bits: 48
2179 physical_memory: phys_mem0
2180 control_registers: (("mid", 56))
2181 irq_bus: irqbus0
2182 thread_id: 0
2183 other_threads: (
2184 th57,
2185 th58,
2186 th59,
2187 th60,
2188 th61,
2189 th62,
2190 th63
2191 )
2192#if defined(RTL) || defined(PLI_REPLAY)
2193 extra_irq_enable: 0
2194#endif
2195}
2196
2197OBJECT stmmu56 TYPE swerver-thread-mmu {
2198 full-swerver-decode: 1
2199 niagara-mmu: 1
2200 disable-sun4u-interrupts: 1
2201 model-real-sfar: 1
2202}
2203
2204OBJECT th57 TYPE niagara2 {
2205 mmu: stmmu57
2206 queue: th57
2207 freq_mhz: 800
2208 max-trap-levels: 6
2209 va_bits: 48
2210 physical_memory: phys_mem0
2211 control_registers: (("mid", 57))
2212 irq_bus: irqbus0
2213 thread_id: 1
2214 other_threads: (
2215 th56,
2216 th58,
2217 th59,
2218 th60,
2219 th61,
2220 th62,
2221 th63
2222 )
2223#if defined(RTL) || defined(PLI_REPLAY)
2224 extra_irq_enable: 0
2225#endif
2226}
2227
2228OBJECT stmmu57 TYPE swerver-thread-mmu {
2229 full-swerver-decode: 1
2230 niagara-mmu: 1
2231 disable-sun4u-interrupts: 1
2232 model-real-sfar: 1
2233}
2234
2235OBJECT th58 TYPE niagara2 {
2236 mmu: stmmu58
2237 queue: th58
2238 freq_mhz: 800
2239 max-trap-levels: 6
2240 va_bits: 48
2241 physical_memory: phys_mem0
2242 control_registers: (("mid", 58))
2243 irq_bus: irqbus0
2244 thread_id: 2
2245 other_threads: (
2246 th56,
2247 th57,
2248 th59,
2249 th60,
2250 th61,
2251 th62,
2252 th63
2253 )
2254#if defined(RTL) || defined(PLI_REPLAY)
2255 extra_irq_enable: 0
2256#endif
2257}
2258
2259OBJECT stmmu58 TYPE swerver-thread-mmu {
2260 full-swerver-decode: 1
2261 niagara-mmu: 1
2262 disable-sun4u-interrupts: 1
2263 model-real-sfar: 1
2264}
2265
2266OBJECT th59 TYPE niagara2 {
2267 mmu: stmmu59
2268 queue: th59
2269 freq_mhz: 800
2270 max-trap-levels: 6
2271 va_bits: 48
2272 physical_memory: phys_mem0
2273 control_registers: (("mid", 59))
2274 irq_bus: irqbus0
2275 thread_id: 3
2276 other_threads: (
2277 th56,
2278 th57,
2279 th58,
2280 th60,
2281 th61,
2282 th62,
2283 th63
2284 )
2285#if defined(RTL) || defined(PLI_REPLAY)
2286 extra_irq_enable: 0
2287#endif
2288}
2289
2290OBJECT stmmu59 TYPE swerver-thread-mmu {
2291 full-swerver-decode: 1
2292 niagara-mmu: 1
2293 disable-sun4u-interrupts: 1
2294 model-real-sfar: 1
2295}
2296
2297OBJECT th60 TYPE niagara2 {
2298 mmu: stmmu60
2299 queue: th60
2300 freq_mhz: 800
2301 max-trap-levels: 6
2302 va_bits: 48
2303 physical_memory: phys_mem0
2304 control_registers: (("mid", 60))
2305 irq_bus: irqbus0
2306 thread_id: 4
2307 other_threads: (
2308 th56,
2309 th57,
2310 th58,
2311 th59,
2312 th61,
2313 th62,
2314 th63
2315 )
2316#if defined(RTL) || defined(PLI_REPLAY)
2317 extra_irq_enable: 0
2318#endif
2319}
2320
2321OBJECT stmmu60 TYPE swerver-thread-mmu {
2322 full-swerver-decode: 1
2323 niagara-mmu: 1
2324 disable-sun4u-interrupts: 1
2325 model-real-sfar: 1
2326}
2327
2328OBJECT th61 TYPE niagara2 {
2329 mmu: stmmu61
2330 queue: th61
2331 freq_mhz: 800
2332 max-trap-levels: 6
2333 va_bits: 48
2334 physical_memory: phys_mem0
2335 control_registers: (("mid", 61))
2336 irq_bus: irqbus0
2337 thread_id: 5
2338 other_threads: (
2339 th56,
2340 th57,
2341 th58,
2342 th59,
2343 th60,
2344 th62,
2345 th63
2346 )
2347#if defined(RTL) || defined(PLI_REPLAY)
2348 extra_irq_enable: 0
2349#endif
2350}
2351
2352OBJECT stmmu61 TYPE swerver-thread-mmu {
2353 full-swerver-decode: 1
2354 niagara-mmu: 1
2355 disable-sun4u-interrupts: 1
2356 model-real-sfar: 1
2357}
2358
2359OBJECT th62 TYPE niagara2 {
2360 mmu: stmmu62
2361 queue: th62
2362 freq_mhz: 800
2363 max-trap-levels: 6
2364 va_bits: 48
2365 physical_memory: phys_mem0
2366 control_registers: (("mid", 62))
2367 irq_bus: irqbus0
2368 thread_id: 6
2369 other_threads: (
2370 th56,
2371 th57,
2372 th58,
2373 th59,
2374 th60,
2375 th61,
2376 th63
2377 )
2378#if defined(RTL) || defined(PLI_REPLAY)
2379 extra_irq_enable: 0
2380#endif
2381}
2382
2383OBJECT stmmu62 TYPE swerver-thread-mmu {
2384 full-swerver-decode: 1
2385 niagara-mmu: 1
2386 disable-sun4u-interrupts: 1
2387 model-real-sfar: 1
2388}
2389
2390OBJECT th63 TYPE niagara2 {
2391 mmu: stmmu63
2392 queue: th63
2393 freq_mhz: 800
2394 max-trap-levels: 6
2395 va_bits: 48
2396 physical_memory: phys_mem0
2397 control_registers: (("mid", 63))
2398 irq_bus: irqbus0
2399 thread_id: 7
2400 other_threads: (
2401 th56,
2402 th57,
2403 th58,
2404 th59,
2405 th60,
2406 th61,
2407 th62
2408 )
2409#if defined(RTL) || defined(PLI_REPLAY)
2410 extra_irq_enable: 0
2411#endif
2412}
2413
2414OBJECT stmmu63 TYPE swerver-thread-mmu {
2415 full-swerver-decode: 1
2416 niagara-mmu: 1
2417 disable-sun4u-interrupts: 1
2418 model-real-sfar: 1
2419}
2420
2421#endif
2422
2423OBJECT phys_mem0 TYPE memory-space {
2424 map: (
2425 (0x00000000000, memory_cache, 0x0, 0, 0x2000000000),
2426#ifdef CIOP0
2427 (0x0d500000000, ciop0, 0, 0, 0xb00000000),
2428 (0x0d300000000, bsc0, 0, 0, 0x200000000),
2429 (0x0c500000000, egress0, 0, 0, 0x200000000),
2430 (0x0c300000000, ingress0, 0, 0, 0x200000000),
2431 (0x0d000000000, rdma0, 0, 0, 0x300000000),
2432 (0x0ef00000000, echo0, 0, 0, 0x100000000),
2433#else
2434 (0x08000000000, memory_ciop, 0x0, 0, 0x7f00000000),
2435#endif
2436 (0x0ff00000000, memory0, 0x0, 0, 0x100000000))
2437#if defined(MOM)
2438 timing_model: mom0
2439 snoop_device: mom0
2440#elif !defined(NOLDST_SYNC) || defined(INDRA_MEM)
2441 timing_model: swvmem0
2442 snoop_device: swvmem0
2443#endif
2444}
2445
2446OBJECT memory0 TYPE ram {
2447 image: memory0_image
2448}
2449
2450OBJECT memory0_image TYPE image {
2451 size: 0x100000000
2452 queue: th00
2453}
2454
2455OBJECT memory_cache TYPE ram {
2456 image: memory_cache_image
2457}
2458
2459OBJECT memory_cache_image TYPE image {
2460 size: 0x2000000000
2461 queue: th00
2462}
2463
Full OpenSPARC architecture tarball including simulator, hypervisor, and OBP.