Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / lib / csr / src / N2_McuCsr.cc

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: N2_McuCsr.cc
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
// 
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
// 
// The above named program is distributed in the hope that it will be 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// General Public License for more details.
// 
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
// 
// ========== Copyright Header End ============================================
/************************************************************************
**  
**  Copyright (C) 2005, Sun Microsystems, Inc.
**
**  Sun considers its source code as an unpublished, proprietary
**  trade secret and it is available only under strict license provisions.
**  This copyright notice is placed here only to protect Sun in the event 
**  the source is deemed a published work. Disassembly, decompilation,
**  or other means of reducing the object code to human readable form
**  is prohibited by the license agreement under which this code is
**  provided to the user or company in possession of this copy.
**
*************************************************************************/
#include "N2_McuCsr.h"

using namespace std;

RegisterAttribute N2_McuCsr::attributeTable[] = {
    { 0x8400000000ULL,0x8400003000ULL,0x1000ULL,4,0xbULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffff0ULL,0x0ULL,0xfULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_CAS_ADDR_WIDTH","count 4 step 4096" },
    { 0x8400000008ULL,0x8400003008ULL,0x1000ULL,4,0xfULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffff0ULL,0x0ULL,0xfULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_RAS_ADDR_WIDTH","count 4 step 4096" },
    { 0x8400000010ULL,0x8400003010ULL,0x1000ULL,4,0x3ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffff8ULL,0x0ULL,0x7ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_CAS_LAT_REG","count 4 step 4096" },
    { 0x8400000018ULL,0x8400003018ULL,0x1000ULL,4,0xfffULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffff000ULL,0x0ULL,0xfffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_SCRUB_FREQ_REG","count 4 step 4096" },
    { 0x8400000020ULL,0x8400003020ULL,0x1000ULL,4,0x820ULL,0x0ULL,RegisterAttribute::RW,0xffffffffffffe000ULL,0x0ULL,0x1fffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_REFRESH_FREQ_REG","count 4 step 4096" },
    { 0x8400000028ULL,0x8400002028ULL,0x2000ULL,2,0x1ffffULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffe0000ULL,0x0ULL,0x1ffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_OPEN_BANK_MAX_REG","count 2 step 8192" },
    { 0x8400000038ULL,0x8400003038ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffffffffffe000ULL,0x0ULL,0x1fffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_REFRESH_COUNTER_REG","count 4 step 4096" },
    { 0x8400000040ULL,0x8400003040ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffeULL,0x0ULL,0x1ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_SCRUB_ENABLE_REG","count 4 step 4096" },
    { 0x8400000048ULL,0x8400003048ULL,0x1000ULL,4,0xffffULL,0x0ULL,RegisterAttribute::RW,0xffffffffffff0000ULL,0x0ULL,0xffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_PROG_TIME_CNTR_REG","count 4 step 4096" },
    { 0x8400000080ULL,0x8400003080ULL,0x1000ULL,4,0x2ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffff0ULL,0x0ULL,0xfULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_TRRD_REG","count 4 step 4096" },
    { 0x8400000088ULL,0x8400003088ULL,0x1000ULL,4,0xcULL,0x0ULL,RegisterAttribute::RW,0xffffffffffffffe0ULL,0x0ULL,0x1fULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_TRC_REG","count 4 step 4096" },
    { 0x8400000090ULL,0x8400003090ULL,0x1000ULL,4,0x3ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffff0ULL,0x0ULL,0xfULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_TRCD_REG","count 4 step 4096" },
    { 0x8400000098ULL,0x8400003098ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffff0ULL,0x0ULL,0xfULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_TWTR_REG","count 4 step 4096" },
    { 0x84000000a0ULL,0x84000030a0ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffff0ULL,0x0ULL,0xfULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_TRTW_REG","count 4 step 4096" },
    { 0x84000000a8ULL,0x84000030a8ULL,0x1000ULL,4,0x2ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffff8ULL,0x0ULL,0x7ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_TRTP_REG","count 4 step 4096" },
    { 0x84000000b0ULL,0x84000030b0ULL,0x1000ULL,4,0x9ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffff0ULL,0x0ULL,0xfULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_TRAS_REG","count 4 step 4096" },
    { 0x84000000b8ULL,0x84000030b8ULL,0x1000ULL,4,0x3ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffff0ULL,0x0ULL,0xfULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_TRP_REG","count 4 step 4096" },
    { 0x84000000c0ULL,0x84000030c0ULL,0x1000ULL,4,0x3ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffff0ULL,0x0ULL,0xfULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_TWR_REG","count 4 step 4096" },
    { 0x84000000c8ULL,0x84000030c8ULL,0x1000ULL,4,0x27ULL,0x0ULL,RegisterAttribute::RW,0xffffffffffffff80ULL,0x0ULL,0x7fULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_TRFC_REG","count 4 step 4096" },
    { 0x84000000d0ULL,0x84000030d0ULL,0x1000ULL,4,0x2ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffcULL,0x0ULL,0x3ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_TMRD_REG","count 4 step 4096" },
    { 0x84000000d8ULL,0x84000030d8ULL,0x1000ULL,4,0xaULL,0x0ULL,RegisterAttribute::RW,0xffffffffffffffe0ULL,0x0ULL,0x1fULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_FAWIN_REG","count 4 step 4096" },
    { 0x84000000e0ULL,0x84000030e0ULL,0x1000ULL,4,0x2ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffcULL,0x0ULL,0x3ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_TIWTR_REG","count 4 step 4096" },
    { 0x84000000e8ULL,0x84000030e8ULL,0x1000ULL,4,0x55ULL,0x0ULL,RegisterAttribute::RW,0xffffffffffffff00ULL,0x0ULL,0xffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_PRECHARGE_WAIT_REG","count 4 step 4096" },
    { 0x8400000108ULL,0x8400003108ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffeULL,0x0ULL,0x1ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_DIMM_STACK_REG","count 4 step 4096" },
    { 0x8400000110ULL,0x8400003110ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffffffffff8000ULL,0x0ULL,0x7fffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_EXT_WR_MODE2_REG","count 4 step 4096" },
    { 0x8400000118ULL,0x8400003118ULL,0x1000ULL,4,0x18ULL,0x0ULL,RegisterAttribute::RW,0xffffffffffff8000ULL,0x0ULL,0x7fffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_EXT_WR_MODE1_REG","count 4 step 4096" },
    { 0x8400000120ULL,0x8400003120ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffffffffff8000ULL,0x0ULL,0x7fffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_EXT_WR_MODE3_REG","count 4 step 4096" },
    { 0x8400000128ULL,0x8400003128ULL,0x1000ULL,4,0x1ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffeULL,0x0ULL,0x1ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_WAIR_CONTROL_REG","count 4 step 4096" },
    { 0x8400000130ULL,0x8400003130ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffeULL,0x0ULL,0x1ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_RANK1_PRESENT_REG","count 4 step 4096" },
    { 0x8400000138ULL,0x8400003138ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffeULL,0x0ULL,0x1ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_CHANNEL_DISABLED_REG","count 4 step 4096" },
    { 0x8400000140ULL,0x8400003140ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffeULL,0x0ULL,0x1ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_SEL_LO_ADDR_BITS_REG","count 4 step 4096" },
    { 0x8400000148ULL,0x8400003148ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffeULL,0x0ULL,0x1ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_SNGL_CHNL_MODE_REG","count 4 step 4096" },
    { 0x84000001a0ULL,0x84000031a0ULL,0x1000ULL,4,0x1ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffcULL,0x0ULL,0x3ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_DIMM_INIT_REG","count 4 step 4096" },
    { 0x84000001b0ULL,0x84000031b0ULL,0x1000ULL,4,0x1ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffff0ULL,0x0ULL,0xfULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_SW_DV_COUNT_REG","count 4 step 4096" },
    { 0x84000001b8ULL,0x84000031b8ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffeULL,0x0ULL,0x1ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_HW_DMUX_CLK_INV_REG","count 4 step 4096" },
    { 0x84000001c0ULL,0x84000031c0ULL,0x1000ULL,4,0xcULL,0x0ULL,RegisterAttribute::RW,0xffffffffffffffe0ULL,0x0ULL,0x1fULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_PAD_EN_CLK_INV_REG","count 4 step 4096" },
    { 0x8400000208ULL,0x8400003208ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RO,0xfffffffffffffffeULL,0x0ULL,0x1ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_MODE_WRITE_STATUS_REG","count 4 step 4096" },
    { 0x8400000210ULL,0x8400003210ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RO,0xfffffffffffffffeULL,0x0ULL,0x1ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_INIT_STATUS_REG","count 4 step 4096" },
    { 0x8400000218ULL,0x8400003218ULL,0x1000ULL,4,0x3ULL,0x0ULL,RegisterAttribute::RO,0xfffffffffffffff0ULL,0x0ULL,0xfULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_DIMM_PRESENT_REG","count 4 step 4096" },
    { 0x8400000218ULL,0x8400003218ULL,0x1000ULL,4,0x1ULL,0x0ULL,RegisterAttribute::RO,0xfffffffffffffff0ULL,0x0ULL,0xfULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_DIMM_PRESENT_REG","count 4 step 4096" },
    { 0x8400000220ULL,0x8400003220ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffeULL,0x0ULL,0x1ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_FAILOVER_STATUS_REG","count 4 step 4096" },
    { 0x8400000228ULL,0x8400003228ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffff800000000ULL,0x0ULL,0x7ffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DRAM_FAILOVER_MASK_REG","count 4 step 4096" },
    { 0x8400000238ULL,0x8400003238ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffeULL,0x0ULL,0x1ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_Power_Down_Mode_Register","count 4 step 4096" },
    { 0x8400000280ULL,0x8400003280ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0x3fffffffff0000ULL,0x3fffffffff0000ULL,0xffc000000000ffffULL,0xffc0000000000000ULL,0x0ULL,0x0ULL,"N2_DRAM_ERROR_STATUS_REG","count 4 step 4096" },
    { 0x8400000288ULL,0x8400003288ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffff000000000f,0xULL,0xfffffffff0ULL,0x0ULL,0x0ULL,0x0ULL,"N2_DRAM_ERROR_INJECT_REG","count 4 step 4096" },
    { 0x8400000290ULL,0x8400003290ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffffff3fff0000,0xULL,0xc000ffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_DRAM_ERROR_INJECT_REG","count 4 step 4096" },
    { 0x8400000298ULL,0x8400003298ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffffffffff0000ULL,0x0ULL,0xffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_DRAM_ERROR_COUNTER_REG","count 4 step 4096" },
    { 0x84000002a0ULL,0x84000032a0ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffff000000000ULL,0x0ULL,0xfffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_DRAM_ERROR_LOCATION_REG","count 4 step 4096" },
    { 0x8400000800ULL,0x8400003800ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffffffffffff00ULL,0x0ULL,0xffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_FBD_CHANNEL_STATE_REG","count 4 step 4096" },
    { 0x8400000808ULL,0x8400003808ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffff0ULL,0x0ULL,0xfULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_CHANNEL_RESET_REG","count 4 step 4096" },
    { 0x8400000810ULL,0x8400003810ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffcULL,0x0ULL,0x3ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_FAST_RESET_FLAG_REG","count 4 step 4096" },
    { 0x8400000818ULL,0x8400003818ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffff0ULL,0x0ULL,0xfULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_TS1_SB_NB_MAPPING_REG","count 4 step 4096" },
    { 0x8400000820ULL,0x8400003820ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffffffff000000ULL,0x0ULL,0xffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_TS1_TEST_PARAMETER_REG","count 4 step 4096" },
    { 0x8400000828ULL,0x8400003828ULL,0x1000ULL,4,0xffffULL,0x0ULL,RegisterAttribute::RW,0xffffffffffff0000ULL,0x0ULL,0xffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_TS3_FAILOVER_CONFIG_REG","count 4 step 4096" },
    { 0x8400000830ULL,0x8400003830ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RO,0xfffffffff0000000ULL,0x0ULL,0xfffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_ELECTRICAL_IDLE_DETECTED_REG","count 4 step 4096" },
    { 0x8400000838ULL,0x8400003838ULL,0x1000ULL,4,0x3fULL,0x0ULL,RegisterAttribute::RW,0xffffffffffffffc0ULL,0x0ULL,0x3fULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DISABLE_STATE_PERIOD_REG","count 4 step 4096" },
    { 0x8400000840ULL,0x8400003840ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RO,0xfffffffffffffffeULL,0x0ULL,0x1ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_DISABLE_STATE_PERIOD_DONE_REG","count 4 step 4096" },
    { 0x8400000848ULL,0x8400003848ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffff00000ULL,0x0ULL,0xfffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_CALIBRATE_STATE_PERIOD_REG","count 4 step 4096" },
    { 0x8400000850ULL,0x8400003850ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RO,0xfffffffffffffffeULL,0x0ULL,0x1ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_CALIBRATE_STATE_PERIOD_DONE_REG","count 4 step 4096" },
    { 0x8400000858ULL,0x8400003858ULL,0x1000ULL,4,0xffULL,0x0ULL,RegisterAttribute::RW,0xffffffffffff0000ULL,0x0ULL,0xffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_TRAINING_STATE_MIN_TIME_REG","count 4 step 4096" },
    { 0x8400000860ULL,0x8400003860ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffcULL,0x0ULL,0x3ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_TRAINING_STATE_DONE_REG","count 4 step 4096" },
    { 0x8400000868ULL,0x8400003868ULL,0x1000ULL,4,0xffULL,0x0ULL,RegisterAttribute::RW,0xffffffffffffff00ULL,0x0ULL,0xffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_TRAINING_STATE_TIMEOUT_REG","count 4 step 4096" },
    { 0x8400000870ULL,0x8400003870ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffcULL,0x0ULL,0x3ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_TESTING_STATE_DONE_REG","count 4 step 4096" },
    { 0x8400000878ULL,0x8400003878ULL,0x1000ULL,4,0xffULL,0x0ULL,RegisterAttribute::RW,0xffffffffffffff00ULL,0x0ULL,0xffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_TESTING_STATE_TIMEOUT_REG","count 4 step 4096" },
    { 0x8400000880ULL,0x8400003880ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffcULL,0x0ULL,0x3ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_POLLING_STATE_DONE_REG","count 4 step 4096" },
    { 0x8400000888ULL,0x8400003888ULL,0x1000ULL,4,0xffULL,0x0ULL,RegisterAttribute::RW,0xffffffffffffff00ULL,0x0ULL,0xffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_POLLING_STATE_TIMEOUT_REG","count 4 step 4096" },
    { 0x8400000890ULL,0x8400003890ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffcULL,0x0ULL,0x3ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_CONFIG_STATE_DONE_REG","count 4 step 4096" },
    { 0x8400000898ULL,0x8400003898ULL,0x1000ULL,4,0xffULL,0x0ULL,RegisterAttribute::RW,0xffffffffffffff00ULL,0x0ULL,0xffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_CONFIG_STATE_TIMEOUT_PERIOD_REG","count 4 step 4096" },
    { 0x84000008a0ULL,0x84000038a0ULL,0x1000ULL,4,0xffffULL,0x0ULL,RegisterAttribute::RW,0xffffffffffff0000ULL,0x0ULL,0xffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_RECALIBRATION_DURATION_REG","count 4 step 4096" },
    { 0x84000008a8ULL,0x84000038a8ULL,0x1000ULL,4,0x2aULL,0x0ULL,RegisterAttribute::RW,0xffffffffffffff80ULL,0x0ULL,0x7fULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_LOS_DURATION_REG","count 4 step 4096" },
    { 0x84000008b0ULL,0x84000038b0ULL,0x1000ULL,4,0x2aULL,0x0ULL,RegisterAttribute::RW,0xffffffffffffffc0ULL,0x0ULL,0x3fULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_SYNC_FRAME_FREQ_REG","count 4 step 4096" },
    { 0x84000008b8ULL,0x84000038b8ULL,0x1000ULL,4,0xffffULL,0x0ULL,RegisterAttribute::RW,0xffffffffffff0000ULL,0x0ULL,0xffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_CHANNEL_READ_LATENCY_REG","count 4 step 4096" },
    { 0x84000008c0ULL,0x84000038c0ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffc00ULL,0x0ULL,0x3ffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_CHANNEL_CAPABILITY_REG","count 4 step 4096" },
    { 0x84000008c8ULL,0x84000038c8ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffcULL,0x0ULL,0x3ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_LOOPBACK_MODE_CNTL_REG","count 4 step 4096" },
    { 0x84000008d0ULL,0x84000038d0ULL,0x1000ULL,4,0x1000018ULL,0x0ULL,RegisterAttribute::RW,0xffffffffc0000000ULL,0x0ULL,0x3fffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_SERDES_CONFIG_BUS_REG","count 4 step 4096" },
    { 0x84000008d8ULL,0x84000038d8ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffff000000000000ULL,0x0ULL,0xffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_SERDES_INVPAIR_REG","count 4 step 4096" },
    { 0x84000008e0ULL,0x84000038e0ULL,0x1000ULL,4,0xc003ULL,0x0ULL,RegisterAttribute::RW,0xffffffff00000000ULL,0x0ULL,0xffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_SERDES_TEST_CONFIG_BUS_REG","count 4 step 4096" },
    { 0x8400000900ULL,0x8400003900ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffffffffff0003ULL,0x0ULL,0xfffcULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_CONFIG_REG_ACCESS_ADDR_REG","count 4 step 4096" },
    { 0x8400000908ULL,0x8400003908ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xffffffff00000000ULL,0x0ULL,0xffffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_CONFIG_REG_ACCESS_DATA_REG","count 4 step 4096" },
    { 0x8400000c00ULL,0x8400003c00ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0x7fffffffc0000000ULL,0x0ULL,0x800000003fffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_MCU_SYNDROME_REG","count 4 step 4096" },
    { 0x8400000c08ULL,0x8400003c08ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffffffcULL,0x0ULL,0x3ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_INJ_ERR_SOURCE_REG","count 4 step 4096" },
    { 0x8400000c10ULL,0x8400003c10ULL,0x1000ULL,4,0x0ULL,0x0ULL,RegisterAttribute::RW,0xfffffffffffe0000ULL,0x0ULL,0x1ffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_MCU_FBR_COUNT_REG","count 4 step 4096" },
    { 0x8400000e80ULL,0x8400003e80ULL,0x1000ULL,4,0x23c01e478ULL,0x23c01e478ULL,RegisterAttribute::RW,0xff7fffd000000000ULL,0x200000000ULL,0x80002dffffffffULL,0x400000000ULL,0x0ULL,0x0ULL,"N2_MCU_SBFIBPORTCTL_SBFIBPGCTL_REG","" },
    { 0x8400000e88ULL,0x8400003e88ULL,0x1000ULL,4,0x2ccfd000003ffULL,0x2ccfd000003ffULL,RegisterAttribute::RW,0xff000000fffffc00ULL,0x0ULL,0xffffff000003ffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_SBFIBPATTBUF1_SBFIBTXMSK_REG","" },
    { 0x8400000e90ULL,0x8400003e90ULL,0x1000ULL,4,0x3ffULL,0x3ffULL,RegisterAttribute::RW,0xfffffffffffffc00ULL,0x0ULL,0x3ffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_SBFIBTXSHFT_REG","" },
    { 0x8400000ea0ULL,0x8400003ea0ULL,0x1000ULL,4,0xfd330200000000ULL,0xfd330200000000ULL,RegisterAttribute::RW,0xff000000fffffc00ULL,0x0ULL,0xffffff000003ffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_SBFIBPATTBUF2_SBFIBPATT2EN_REG","" },
    { 0x8400000eb0ULL,0x8400003eb0ULL,0x1000ULL,4,0x1900280400061a80ULL,0x1900280400061a80ULL,RegisterAttribute::RW,0x80000002ff000000ULL,0x0ULL,0x7ffffffd00ffffffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_SBFIBINIT_SBIBISTMISC_REG","" },
    { 0x8400000ec0ULL,0x8400003ec0ULL,0x1000ULL,4,0x3c01e478ULL,0x3c01e478ULL,RegisterAttribute::RW,0xffc0000000000000ULL,0xf0200000000ULL,0x3ff0fdffffffffULL,0x3ff0c400000000ULL,0x0ULL,0x0ULL,"N2_MCU_NBFIBPORTCTL_NBFIBPGCTL_REG","" },
    { 0x8400000ec8ULL,0x8400003ec8ULL,0x1000ULL,4,0x2ccfd00000000ULL,0x2ccfd00000000ULL,RegisterAttribute::RW,0xff000000ffffffffULL,0x0ULL,0xffffff00000000ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_NBFIBPATTBUF1_REG","" },
    { 0x8400000ed0ULL,0x8400003ed0ULL,0x1000ULL,4,0x3fff00000000ULL,0x3fff00000000ULL,RegisterAttribute::RW,0xffffc000ffffffffULL,0x0ULL,0x3fff00000000ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_NBFIBRXMSK_REG","" },
    { 0x8400000ed8ULL,0x8400003ed8ULL,0x1000ULL,4,0x3fff00000000ULL,0x3fff00000000ULL,RegisterAttribute::RW,0xffffc000ffffc000ULL,0x3fffULL,0x3fff00000000ULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_NBFIBRXSHFT_NBFIBRXLNERR_REG","" },
    { 0x8400000ee0ULL,0x8400003ee0ULL,0x1000ULL,4,0xfd330200000000ULL,0xfd330200000000ULL,RegisterAttribute::RW,0xff000000ffffc000ULL,0x0ULL,0xffffff00003fffULL,0x0ULL,0x0ULL,0x0ULL,"N2_MCU_NBFIBPATTBUF2_NBFIBPATT2EN_REG","" },
    { 0x8400000408ULL,0x8400003408ULL,0x1000ULL,4,0x1ULL,0x1ULL,RegisterAttribute::RW,0x0ULL,0xffffffffffffffffULL,0x0ULL,0x0ULL,0x0ULL,0x0ULL,"N2_DRAM_PERF_COUNT_REG","count 4 step 4096" }
};
const int N2_McuCsr::NUMBER_ENTRIES = sizeof(N2_McuCsr::attributeTable)/sizeof(N2_McuCsr::attributeTable[0]);

//======================================================================
//=============================================================================
N2_McuCsr::N2_McuCsr( ) :
  SS_BaseCsr("N2_McuCsr", attributeTable, NUMBER_ENTRIES)
{
}

//=============================================================================
//=============================================================================
void N2_McuCsr::regAddrSpace()
{ 
  const static std::string descr("N2_McuCsr address space");
  registerAddressSpace(attributeTable, NUMBER_ENTRIES, descr);
}