Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / lib / ras / xml / N2_DramErrorInjectMem.xml

<!-- interpreter=xml2reg args='-t' -->
<register_list>
<register name="DRAM_ERROR_INJECT_REG (DRAM_ERROR_INJECT_REG)">
    <class_name>N2_DramErrorInjectMem</class_name>
    <submodule>N2</submodule>
    <comment>
DRAM Error Injection Register. Each DRAM channel has an error injection register for use in injecting DRAM errors to test error functionality or error handling code. The DRAM error injection register only provides for the injection of bad ECC on data written to memory. To inject an ECC error on data read from memory, bad ECC must be set up via a memory write, and then the memory locations with the bad ECC accessed with a read. Errors can be injected either single-shot or continuously. Once the ENB bit set, either the first subsequent operation (for SSHOT=1), or all subsequent operations (for SSHOT=0) that cause a DRAM write will XOR the ECCMASK with the normally generated ECC when writing memory. When in single-shot mode, after the first injected error is generated, the SSHOT and ENB are automatically reset by the hardware to 0. ECC in dram controller is calculated on 32 bytes in one cycle. Therefore in SSHOT mode, error is injected into 2 bursts out of 4 for a cacheline of 64 bytes. TABLE 12-34 shows the format of the DRAM Error Injection Register. TABLE 12-34 Register64 DRAM Error Injection Register - DRAM_ERROR_INJECT_REG (0x84-0000-0290) (Count 4 Step 4096)
    </comment>
    <base_address>0x8400000290ULL</base_address>
    <count>4</count>
    <stride>4096</stride>
    <priv>yes</priv>
    <field name="ECCMASK">
        <start_offset>0</start_offset>
        <end_offset>15</end_offset>
        <initial_value>0</initial_value>
        <protection>RW</protection>
        <field_type>NORMAL</field_type>
        <comment>
ECC mask for error injection. The mask is XORed with the computed ECC.
        </comment>
        <format type="hex"/>
    </field>
    <field name="RSVD0">
        <start_offset>16</start_offset>
        <end_offset>29</end_offset>
        <initial_value>0</initial_value>
        <protection>RO</protection>
        <field_type>ZERO</field_type>
        <comment>
Reserved
        </comment>
    </field>
    <field name="SSHOT">
        <start_offset>30</start_offset>
        <end_offset>30</end_offset>
        <initial_value>0</initial_value>
        <protection>RW</protection>
        <field_type>NORMAL</field_type>
        <comment>
Controls type of error injection. 1, single shot, 0 continuous.
        </comment>
        <format type="hex"/>
    </field>
    <field name="ENB">
        <start_offset>31</start_offset>
        <end_offset>31</end_offset>
        <initial_value>0</initial_value>
        <protection>RW</protection>
        <field_type>NORMAL</field_type>
        <comment>
Enables error injection
        </comment>
        <format type="hex"/>
    </field>
    <field name="RSVD1">
        <start_offset>32</start_offset>
        <end_offset>63</end_offset>
        <initial_value>0</initial_value>
        <protection>RO</protection>
        <field_type>ZERO</field_type>
        <comment>
Reserved.
        </comment>
    </field>
</register>
</register_list>