Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / lib / ras / xml / N2_L2DiagTagMem.xml

<!-- interpreter=xml2reg args='-t' -->
<register_list>
<register name="L2_DIAG_TAG (L2_DIAG_TAG)">
    <class_name>N2_L2DiagTagMem</class_name>
    <submodule>N2</submodule>
    <comment>
Diagnostic access to the L2 tag array is done through 64 bit read/writes that access the tag along with the corresponding 6 bit ECC. Diag loads of the L2 tag do not check the ECC, and thus cannot generate an ECC error. L2 Diagnostic Tag - L2_DIAG_TAG (0xA4-0000-0000) (Count 49152, Step 64)
    </comment>
    <base_address>0xA400000000ULL</base_address>
    <count>0x10000</count>
    <stride>64</stride>
    <priv>yes</priv>
    <field name="ECC">
        <start_offset>0</start_offset>
        <end_offset>5</end_offset>
        <initial_value>0</initial_value>
        <protection>RW</protection>
        <field_type>NORMAL</field_type>
        <comment>
ECC value for tag.
        </comment>
        <format type="hex"/>
    </field>
    <field name="TAG">
        <start_offset>6</start_offset>
        <end_offset>27</end_offset>
        <initial_value>0</initial_value>
        <protection>RW</protection>
        <field_type>NORMAL</field_type>
        <comment>
Tag, corresponds to ADDR[39:18]
        </comment>
        <format type="hex"/>
    </field>
    <field name="RSVD0">
        <start_offset>28</start_offset>
        <end_offset>63</end_offset>
        <initial_value>0</initial_value>
        <protection>RO</protection>
        <field_type>ZERO</field_type>
        <comment>
Reserved
        </comment>
    </field>
</register>
</register_list>