Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / api / memsync / src / MemoryAccessEntry.h

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: MemoryAccessEntry.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
* 
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
* 
* The above named program is distributed in the hope that it will be 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
* 
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
* 
* ========== Copyright Header End ============================================
*/
#ifndef _MEMORYACCESSENTRY_H
#define _MEMORYACCESSENTRY_H
/************************************************************************
**  
**  Copyright (C) 2002, Sun Microsystems, Inc.
**
**  Sun considers its source code as an unpublished, proprietary
**  trade secret and it is available only under strict license provisions.
**  This copyright notice is placed here only to protect Sun in the event 
**  the source is deemed a published work. Disassembly, decompilation,
**  or other means of reducing the object code to human readable form
**  is prohibited by the license agreement under which this code is
**  provided to the user or company in possession of this copy."
**
*************************************************************************/
#include <iostream>
#include <list>
#include "LoadStoreCmd.h"


class MemoryAccessEntry  {

    static uint64_t maeid;
    
  public:

    /**
     * Default constructor
     */
    MemoryAccessEntry();

    MemoryAccessEntry(LoadStoreCmd& cmd);
   
    /**
     * Copy constructor
     * 
     * @param orig The MemoryAccessEntry object to copy.
     */
    MemoryAccessEntry( const MemoryAccessEntry &orig );

    /**
     * Destructor
     */
    virtual ~MemoryAccessEntry();
    
    /**
     * Equality operator
     * 
     * @param rhs The right hand side of the equality operator
     * @return Return true if this objec and rhs are equal, 
     * otherwise return false
     */
    bool operator==( const MemoryAccessEntry &rhs ) const;
    
    /**
     * Assignment operator
     * 
     * @param rhs The right hand side of the assignment operator.
     * @return The lvalue of the assignment.
     */
    const MemoryAccessEntry & operator=( const MemoryAccessEntry &rhs );
    
    /**
     * Return a string representation of this MemoryAccessEntry object. 
     */
    std::string toString() const;

    void setMaeId (uint64_t value) { MemoryAccessEntry::maeid = value; }

    void setLink(std::list<MemoryAccessEntry>::iterator link)  { link_ = link; vlink_ = true; }
    void setLinkValid (bool valid) { vlink_ = valid; }
    void setAddr(uint64_t addr)  { addr_ = addr; }
    void setData(uint64_t data)  { data_ = data; }
    void setThrdId(uint32_t tid)  { tid_ = tid; }
    void setCoreId(uint32_t cid)  { cid_ = cid; }
    void setInv(uint32_t inv)  { inv_ = inv; }
    void setCinv(uint32_t cinv) { cinv_ = cinv; }
    void setSrcBank (uint32_t srcBank) { srcBank_ = srcBank; }
    void setSet (uint32_t set) { set_ = set; }
    void setWay (uint32_t way) { way_ = way; }
    void setIseq (uint64_t iseq) { iseq_ = iseq; }
    void setDsrcMid (uint64_t dsrcMid) { dsrcMid_ = dsrcMid; }
    void setGlobal (uint64_t global) { global_ = global; }

    void setEntryType(enum MEM_CMD etype)  { etype_ = etype; }
    void setItype(enum INSTR_TYPE itype)  { itype_ = itype; }
    void setDsrc(enum DATA_SRC dsrc)  { dsrc_ = dsrc; }
    void setVbyte(uint8_t vbyte)  { vbyte_ = vbyte; }
    void setSizeV(uint8_t vbyte)  { vbyte_ = vbyte; }
    void setCacheL1(bool cacheL1) { cacheL1_ = cacheL1; }
    void setExecuted(bool executed)  { executed_ = executed; }
    void setValid(bool valid) { valid_ = valid; }
    void setAcked(bool acked) { acked_ = acked; }
    void setSwitchData (bool switchData) { switchData_ = switchData; }

    void setLink2(std::list<MemoryAccessEntry>::iterator link2) { link2_ = link2; vlink2_ = true; }
    void setLink2Valid (bool valid) { vlink2_ = valid; }
    void setPopped()  { popped_ = true; }

    std::list<MemoryAccessEntry>::iterator getLink() const { return link_; }
    uint64_t        getId() const { return id_; }
    uint64_t        getAddr() const { return addr_; }
    uint64_t        getData() const { return data_; }
    uint32_t        getThrdId() const { return tid_; }
    uint32_t        getCoreId() const { return cid_; }
    uint32_t        getInv() const { return inv_; }
    uint32_t        getCinv() const { return cinv_; }
    uint32_t        getSrcBank() const { return srcBank_; }
    uint32_t        getSet() const { return set_; }
    uint32_t        getWay() const { return way_; }
    uint64_t        getIseq() const { return iseq_; }
    uint64_t        getDsrcMid() const { return dsrcMid_; }
    uint64_t        getGlobal() const { return global_; }

    enum MEM_CMD    getEntryType() const { return etype_; }
    enum INSTR_TYPE getItype() const { return itype_; }
    enum DATA_SRC   getDsrc() const { return dsrc_; }
    uint8_t         getVbyte() const { return vbyte_; }
    uint8_t         getSizeV() const { return vbyte_; }
    bool            isCacheL1() const { return cacheL1_; }
    bool            isExecuted() const { return executed_; }
    bool            isValid() const { return valid_; }
    bool            isLinkValid() const { return vlink_; }
    bool            isAcked() const { return acked_; }
    bool            isSwitchData() const { return switchData_; }
    bool            isPopped() const { return popped_; }

    std::list<MemoryAccessEntry>::iterator getLink2() const { return link2_; }
    bool                isLink2Valid() const { return vlink2_; }

    uint32_t        addCinv (uint32_t cinv) { cinv_ |= cinv; return cinv_; }
#ifdef N3MODEL
    bool            isInvDone() { return (((inv_ ^ cinv_) || !acked_) ? false : true); }
#else
    bool            isInvDone() { return ((inv_ ^ cinv_) ? false : true); }
#endif
    /**
     * 
     */
    std::list<MemoryAccessEntry>::iterator getEntry();

    /**
     * 
     */
    void setEntry(std::list<MemoryAccessEntry>::iterator);

    void setCycle(uint64_t cyc) { cycle_ = cyc; }
    uint64_t getCycle() { return cycle_; }
    
    /**
     * handle error injection corner cases
     */
    void setMerged(bool merged) { merged_ = merged; }
    void setOrigData(uint64_t data) { origData_ = data; }
    void setOrigSizeV(uint8_t vbyte) { origVbyte_ = vbyte; }
    bool getMerged() const { return merged_; }
    uint64_t getOrigData() const { return origData_; }
    uint8_t getOrigSizeV() const { return origVbyte_; }

    /**
     * DMA_STORE
     */
    void setDmaStore(bool val) { dmaStore = val; }
    bool getDmaStore() { return dmaStore; }
    void setTsize(int _tsize) { tsize = _tsize; }
    int getTsize() { return tsize; }
    void setWriteBack() { writeBack = true; }
    bool isWriteBack() { return writeBack; }
    void setInvSet(bool val) { invSet = val; }
    bool getInvSet() { return invSet; }

  protected:

  private:
    std::list<MemoryAccessEntry>::iterator link_; // link to other entry
    std::list<MemoryAccessEntry>::iterator link2_; // link to other entry
    uint64_t        id_;      // sequential id, to indicates the order of reference
    uint64_t        addr_;    // physical address
    uint64_t        data_;     // 8 byte data
    uint64_t        iseq_;     // instruction sequence (for TSOchecker)
    uint64_t        dsrcMid_;  // MAE id of data source (for TSOchecker)
    uint64_t        global_;   // the last MAE id at which old data is invalidated/updated in all L1$s (for TSOchecker)
    uint32_t        tid_;      // thread id
    uint32_t        cid_;      // core id
    uint32_t        inv_;      // invalidation vector
    uint32_t        cinv_;     // core invalidated
    uint32_t        srcBank_; // source bank id, used in EVICT
    uint32_t        set_;        // cache set
    uint32_t        way_;        // cache way
    enum MEM_CMD    etype_;    // entry type
    enum INSTR_TYPE itype_;    // instruction type
    enum DATA_SRC   dsrc_;     // load data source    
    uint8_t         vbyte_;    // valid byte: bit 0 represents byte 0, and so on.
    bool            cacheL1_;  // perform L1 line fill?
    bool            executed_; // corresponding instruction executed
    bool            valid_;    // valid entry
    bool            vlink_;    // valid link
    bool            acked_;    // acked by its own used for store instruction, or in imab, storeL2 removed
    bool            vlink2_;   // 2nd link 
    bool            switchData_; // indicates if the memory data will be changed for an atomic instr
    bool            popped_;   // the entry is popped by LOAD_POP
    uint64_t        cycle_;   // RTL cycle, i.e., timestamp from testbench

    bool            merged_;   // true mean we need to re-do data merge
    uint64_t        origData_;     // original data before before SC merge
    uint8_t         origVbyte_;    // original valid byte vector
    bool            dmaStore;   // true - this is a dma_store related SC entry
    int             tsize;   // the size of a DMA_STORE operation
    bool            writeBack; // true - a st_commit has been written back to memory before it reaches head of MAB
    bool            invSet; // true - no more evict assoicated with this dma_store

  };
  
#endif /* _MEMORYACCESSENTRY_H */