Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / dev / rom / src / SS_Rom.cc

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: SS_Rom.cc
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
// 
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
// 
// The above named program is distributed in the hope that it will be 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// General Public License for more details.
// 
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
// 
// ========== Copyright Header End ============================================

#include <sys/socket.h>
#include <unistd.h>
#include "SS_Rom.h"

SS_Rom::SS_Rom( SS_AddressMap* map, SS_Paddr lo, SS_Paddr hi )/*{{{*/
 :
  base(lo),
  ram(&SS_Memory::memory)
{
  map->add(lo,hi,this,SS_AddressMap::REL,SS_Rom::access);
}
/*}}}*/
SS_Rom::~SS_Rom()/*{{{*/
{
}
/*}}}*/

void SS_Rom::access( void* obj, uint_t sid, SS_Access::Type type, SS_Paddr pa, uint_t size, uint64_t* data )/*{{{*/
{
  SS_Rom* self = (SS_Rom*)obj;

  pa += self->base;

  if (type == SS_Access::LOAD)
  {
#if defined(MEMORY_MSYNC)
    self->ram->msync_info(sid,pa);
#elif defined(MEMORY_EXTERNAL)
    self->ram->set_strand_id(sid);
#endif
    switch (size)
    {
      case  1: *data = self->ram->ld8u(pa); break;
      case  2: *data = self->ram->ld16u(pa); break;
      case  4: *data = self->ram->ld32u(pa); break;
      case  8: *data = self->ram->ld64(pa); break;
      case 16: self->ram->ld128(pa,data); break;
      case 64: self->ram->ld512(pa,data); break;
      default: assert(0);
    }
  }
  else
  {
    fprintf(stderr,"ROM: Non load access detected\n");
  }
}
/*}}}*/