Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / lib / cpu / src / SS_MsyncMemory.h

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: SS_MsyncMemory.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
* 
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
* 
* The above named program is distributed in the hope that it will be 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
* 
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
* 
* ========== Copyright Header End ============================================
*/
#ifndef __SS_MsyncMemory_h__
#define __SS_MsyncMemory_h__

#ifdef MEMORY_MSYNC
#include <string.h>
#include <sys/mman.h>
#include "MemoryTransaction.h"
#include "SS_FastMemory.h"

class SS_Strand;

class SS_MsyncMemory:public SS_FastMemory/*{{{*/
{
  public:
    SS_MsyncMemory();
    ~SS_MsyncMemory();

    // Supported Fetch Operation (instruction fetch) 
   
    virtual uint32_t fetch32 ( uint64_t addr );
    virtual void     fetch256( uint64_t addr, uint64_t data[4] );
    virtual void     fetch512( uint64_t addr, uint64_t data[8] );
    
    // Supported Store Operations. st8(), st16(), st32() and st64() are gueranteed to be atomic.
    // st128() and st512() are atomic per 64bit quantity.
   
    virtual void st8  ( uint64_t addr, uint8_t data );
    virtual void st16 ( uint64_t addr, uint16_t data );
    virtual void st32 ( uint64_t addr, uint32_t data );
    virtual void st64 ( uint64_t addr, uint64_t data );
    virtual void st128( uint64_t addr, uint64_t data[2] );
    virtual void st512( uint64_t addr, uint64_t data[8] );

    // Supported Load Operations. ld8[su]() to ld64() are quaranteed to be atomic. ld128() and
    // above are atomic at the 64 bit granularity.

    virtual uint8_t  ld8u ( uint64_t addr );
    virtual int8_t   ld8s ( uint64_t addr );
    virtual uint16_t ld16u( uint64_t addr );
    virtual int16_t  ld16s( uint64_t addr );
    virtual uint32_t ld32u( uint64_t addr );
    virtual int32_t  ld32s( uint64_t addr );
    virtual uint64_t ld64 ( uint64_t addr );
    virtual void     ld128( uint64_t addr, uint64_t data[2] );
    virtual void     ld256( uint64_t addr, uint64_t data[4] );
    virtual void     ld512( uint64_t addr, uint64_t data[8] );
    
    // st64partial() performs 8 byte partial store. The bytes to store are specified by mask. A 1 in bit N of 
    // mask denotes that byte (data >> (8*N)) & 0xff should be written to memory

    virtual void st64partial( uint64_t addr, uint64_t data, uint64_t mask );
    
    // ld128atomic() (aka load twin double, load quad atomic) atomically loads two
    // 64bit values from memory at addr into rd. rd[0] is the value at addr, rd[1]
    // is the value at addr + 8. Note ld128 does() not guarantee atomicity.
    
    virtual void ld128atomic( uint64_t addr, uint64_t data[2] );

    // ldstub() return a byte from memory at addr, and set the byte at addr
    // to 0xff. The ldstub() operation is atomic.
   
    virtual uint8_t ldstub( uint64_t addr );

    // swap() stores the 32bit value rd with the 32bit value at addr.
    // The old 32bit value at addr is returned.  The operation is atomic.
    
    virtual uint32_t swap( uint64_t addr, uint32_t rd );

    // casx() compares the 64bit value rs2 with the 64bit value at addr.
    // If the two values are equal, the value rd is stored in the
    // 64bit value at addr. In both cases the old 64bit value at addr is
    // returned, that is the value at addr before the storei happened.
    // The casx() operation is atomic.
    
    virtual uint64_t casx( uint64_t addr, uint64_t rd, uint64_t rs2 );

    // cas() is as casx, but for 32bit.

    virtual uint32_t cas( uint64_t addr, uint32_t rd, uint32_t rs2 );

    // prefetch() prefetches data from memory into the cache hierarchy.
    
    void prefetch( uint64_t addr, uint_t size ) {}

    // flush() writes dirty data in the cache back to memory.

    void flush( uint64_t addr, uint_t size ) {}   // process does not provide data.
   
    static SS_MsyncMemory memory;

    //----------------------------------------------------------------------------
    // Memory Sync additional interface
    //----------------------------------------------------------------------------

    enum Info
    {
      NONE = 0,
      LDD  = 1,	// Treat as 2xld32 
      STD  = 2, // Treat as 2xst32
      HTW  = 3  // Ignore ld128atomic
    };

 
    void msync_info( uint_t strand_id, SS_Vaddr va, Info info=NONE )
    {
      mem_xact.setStrand(strand_id);
      mem_xact.vaddr(va);
      msync_help = info;
    }

    void*  msync_object;
    void (*msync_pre_access)( void* obj, MemoryTransaction& );
    void (*msync_post_access)( void* obj, MemoryTransaction& );

  private:
    MemoryTransaction mem_xact;

    uint64_t msync_ld( uint64_t addr, uint_t size );
    void     msync_ld( uint64_t addr, uint_t size, uint64_t* data );
    void     msync_st( uint64_t addr, uint_t size, uint64_t data );
    void     msync_st( uint64_t addr, uint_t size, uint64_t* data );

    Info     msync_help;
};
/*}}}*/

#endif /* MEMORY_MSYNC */
#endif /* __SS_MsyncMemory_h__ */