[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / lib / ras / bin / SS_TrcExe.py

# ========== Copyright Header Begin ==========================================
# 
# OpenSPARC T2 Processor File: SS_TrcExe.py
# Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
# 
# The above named program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
# 
# The above named program is distributed in the hope that it will be 
# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
# General Public License for more details.
# 
# You should have received a copy of the GNU General Public
# License along with this work; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
# 
# ========== Copyright Header End ============================================

import sys


# The SS_TrcExe class generates envelope functions for tracing and RAS
# register file injection/detection.  These envelope functions capture
# which registers operands are used by an opcode and direct the
# operands to SS_Strand::*rf_rs[123] and SS_Strand::*rd_rd routines.
#
# The opcode classes use these envelope functions in the run_exe_tbl[]
# execution vector.

class SS_TrcExe:
  def __init__(self,regs):
    self.regs = regs

  def run_exe_h(self,file):
    file.write('extern "C" SS_Vaddr trc_exe_'+self.regs+'( SS_Vaddr pc, SS_Vaddr npc, SS_Strand* s, SS_Instr* i);\n')
    
  def run_exe_c(self,file):
    file.write('extern "C" SS_Vaddr trc_exe_'+self.regs+'( SS_Vaddr pc, SS_Vaddr npc, SS_Strand* s, SS_Instr* i)\n')
    file.write('{\n')
    file.write('  s->sim_state.trap_taken(0);\n')
    self.gen_ras_src_reg_c(file,1)
    self.gen_ras_src_reg_c(file,2)
    self.gen_ras_src_reg_c(file,3)
    file.write('  SS_Execute exe = s->run_exe_table_ref[i->exe_tbl_idx];\n')
    file.write('  pc = (*exe)(pc, npc, s, i);\n')
    self.gen_ras_dest_reg_c(file)
    file.write('  return pc;\n')
    file.write('}\n')

  def gen_ras_reg_nr(self,file,reg,reg_nr):
    reg = reg.lower()
    if reg == 'r' or reg == 'p':
      file.write('  int reg_nr%d = SS_Strand::reg_off2idx(i->rs%d);\n' \
                 % (reg_nr, reg_nr))
    elif reg == 'f' or reg == 'd':
      file.write('  int reg_nr%d = SS_Strand::freg_off2idx(i->rs%d);\n' \
                 % (reg_nr, reg_nr))
    elif reg == '0':
      pass
    else:
      raise RuntimeError, 'Bad regsiter type: '+reg

  def gen_ras_src_reg_c(self,file,reg_nr):
    if reg_nr == 1 or reg_nr == 2:
      reg = self.regs[reg_nr]
      self.gen_ras_reg_nr(file,reg,reg_nr)
    elif reg_nr == 3:
      if self.regs == 'ffff' or self.regs == 'dddd':
        reg = self.regs[3]
        self.gen_ras_reg_nr(file,reg,reg_nr)
      elif self.regs[0].isupper():
        reg = self.regs[0].lower()
        if reg == 'r' or reg == 'p':
          file.write('  int reg_nr3 = SS_Strand::reg_off2idx(i->rd); /* rd as source */\n')
        elif reg == 'f' or reg == 'd' or reg == 'b':
          file.write('  int reg_nr3 = SS_Strand::freg_off2idx(i->rd); /* rd as source */\n')
        elif reg == '0':
          pass
        else:
          raise RuntimeError, 'Bad regsiter type: '+reg
      else:
        reg = '0'
    else:
      raise RuntimeError, 'Bad regsiter number: '+reg_nr

    if reg == 'r' or reg == 'p':
      file.write('  if (s->ras_rs%d)\n' % (reg_nr))
      file.write('  {\n')
      file.write('    SS_Vaddr trap_pc = (*s->ras_rs%d)(pc, npc, s, i, reg_nr%d);\n' % (reg_nr, reg_nr))
      file.write('    if (s->sim_state.trap_taken())\n')
      file.write('      return trap_pc;\n')
      file.write('  }\n')
      if reg == 'p':
        file.write('  if (s->ras_rs%d)\n' % (reg_nr))
        file.write('  {\n')
        file.write('    SS_Vaddr trap_pc = (*s->ras_rs%d)(pc, npc, s, i, reg_nr%d+1);\n' % (reg_nr, reg_nr))
        file.write('    if (s->sim_state.trap_taken())\n')
        file.write('      return trap_pc;\n')
        file.write('  }\n')

    elif reg == 'f':
      file.write('  if (s->ras_frs%d)\n' % (reg_nr))
      file.write('  {\n')
      file.write('    SS_Vaddr trap_pc = (*s->ras_frs%d)(pc, npc, s, i, reg_nr%d);\n' % (reg_nr, reg_nr))
      file.write('    if (s->sim_state.trap_taken())\n')
      file.write('      return trap_pc;\n')
      file.write('  }\n')
    elif reg == 'd':
      file.write('  if (s->ras_drs%d)\n' % (reg_nr))
      file.write('  {\n')
      file.write('    SS_Vaddr trap_pc = (*s->ras_drs%d)(pc, npc, s, i, reg_nr%d);\n' % (reg_nr, reg_nr))
      file.write('    if (s->sim_state.trap_taken())\n')
      file.write('      return trap_pc;\n')
      file.write('  }\n')
    elif reg == 'b':
      file.write('  if (s->ras_drs%d)\n' % (reg_nr))
      file.write('  {\n')
      file.write('    for (int ndx = 0; ndx < 8; ++ndx)\n')
      file.write('    {\n')
      file.write('      SS_Vaddr trap_pc = (*s->ras_drs%d)(pc, npc, s, i, reg_nr%d + 2*ndx);\n' % (reg_nr, reg_nr))
      file.write('      if (s->sim_state.trap_taken())\n')
      file.write('        return trap_pc;\n')
      file.write('    }\n')
      file.write('  }\n')
    elif reg == '0':
      pass
    else:
      raise RuntimeError, 'Bad register type: '+reg+'\n'

  def gen_ras_dest_reg_c(self,file):
    if self.regs[0].isupper():
      reg = '0'
    else:
      reg = self.regs[0]

    if reg == 'r' or reg == 'p':
      file.write('  if (s->ras_rd && !s->sim_state.trap_taken())\n')
      file.write('  {\n')
      file.write('    SS_Vaddr trap_pc = (*s->ras_rd)(pc, npc, s, i, SS_Strand::reg_off2idx(i->rd));\n')
      file.write('    if (s->sim_state.trap_taken())\n')
      file.write('      return trap_pc;\n')
      file.write('  }\n')
      if reg == 'p':
        file.write('  if (s->ras_rd && !s->sim_state.trap_taken())\n')
        file.write('  {\n')
        file.write('    SS_Vaddr trap_pc = (*s->ras_rd)(pc, npc, s, i, SS_Strand::reg_off2idx(i->rd)+1);\n')
        file.write('    if (s->sim_state.trap_taken())\n')
        file.write('      return trap_pc;\n')
        file.write('  }\n')
    elif reg == 'f':
      file.write('  if (s->ras_frd && !s->sim_state.trap_taken())\n')
      file.write('  {\n')
      file.write('    SS_Vaddr trap_pc = (*s->ras_frd)(pc, npc, s, i, SS_Strand::freg_off2idx(i->rd));\n')
      file.write('    if (s->sim_state.trap_taken())\n')
      file.write('      return trap_pc;\n')
      file.write('  }\n')
    elif reg == 'd':
      file.write('  if (s->ras_drd && !s->sim_state.trap_taken())\n')
      file.write('  {\n')
      file.write('    SS_Vaddr trap_pc = (*s->ras_drd)(pc, npc, s, i, SS_Strand::freg_off2idx(i->rd));\n')
      file.write('    if (s->sim_state.trap_taken())\n')
      file.write('      return trap_pc;\n')
      file.write('  }\n')
    elif reg == 'b':
      file.write('  if (s->ras_drd && !s->sim_state.trap_taken())\n')
      file.write('  {\n')
      file.write('    int reg_nr = SS_Strand::freg_off2idx(i->rd);\n')
      file.write('    for (int ndx = 0; ndx < 8; ++ndx)\n')
      file.write('    {\n')
      file.write('      SS_Vaddr trap_pc = (*s->ras_drd)(pc, npc, s, i, reg_nr + 2*ndx);\n')
      file.write('      if (s->sim_state.trap_taken())\n')
      file.write('        return trap_pc;\n')
      file.write('    }\n')
      file.write('  }\n')
    elif reg == '0':
      pass
    else:
      raise RuntimeError, 'Bad register type: '+reg+'\n'


ras_reg_fmts = [
  'rrr',
  'rr0',
  'prr',
  'pr0',
  'r0r',
  'rf0',
  'rd0',
  '00r',
  '0r0',
  'r00',
  'r0f',  
  'r0d',
  '0rr',
  'Rrr',
  'Rr0',
  'Prr',
  'Pr0',
  'f0f',
  'd0d',
  'frf',
  'drd',
  'd0f',
  'df0',
  'f0d',
  '0ff',
  '0dd',
  'fff',
  'ddd',
  'dfd',
  'dff',
  'fdd',
  'rdd',
  'frr',
  'Frr',
  'drr',
  'Drr',
  'd00',
  'f0r',
  'd0r',
  'f00',
  'ff0',
  'dd0',
  'fr0',
  'Fr0',
  'dr0',
  'Dr0',
  'Ddd',
  'br0',
  'brr',
  'Br0',
  'Brr',
  'ffff',
  'dddd'
];

if sys.argv[1] == 'h':
  h_base_name = sys.argv[2].split('/')[-1]
  h_file=open(sys.argv[2]+'.h','w')
  h_file.write('#ifndef __'+h_base_name+'_h__\n')
  h_file.write('#define __'+h_base_name+'_h__\n')
  h_file.write('\n')
  h_file.write('#include "SS_Types.h"\n')
  h_file.write('\n')
  for fmt in ras_reg_fmts:
    SS_TrcExe(fmt).run_exe_h(h_file)
  h_file.write('#endif\n')
  h_file.close()
elif sys.argv[1] == 'cc':
  cc_base_name = sys.argv[2].split('/')[-1]
  cc_file=open(sys.argv[2]+'.cc','w')
  cc_file.write('#include "SS_Strand.h"\n')
  cc_file.write('#include "SS_Instr.h"\n')  
  cc_file.write('#include "SS_TrcExe.h"\n')
  cc_file.write("\n")
  for fmt in ras_reg_fmts:
    SS_TrcExe(fmt).run_exe_c(cc_file)
  cc_file.close()
else:
  sys.stderr.write('bad file specifier: '+sys.argv[1]+'\n')
Commit	Line	Data
920dae64 AT	1	# ========== Copyright Header Begin ==========================================
	2	#
	3	# OpenSPARC T2 Processor File: SS_TrcExe.py
	4	# Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	5	# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
	6	#
	7	# The above named program is free software; you can redistribute it and/or
	8	# modify it under the terms of the GNU General Public
	9	# License version 2 as published by the Free Software Foundation.
	10	#
	11	# The above named program is distributed in the hope that it will be
	12	# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	# General Public License for more details.
	15	#
	16	# You should have received a copy of the GNU General Public
	17	# License along with this work; if not, write to the Free Software
	18	# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
	19	#
	20	# ========== Copyright Header End ============================================
	21
	22	import sys
	23
	24
	25	# The SS_TrcExe class generates envelope functions for tracing and RAS
	26	# register file injection/detection. These envelope functions capture
	27	# which registers operands are used by an opcode and direct the
	28	# operands to SS_Strand::rf_rs[123] and SS_Strand::rd_rd routines.
	29	#
	30	# The opcode classes use these envelope functions in the run_exe_tbl[]
	31	# execution vector.
	32
	33	class SS_TrcExe:
	34	def __init__(self,regs):
	35	self.regs = regs
	36
	37	def run_exe_h(self,file):
	38	file.write('extern "C" SS_Vaddr trc_exe_'+self.regs+'( SS_Vaddr pc, SS_Vaddr npc, SS_Strand* s, SS_Instr* i);\n')
	39
	40	def run_exe_c(self,file):
	41	file.write('extern "C" SS_Vaddr trc_exe_'+self.regs+'( SS_Vaddr pc, SS_Vaddr npc, SS_Strand* s, SS_Instr* i)\n')
	42	file.write('{\n')
	43	file.write(' s->sim_state.trap_taken(0);\n')
	44	self.gen_ras_src_reg_c(file,1)
	45	self.gen_ras_src_reg_c(file,2)
	46	self.gen_ras_src_reg_c(file,3)
	47	file.write(' SS_Execute exe = s->run_exe_table_ref[i->exe_tbl_idx];\n')
	48	file.write(' pc = (*exe)(pc, npc, s, i);\n')
	49	self.gen_ras_dest_reg_c(file)
	50	file.write(' return pc;\n')
	51	file.write('}\n')
	52
	53	def gen_ras_reg_nr(self,file,reg,reg_nr):
	54	reg = reg.lower()
	55	if reg == 'r' or reg == 'p':
	56	file.write(' int reg_nr%d = SS_Strand::reg_off2idx(i->rs%d);\n' \
	57	% (reg_nr, reg_nr))
	58	elif reg == 'f' or reg == 'd':
	59	file.write(' int reg_nr%d = SS_Strand::freg_off2idx(i->rs%d);\n' \
	60	% (reg_nr, reg_nr))
	61	elif reg == '0':
	62	pass
	63	else:
	64	raise RuntimeError, 'Bad regsiter type: '+reg
65
66	def gen_ras_src_reg_c(self,file,reg_nr):
67	if reg_nr == 1 or reg_nr == 2:
68	reg = self.regs[reg_nr]
69	self.gen_ras_reg_nr(file,reg,reg_nr)
70	elif reg_nr == 3:
71	if self.regs == 'ffff' or self.regs == 'dddd':
72	reg = self.regs[3]
73	self.gen_ras_reg_nr(file,reg,reg_nr)
74	elif self.regs[0].isupper():
75	reg = self.regs[0].lower()
76	if reg == 'r' or reg == 'p':
77	file.write(' int reg_nr3 = SS_Strand::reg_off2idx(i->rd); /* rd as source */\n')
78	elif reg == 'f' or reg == 'd' or reg == 'b':
79	file.write(' int reg_nr3 = SS_Strand::freg_off2idx(i->rd); /* rd as source */\n')
80	elif reg == '0':
81	pass
82	else:
83	raise RuntimeError, 'Bad regsiter type: '+reg
84	else:
85	reg = '0'
86	else:
87	raise RuntimeError, 'Bad regsiter number: '+reg_nr
88
89	if reg == 'r' or reg == 'p':
90	file.write(' if (s->ras_rs%d)\n' % (reg_nr))
91	file.write(' {\n')
92	file.write(' SS_Vaddr trap_pc = (*s->ras_rs%d)(pc, npc, s, i, reg_nr%d);\n' % (reg_nr, reg_nr))
93	file.write(' if (s->sim_state.trap_taken())\n')
94	file.write(' return trap_pc;\n')
95	file.write(' }\n')
96	if reg == 'p':
97	file.write(' if (s->ras_rs%d)\n' % (reg_nr))
98	file.write(' {\n')
99	file.write(' SS_Vaddr trap_pc = (*s->ras_rs%d)(pc, npc, s, i, reg_nr%d+1);\n' % (reg_nr, reg_nr))
100	file.write(' if (s->sim_state.trap_taken())\n')
101	file.write(' return trap_pc;\n')
102	file.write(' }\n')
103
104	elif reg == 'f':
105	file.write(' if (s->ras_frs%d)\n' % (reg_nr))
106	file.write(' {\n')
107	file.write(' SS_Vaddr trap_pc = (*s->ras_frs%d)(pc, npc, s, i, reg_nr%d);\n' % (reg_nr, reg_nr))
108	file.write(' if (s->sim_state.trap_taken())\n')
109	file.write(' return trap_pc;\n')
110	file.write(' }\n')
111	elif reg == 'd':
112	file.write(' if (s->ras_drs%d)\n' % (reg_nr))
113	file.write(' {\n')
114	file.write(' SS_Vaddr trap_pc = (*s->ras_drs%d)(pc, npc, s, i, reg_nr%d);\n' % (reg_nr, reg_nr))
115	file.write(' if (s->sim_state.trap_taken())\n')
116	file.write(' return trap_pc;\n')
117	file.write(' }\n')
118	elif reg == 'b':
119	file.write(' if (s->ras_drs%d)\n' % (reg_nr))
120	file.write(' {\n')
121	file.write(' for (int ndx = 0; ndx < 8; ++ndx)\n')
122	file.write(' {\n')
123	file.write(' SS_Vaddr trap_pc = (s->ras_drs%d)(pc, npc, s, i, reg_nr%d + 2ndx);\n' % (reg_nr, reg_nr))
124	file.write(' if (s->sim_state.trap_taken())\n')
125	file.write(' return trap_pc;\n')
126	file.write(' }\n')
127	file.write(' }\n')
128	elif reg == '0':
129	pass
130	else:
131	raise RuntimeError, 'Bad register type: '+reg+'\n'
132
133	def gen_ras_dest_reg_c(self,file):
134	if self.regs[0].isupper():
135	reg = '0'
136	else:
137	reg = self.regs[0]
138
139	if reg == 'r' or reg == 'p':
140	file.write(' if (s->ras_rd && !s->sim_state.trap_taken())\n')
141	file.write(' {\n')
142	file.write(' SS_Vaddr trap_pc = (*s->ras_rd)(pc, npc, s, i, SS_Strand::reg_off2idx(i->rd));\n')
143	file.write(' if (s->sim_state.trap_taken())\n')
144	file.write(' return trap_pc;\n')
145	file.write(' }\n')
146	if reg == 'p':
147	file.write(' if (s->ras_rd && !s->sim_state.trap_taken())\n')
148	file.write(' {\n')
149	file.write(' SS_Vaddr trap_pc = (*s->ras_rd)(pc, npc, s, i, SS_Strand::reg_off2idx(i->rd)+1);\n')
150	file.write(' if (s->sim_state.trap_taken())\n')
151	file.write(' return trap_pc;\n')
152	file.write(' }\n')
153	elif reg == 'f':
154	file.write(' if (s->ras_frd && !s->sim_state.trap_taken())\n')
155	file.write(' {\n')
156	file.write(' SS_Vaddr trap_pc = (*s->ras_frd)(pc, npc, s, i, SS_Strand::freg_off2idx(i->rd));\n')
157	file.write(' if (s->sim_state.trap_taken())\n')
158	file.write(' return trap_pc;\n')
159	file.write(' }\n')
160	elif reg == 'd':
161	file.write(' if (s->ras_drd && !s->sim_state.trap_taken())\n')
162	file.write(' {\n')
163	file.write(' SS_Vaddr trap_pc = (*s->ras_drd)(pc, npc, s, i, SS_Strand::freg_off2idx(i->rd));\n')
164	file.write(' if (s->sim_state.trap_taken())\n')
165	file.write(' return trap_pc;\n')
166	file.write(' }\n')
167	elif reg == 'b':
168	file.write(' if (s->ras_drd && !s->sim_state.trap_taken())\n')
169	file.write(' {\n')
170	file.write(' int reg_nr = SS_Strand::freg_off2idx(i->rd);\n')
171	file.write(' for (int ndx = 0; ndx < 8; ++ndx)\n')
172	file.write(' {\n')
173	file.write(' SS_Vaddr trap_pc = (s->ras_drd)(pc, npc, s, i, reg_nr + 2ndx);\n')
174	file.write(' if (s->sim_state.trap_taken())\n')
175	file.write(' return trap_pc;\n')
176	file.write(' }\n')
177	file.write(' }\n')
178	elif reg == '0':
179	pass
180	else:
181	raise RuntimeError, 'Bad register type: '+reg+'\n'
182
183
184	ras_reg_fmts = [
185	'rrr',
186	'rr0',
187	'prr',
188	'pr0',
189	'r0r',
190	'rf0',
191	'rd0',
192	'00r',
193	'0r0',
194	'r00',
195	'r0f',
196	'r0d',
197	'0rr',
198	'Rrr',
199	'Rr0',
200	'Prr',
201	'Pr0',
202	'f0f',
203	'd0d',
204	'frf',
205	'drd',
206	'd0f',
207	'df0',
208	'f0d',
209	'0ff',
210	'0dd',
211	'fff',
212	'ddd',
213	'dfd',
214	'dff',
215	'fdd',
216	'rdd',
217	'frr',
218	'Frr',
219	'drr',
220	'Drr',
221	'd00',
222	'f0r',
223	'd0r',
224	'f00',
225	'ff0',
226	'dd0',
227	'fr0',
228	'Fr0',
229	'dr0',
230	'Dr0',
231	'Ddd',
232	'br0',
233	'brr',
234	'Br0',
235	'Brr',
236	'ffff',
237	'dddd'
238	];
239
240	if sys.argv[1] == 'h':
241	h_base_name = sys.argv[2].split('/')[-1]
242	h_file=open(sys.argv[2]+'.h','w')
243	h_file.write('#ifndef __'+h_base_name+'_h__\n')
244	h_file.write('#define __'+h_base_name+'_h__\n')
245	h_file.write('\n')
246	h_file.write('#include "SS_Types.h"\n')
247	h_file.write('\n')
248	for fmt in ras_reg_fmts:
249	SS_TrcExe(fmt).run_exe_h(h_file)
250	h_file.write('#endif\n')
251	h_file.close()
252	elif sys.argv[1] == 'cc':
253	cc_base_name = sys.argv[2].split('/')[-1]
254	cc_file=open(sys.argv[2]+'.cc','w')
255	cc_file.write('#include "SS_Strand.h"\n')
256	cc_file.write('#include "SS_Instr.h"\n')
257	cc_file.write('#include "SS_TrcExe.h"\n')
258	cc_file.write("\n")
259	for fmt in ras_reg_fmts:
260	SS_TrcExe(fmt).run_exe_c(cc_file)
261	cc_file.close()
262	else:
263	sys.stderr.write('bad file specifier: '+sys.argv[1]+'\n')
264