Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / devices / n2_piu / piu_dr.cc
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: piu_dr.cc
4// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
5// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6//
7// The above named program is free software; you can redistribute it and/or
8// modify it under the terms of the GNU General Public
9// License version 2 as published by the Free Software Foundation.
10//
11// The above named program is distributed in the hope that it will be
12// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14// General Public License for more details.
15//
16// You should have received a copy of the GNU General Public
17// License along with this work; if not, write to the Free Software
18// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19//
20// ========== Copyright Header End ============================================
21#include <sam_piu.h>
22
23extern pcie_csr_desc_t pcie_csrs[];
24
25bool samPiu::dump(FILE * fp){
26
27 const char * m1 = "-----PIU CSRs----\n";
28 fwrite(m1,strlen(m1),1,fp);
29 // dump the csrs
30 dump_piu_csrs(fp);
31
32 const char * m2 = "-----PIU pending interrupts----\n";
33 fwrite(m2,strlen(m2),1,fp);
34 // dump the intr lists
35 dump_intr(fp);
36
37 const char * m3 = "-----PIU nacked interrupt----\n";
38 fwrite(m3,strlen(m3),1,fp);
39 // dump the IRQ and time
40 dump_irq(fp);
41 return true;
42}
43
44void samPiu::dump_irq(FILE * fp){
45 fprintf(fp,"next_event_fire_time %llx\n",event_fire_time);
46 if(irql.empty()){
47 fprintf(fp,"no_nacked_irq\n");
48 return;
49 }
50
51 fprintf(fp,"Num Irq's %d\n",irql.size());
52 list <VCPU_InterruptRequest* >::iterator it;
53 for(it = irql.begin(); it != irql.end(); it++){
54 fprintf(fp,"itid %d\n",(*it)->itid);
55 fprintf(fp,"isid %d\n",(*it)->isid);
56 fprintf(fp,"data0 %llx\n",(*it)->data[0]);
57 fprintf(fp,"data1 %llx\n",(*it)->data[1]);
58 }
59 fflush(fp);
60 return;
61}
62
63
64void samPiu::dump_piu_csrs(FILE * fp){
65 const int bufsize = 64 * 1024;
66 char buf[bufsize];
67 uint64_t *csrs = (uint64_t *)&piuModel.csrs;
68
69 for(int i = 0; i < NUM_PCIE_CSRS; i++){
70 sprintf(buf,"%-80s0x%-16llx ",pcie_csrs[i].name,pcie_csrs[i].offset);
71 int index = pcie_csrs[i].regx;
72 for(int j = 0; j < pcie_csrs[i].nwords; j++){
73 char val[128];
74 sprintf(val,"0x%x 0x%016llx,",j,csrs[index+j]);
75 strcat(buf,val);
76 }
77 fwrite(buf,strlen(buf),1,fp);
78 fwrite("\n",strlen("\n"),1,fp);
79 }
80 fflush(fp);
81 return;
82}
83
84void samPiu::dump_intr(FILE * fp){
85 const int bufsize = 64 * 1024;
86 char buf[bufsize];
87 char tbuf[bufsize];
88
89 for(int i = 0; i < 4; i++){
90 sprintf(buf,"Int%c ",'A' + i);
91 list<int>::iterator listIt;
92 tbuf[0] = 0;
93 for(listIt = intLine[i].begin(); listIt != intLine[i].end(); listIt++){
94 sprintf(tbuf,"0x%x ",*listIt);
95 strcat(buf,tbuf);
96 }
97 fwrite(buf,strlen(buf),1,fp);
98 fwrite("\n",strlen("\n"),1,fp);
99 }
100
101 buf[0] = 0;
102 for(int i = 0; i < 64; i++){
103 sprintf(tbuf,"%d,",pendingIntr[i]);
104 strcat(buf,tbuf);
105 }
106
107 fwrite(buf,strlen(buf),1,fp);
108 fwrite("\n",strlen("\n"),1,fp);
109
110 fflush(fp);
111 return;
112}
113
114bool samPiu::restore(FILE *fp){
115 const int bufsize = 64 * 1024;
116 char buf[bufsize];
117
118 fgets(buf,bufsize,fp);
119 restore_piu_csrs(fp);
120
121 fgets(buf,bufsize,fp);
122 restore_intr(fp);
123
124 fgets(buf,bufsize,fp);
125 restore_irq(fp);
126 return true;
127}
128
129void samPiu::restore_irq(FILE * fp){
130 char buf[1024];
131
132 fgets(buf,1024,fp);
133 sscanf(buf,"next_event_fire_time %llx\n",&event_fire_time);
134 mmi_register_event(event_fire_time,samPiu_1ms_callback,(void*)this,0);
135
136 fgets(buf,1024,fp);
137 if(!strcmp("no_nacked_irq\n",buf))
138 return;
139
140 int size;
141 sscanf(buf,"Num Irq's %d\n",&size);
142
143 for(int i = 0 ; i < size; i++){
144 VCPU_InterruptRequest *ir = new VCPU_InterruptRequest;
145 fgets(buf,1024,fp);
146 sscanf(buf,"itid %d\n",&ir->itid);
147 fgets(buf,1024,fp);
148 sscanf(buf,"isid %d\n",&ir->isid);
149 fgets(buf,1024,fp);
150 sscanf(buf,"data0 %llx\n",&ir->data[0]);
151 fgets(buf,1024,fp);
152 sscanf(buf,"data1 %llx\n",&ir->data[1]);
153 irql.push_back(ir);
154 }
155
156 return;
157}
158
159void samPiu::restore_piu_csrs(FILE * fp){
160 const int bufsize = 64 * 1024;
161 char buf[bufsize];
162 uint64_t *csrs = (uint64_t *)&piuModel.csrs;
163
164 for(int i = 0; i < NUM_PCIE_CSRS; i++){
165 fgets(buf,bufsize,fp);
166 strtok(buf," "); // csr name, ignore
167 const char * csr_offset = strtok(0," "); // csr offset
168 uint64_t offset = strtoull(csr_offset,0,0);
169
170 int regx;
171 pcie_csr_t index = piu_offset2reg(offset, &regx);
172
173 for(int j = 0; j < pcie_csrs[index].nwords; j++){
174 strtok(0," "); // index, ignore
175 const char * csr_val = strtok(0,",");
176 uint64_t val = strtoull(csr_val,0,0);
177 csrs[regx] = val;
178 regx++;
179 }
180 }
181
182 // set the bus/device/function etc
183 int i;
184 piu_offset2reg( PIU_CSR_BASE + PIU_DMU_PCIE_CONFREG_OFFSET , &i);
185
186 secondary_bus_no = (csrs[i]) >> 24 & 0xff;
187 primary_bus_no = (csrs[i]) >> 8 & 0xff;
188 device = (csrs[i]) >> 3 & 0x1f;
189 function = (csrs[i]) & 0x7;
190
191 return;
192}
193
194void samPiu::restore_intr(FILE * fp){
195 const int bufsize = 64 * 1024;
196 char buf[bufsize];
197
198 for(int i = 0; i < 4; i++){
199 fgets(buf,bufsize,fp);
200 strtok(buf," "); // intr line number, ignore
201 const char * bus_val;
202 while( bus_val = strtok(0," ") ){
203 if(bus_val[0] == '\n')
204 break;
205 uint64_t val = strtoull(bus_val,0,0);
206 setIntx(val,i,true);
207 }
208 }
209
210 fgets(buf,bufsize,fp);
211 const char * intr_val = strtok(buf,",");
212 pendingIntr[0] = atoi(intr_val);
213
214 for(int i = 1; i < 64; i++){
215 intr_val = strtok(0,",");
216 pendingIntr[i] = atoi(intr_val);
217 }
218
219 return;
220}
221
222