| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: N2_Csr.h |
| 5 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
| 6 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
| 7 | * |
| 8 | * The above named program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public |
| 10 | * License version 2 as published by the Free Software Foundation. |
| 11 | * |
| 12 | * The above named program is distributed in the hope that it will be |
| 13 | * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public |
| 18 | * License along with this work; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
| 20 | * |
| 21 | * ========== Copyright Header End ============================================ |
| 22 | */ |
| 23 | #ifndef N2_CSR_H |
| 24 | #define N2_CSR_H |
| 25 | /************************************************************************ |
| 26 | ** |
| 27 | ** Copyright (C) 2006, Sun Microsystems, Inc. |
| 28 | ** |
| 29 | ** Sun considers its source code as an unpublished, proprietary |
| 30 | ** trade secret and it is available only under strict license provisions. |
| 31 | ** This copyright notice is placed here only to protect Sun in the event |
| 32 | ** the source is deemed a published work. Disassembly, decompilation, |
| 33 | ** or other means of reducing the object code to human readable form |
| 34 | ** is prohibited by the license agreement under which this code is |
| 35 | ** provided to the user or company in possession of this copy. |
| 36 | ** |
| 37 | *************************************************************************/ |
| 38 | #include "SS_Csr.h" |
| 39 | #include "N2_L2Csr.h" |
| 40 | #include "N2_McuCsr.h" |
| 41 | #include "N2_NcuCsr.h" |
| 42 | #include "N2_NiuCsr.h" |
| 43 | #include "N2_PcieCsr.h" |
| 44 | #include "N2_PiuCsr.h" |
| 45 | #include "N2_RstCsr.h" |
| 46 | #include "N2_SsiCsr.h" |
| 47 | |
| 48 | class N2_Model; |
| 49 | |
| 50 | class N2_Csr : public SS_Csr |
| 51 | { |
| 52 | public: |
| 53 | static int access_io(void* obj, int sid, int access, SS_Paddr addr, uint32_t size, uint64_t* data, uint64_t bitmask); |
| 54 | |
| 55 | static N2_Model* model; |
| 56 | |
| 57 | static const int PA_BITS; |
| 58 | static const uint64_t IO_MASK; |
| 59 | static const int IO_OFFSET; |
| 60 | static const uint64_t IO_RANGE; |
| 61 | |
| 62 | enum Range |
| 63 | { |
| 64 | RANGE_NCU = 0x80, |
| 65 | RANGE_NIU = 0x81, |
| 66 | RANGE_RNG = 0x82, |
| 67 | RANGE_MCU = 0x84, |
| 68 | RANGE_L2_TAP = 0x87, |
| 69 | RANGE_PIU = 0x88, |
| 70 | RANGE_RST = 0x89, |
| 71 | RANGE_NCU_2 = 0x90, |
| 72 | RANGE_L2_LOW = 0xa0, |
| 73 | RANGE_L2_HIGH = 0xbf, |
| 74 | RANGE_PCIE_LOW = 0xc0, |
| 75 | RANGE_PCIE_HIGH = 0xcf, |
| 76 | RANGE_SSI = 0xff |
| 77 | }; |
| 78 | |
| 79 | N2_Csr() { } |
| 80 | virtual ~N2_Csr() { } |
| 81 | |
| 82 | int read64( SS_Paddr pa, |
| 83 | uint64_t *data, |
| 84 | int access=MemoryTransaction::READ, |
| 85 | int sid=-1 ); |
| 86 | |
| 87 | int write64( SS_Paddr pa, |
| 88 | uint64_t value, |
| 89 | int access=MemoryTransaction::WRITE, |
| 90 | int sid=-1 ); |
| 91 | |
| 92 | void warm_reset() |
| 93 | { |
| 94 | l2_.warmReset(); |
| 95 | mcu_.warmReset(); |
| 96 | ncu_.warmReset(); |
| 97 | niu_.warmReset(); |
| 98 | pcie_.warmReset(); |
| 99 | piu_.warmReset(); |
| 100 | rst_.warmReset(); |
| 101 | ssi_.warmReset(); |
| 102 | } |
| 103 | |
| 104 | void reg_addr_space() |
| 105 | { |
| 106 | l2_.regAddrSpace(); |
| 107 | mcu_.regAddrSpace(); |
| 108 | |
| 109 | // commented out as the CSR address space registration clashes |
| 110 | // with the SAM side implementation of device models. |
| 111 | // ncu_.regAddrSpace(); |
| 112 | // niu_.regAddrSpace(); |
| 113 | // pcie_.regAddrSpace(); |
| 114 | // piu_.regAddrSpace(); |
| 115 | |
| 116 | rst_.regAddrSpace(); |
| 117 | ssi_.regAddrSpace(); |
| 118 | } |
| 119 | |
| 120 | protected: |
| 121 | /** |
| 122 | * check address mapping |
| 123 | */ |
| 124 | SS_Io::access_io_status address_map( SS_Paddr paddr, int access, int sid); |
| 125 | |
| 126 | N2_L2Csr l2_; |
| 127 | N2_McuCsr mcu_; |
| 128 | N2_NcuCsr ncu_; |
| 129 | N2_NiuCsr niu_; |
| 130 | N2_PcieCsr pcie_; |
| 131 | N2_PiuCsr piu_; |
| 132 | N2_RstCsr rst_; |
| 133 | N2_SsiCsr ssi_; |
| 134 | }; |
| 135 | |
| 136 | #endif // N2_CSR_H |