Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / lib / csr / src / N2_Csr.h

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: N2_Csr.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
* 
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
* 
* The above named program is distributed in the hope that it will be 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
* 
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
* 
* ========== Copyright Header End ============================================
*/
#ifndef N2_CSR_H
#define N2_CSR_H
/************************************************************************
**  
**  Copyright (C) 2006, Sun Microsystems, Inc.
**
**  Sun considers its source code as an unpublished, proprietary
**  trade secret and it is available only under strict license provisions.
**  This copyright notice is placed here only to protect Sun in the event 
**  the source is deemed a published work. Disassembly, decompilation,
**  or other means of reducing the object code to human readable form
**  is prohibited by the license agreement under which this code is
**  provided to the user or company in possession of this copy.
**
*************************************************************************/
#include "SS_Csr.h"
#include "N2_L2Csr.h"
#include "N2_McuCsr.h"
#include "N2_NcuCsr.h"
#include "N2_NiuCsr.h"
#include "N2_PcieCsr.h"
#include "N2_PiuCsr.h"
#include "N2_RstCsr.h"
#include "N2_SsiCsr.h"

class N2_Model;

class N2_Csr : public SS_Csr 
{
 public:
   static int access_io(void* obj, int sid, int access, SS_Paddr addr, uint32_t size, uint64_t* data, uint64_t bitmask);

   static N2_Model* model;

   static const int      PA_BITS;
   static const uint64_t IO_MASK;
   static const int      IO_OFFSET;
   static const uint64_t IO_RANGE;

   enum Range
   {
     RANGE_NCU       = 0x80,
     RANGE_NIU       = 0x81,
     RANGE_RNG       = 0x82,
     RANGE_MCU       = 0x84,
     RANGE_L2_TAP    = 0x87,
     RANGE_PIU       = 0x88,
     RANGE_RST       = 0x89,
     RANGE_NCU_2     = 0x90,
     RANGE_L2_LOW    = 0xa0,
     RANGE_L2_HIGH   = 0xbf,
     RANGE_PCIE_LOW  = 0xc0,
     RANGE_PCIE_HIGH = 0xcf,
     RANGE_SSI       = 0xff
   };

   N2_Csr() { }
   virtual ~N2_Csr() { }

   int read64( SS_Paddr pa, 
               uint64_t *data,
               int access=MemoryTransaction::READ,
               int sid=-1 );
   
   int write64( SS_Paddr pa, 
                uint64_t value, 
                int access=MemoryTransaction::WRITE,
                int sid=-1 );

   void warm_reset()
   {
     l2_.warmReset();
     mcu_.warmReset();
     ncu_.warmReset();
     niu_.warmReset();
     pcie_.warmReset();
     piu_.warmReset();
     rst_.warmReset();
     ssi_.warmReset();
   }

   void reg_addr_space()
   {
     l2_.regAddrSpace();
     mcu_.regAddrSpace();

     // commented out as the CSR address space registration clashes
     // with the SAM side implementation of device models.
     // ncu_.regAddrSpace();
     // niu_.regAddrSpace();
     // pcie_.regAddrSpace();
     // piu_.regAddrSpace();

     rst_.regAddrSpace();
     ssi_.regAddrSpace();
   }

 protected:
   /**
    * check address mapping
    */
   SS_Io::access_io_status address_map( SS_Paddr paddr, int access, int sid);
 
   N2_L2Csr l2_;
   N2_McuCsr mcu_;
   N2_NcuCsr ncu_;
   N2_NiuCsr niu_;
   N2_PcieCsr pcie_;
   N2_PiuCsr piu_;
   N2_RstCsr rst_;
   N2_SsiCsr ssi_;
};

#endif   // N2_CSR_H