| 1 | OBJECT irq0 |
| 2 | OBJECT irq0 TYPE swerver-interrupt { |
| 3 | need_ssi: 0x1 |
| 4 | queue: th00 |
| 5 | thread_base: 0x0 |
| 6 | } |
| 7 | OBJECT irqbus0 |
| 8 | OBJECT irqbus0 TYPE sparc-irq-bus { |
| 9 | } |
| 10 | OBJECT memory0 |
| 11 | OBJECT memory0 TYPE ram { |
| 12 | image: memory0_image |
| 13 | } |
| 14 | OBJECT memory0_image |
| 15 | OBJECT memory0_image TYPE image { |
| 16 | queue: th00 |
| 17 | size: 0x100000000 |
| 18 | } |
| 19 | OBJECT memory_cache |
| 20 | OBJECT memory_cache TYPE ram { |
| 21 | image: memory_cache_image |
| 22 | } |
| 23 | OBJECT memory_cache_image |
| 24 | OBJECT memory_cache_image TYPE image { |
| 25 | queue: th00 |
| 26 | size: 0x2000000000 |
| 27 | } |
| 28 | OBJECT memory_ciop |
| 29 | OBJECT memory_ciop TYPE ram { |
| 30 | image: memory_ciop_image |
| 31 | } |
| 32 | OBJECT memory_ciop_image |
| 33 | OBJECT memory_ciop_image TYPE image { |
| 34 | queue: th00 |
| 35 | size: 0x7f00000000 |
| 36 | } |
| 37 | OBJECT phys_mem0 |
| 38 | OBJECT phys_mem0 TYPE memory-space { |
| 39 | map: ((0x0,memory_cache,0x0,0x0,0x2000000000),(0x8000000000,memory_ciop,0x0,0x0,0x7f00000000),(0xff00000000,memory0,0x0,0x0,0x100000000)) |
| 40 | snoop_device: swvmem0 |
| 41 | timing_model: swvmem0 |
| 42 | } |
| 43 | OBJECT sim |
| 44 | OBJECT sim TYPE sim { |
| 45 | continue_disabled: 0x0 |
| 46 | cpu_switch_time: 0x1 |
| 47 | instruction_profile_line_size: 0x4 |
| 48 | instruction_profile_mode: instruction-cache-access-trace |
| 49 | time_model: "on" |
| 50 | } |
| 51 | OBJECT socket0 |
| 52 | OBJECT socket0 TYPE pli-socket { |
| 53 | close: 0x0 |
| 54 | cmd_intf: 0x1 |
| 55 | debug_level: 0x1 |
| 56 | enable_ras: 0x0 |
| 57 | force_pc: 0x1 |
| 58 | int_model: 0x1 |
| 59 | mem_model: 0x1 |
| 60 | open: 0x1 |
| 61 | pli_log: 0x0 |
| 62 | reg_cmp: 0x1 |
| 63 | replay_log: 0x0 |
| 64 | show_trap: 0x0 |
| 65 | socket: 0x32e4 |
| 66 | test: 0x0 |
| 67 | tlb_debug: 0x0 |
| 68 | tlb_sync: 0x1 |
| 69 | } |
| 70 | OBJECT stmmu00 |
| 71 | OBJECT stmmu00 TYPE swerver-thread-mmu { |
| 72 | disable-sun4u-interrupts: 0x1 |
| 73 | full-swerver-decode: 0x1 |
| 74 | ignore_asi_0x73: 0x1 |
| 75 | intr_trap_type: 0x60 |
| 76 | ma_cmpl_trap_type: 0x74 |
| 77 | match_rtl: 0x1 |
| 78 | model-real-sfar: 0x1 |
| 79 | niagara-mmu: 0x1 |
| 80 | stream_cmpl_trap_type: 0x70 |
| 81 | thread-status: 0x1 |
| 82 | } |
| 83 | OBJECT stmmu01 |
| 84 | OBJECT stmmu01 TYPE swerver-thread-mmu { |
| 85 | disable-sun4u-interrupts: 0x1 |
| 86 | full-swerver-decode: 0x1 |
| 87 | model-real-sfar: 0x1 |
| 88 | niagara-mmu: 0x1 |
| 89 | } |
| 90 | OBJECT stmmu02 |
| 91 | OBJECT stmmu02 TYPE swerver-thread-mmu { |
| 92 | disable-sun4u-interrupts: 0x1 |
| 93 | full-swerver-decode: 0x1 |
| 94 | model-real-sfar: 0x1 |
| 95 | niagara-mmu: 0x1 |
| 96 | } |
| 97 | OBJECT stmmu03 |
| 98 | OBJECT stmmu03 TYPE swerver-thread-mmu { |
| 99 | disable-sun4u-interrupts: 0x1 |
| 100 | full-swerver-decode: 0x1 |
| 101 | model-real-sfar: 0x1 |
| 102 | niagara-mmu: 0x1 |
| 103 | } |
| 104 | OBJECT stmmu04 |
| 105 | OBJECT stmmu04 TYPE swerver-thread-mmu { |
| 106 | disable-sun4u-interrupts: 0x1 |
| 107 | full-swerver-decode: 0x1 |
| 108 | model-real-sfar: 0x1 |
| 109 | niagara-mmu: 0x1 |
| 110 | } |
| 111 | OBJECT stmmu05 |
| 112 | OBJECT stmmu05 TYPE swerver-thread-mmu { |
| 113 | disable-sun4u-interrupts: 0x1 |
| 114 | full-swerver-decode: 0x1 |
| 115 | model-real-sfar: 0x1 |
| 116 | niagara-mmu: 0x1 |
| 117 | } |
| 118 | OBJECT stmmu06 |
| 119 | OBJECT stmmu06 TYPE swerver-thread-mmu { |
| 120 | disable-sun4u-interrupts: 0x1 |
| 121 | full-swerver-decode: 0x1 |
| 122 | model-real-sfar: 0x1 |
| 123 | niagara-mmu: 0x1 |
| 124 | } |
| 125 | OBJECT stmmu07 |
| 126 | OBJECT stmmu07 TYPE swerver-thread-mmu { |
| 127 | disable-sun4u-interrupts: 0x1 |
| 128 | full-swerver-decode: 0x1 |
| 129 | model-real-sfar: 0x1 |
| 130 | niagara-mmu: 0x1 |
| 131 | } |
| 132 | OBJECT swmmu0 |
| 133 | OBJECT swmmu0 TYPE swerver-proc-mmu { |
| 134 | } |
| 135 | OBJECT swvmem0 |
| 136 | OBJECT swvmem0 TYPE swerver-memory { |
| 137 | debug_level: 0x0 |
| 138 | irq: irq0 |
| 139 | queue: th00 |
| 140 | snoop: 0x0 |
| 141 | tso_checker: 0x1 |
| 142 | } |
| 143 | OBJECT swvp0 |
| 144 | OBJECT swvp0 TYPE swerver-processor { |
| 145 | mmu: swmmu0 |
| 146 | thread0: th00 |
| 147 | thread1: th01 |
| 148 | thread2: th02 |
| 149 | thread3: th03 |
| 150 | thread4: th04 |
| 151 | thread5: th05 |
| 152 | thread6: th06 |
| 153 | thread7: th07 |
| 154 | } |
| 155 | OBJECT th00 |
| 156 | OBJECT th00 TYPE niagara2 { |
| 157 | control_registers: (("mid",0x0)) |
| 158 | extra_irq_enable: 0x0 |
| 159 | freq_mhz: 0x320 |
| 160 | irq_bus: irqbus0 |
| 161 | max-trap-levels: 0x6 |
| 162 | mmu: stmmu00 |
| 163 | other_threads: (th01,th02,th03,th04,th05,th06,th07) |
| 164 | physical_memory: phys_mem0 |
| 165 | queue: th00 |
| 166 | thread_id: 0x0 |
| 167 | va_bits: 0x30 |
| 168 | } |
| 169 | OBJECT th01 |
| 170 | OBJECT th01 TYPE niagara2 { |
| 171 | control_registers: (("mid",0x1)) |
| 172 | extra_irq_enable: 0x0 |
| 173 | freq_mhz: 0x320 |
| 174 | irq_bus: irqbus0 |
| 175 | max-trap-levels: 0x6 |
| 176 | mmu: stmmu01 |
| 177 | other_threads: (th00,th02,th03,th04,th05,th06,th07) |
| 178 | physical_memory: phys_mem0 |
| 179 | queue: th01 |
| 180 | thread_id: 0x1 |
| 181 | va_bits: 0x30 |
| 182 | } |
| 183 | OBJECT th02 |
| 184 | OBJECT th02 TYPE niagara2 { |
| 185 | control_registers: (("mid",0x2)) |
| 186 | extra_irq_enable: 0x0 |
| 187 | freq_mhz: 0x320 |
| 188 | irq_bus: irqbus0 |
| 189 | max-trap-levels: 0x6 |
| 190 | mmu: stmmu02 |
| 191 | other_threads: (th00,th01,th03,th04,th05,th06,th07) |
| 192 | physical_memory: phys_mem0 |
| 193 | queue: th02 |
| 194 | thread_id: 0x2 |
| 195 | va_bits: 0x30 |
| 196 | } |
| 197 | OBJECT th03 |
| 198 | OBJECT th03 TYPE niagara2 { |
| 199 | control_registers: (("mid",0x3)) |
| 200 | extra_irq_enable: 0x0 |
| 201 | freq_mhz: 0x320 |
| 202 | irq_bus: irqbus0 |
| 203 | max-trap-levels: 0x6 |
| 204 | mmu: stmmu03 |
| 205 | other_threads: (th00,th01,th02,th04,th05,th06,th07) |
| 206 | physical_memory: phys_mem0 |
| 207 | queue: th03 |
| 208 | thread_id: 0x3 |
| 209 | va_bits: 0x30 |
| 210 | } |
| 211 | OBJECT th04 |
| 212 | OBJECT th04 TYPE niagara2 { |
| 213 | control_registers: (("mid",0x4)) |
| 214 | extra_irq_enable: 0x0 |
| 215 | freq_mhz: 0x320 |
| 216 | irq_bus: irqbus0 |
| 217 | max-trap-levels: 0x6 |
| 218 | mmu: stmmu04 |
| 219 | other_threads: (th00,th01,th02,th03,th05,th06,th07) |
| 220 | physical_memory: phys_mem0 |
| 221 | queue: th04 |
| 222 | thread_id: 0x4 |
| 223 | va_bits: 0x30 |
| 224 | } |
| 225 | OBJECT th05 |
| 226 | OBJECT th05 TYPE niagara2 { |
| 227 | control_registers: (("mid",0x5)) |
| 228 | extra_irq_enable: 0x0 |
| 229 | freq_mhz: 0x320 |
| 230 | irq_bus: irqbus0 |
| 231 | max-trap-levels: 0x6 |
| 232 | mmu: stmmu05 |
| 233 | other_threads: (th00,th01,th02,th03,th04,th06,th07) |
| 234 | physical_memory: phys_mem0 |
| 235 | queue: th05 |
| 236 | thread_id: 0x5 |
| 237 | va_bits: 0x30 |
| 238 | } |
| 239 | OBJECT th06 |
| 240 | OBJECT th06 TYPE niagara2 { |
| 241 | control_registers: (("mid",0x6)) |
| 242 | extra_irq_enable: 0x0 |
| 243 | freq_mhz: 0x320 |
| 244 | irq_bus: irqbus0 |
| 245 | max-trap-levels: 0x6 |
| 246 | mmu: stmmu06 |
| 247 | other_threads: (th00,th01,th02,th03,th04,th05,th07) |
| 248 | physical_memory: phys_mem0 |
| 249 | queue: th06 |
| 250 | thread_id: 0x6 |
| 251 | va_bits: 0x30 |
| 252 | } |
| 253 | OBJECT th07 |
| 254 | OBJECT th07 TYPE niagara2 { |
| 255 | control_registers: (("mid",0x7)) |
| 256 | extra_irq_enable: 0x0 |
| 257 | freq_mhz: 0x320 |
| 258 | irq_bus: irqbus0 |
| 259 | max-trap-levels: 0x6 |
| 260 | mmu: stmmu07 |
| 261 | other_threads: (th00,th01,th02,th03,th04,th05,th06) |
| 262 | physical_memory: phys_mem0 |
| 263 | queue: th07 |
| 264 | thread_id: 0x7 |
| 265 | va_bits: 0x30 |
| 266 | } |
| 267 | socket0.socket = 0x32e4 |