sam-t2/sam/cpus/vonk/ss/api/pli/tst/test00.ref

OBJECT irq0
OBJECT irq0 TYPE swerver-interrupt {
  need_ssi: 0x1
  queue: th00
  thread_base: 0x0
}
OBJECT irqbus0
OBJECT irqbus0 TYPE sparc-irq-bus {
}
OBJECT memory0
OBJECT memory0 TYPE ram {
  image: memory0_image
}
OBJECT memory0_image
OBJECT memory0_image TYPE image {
  queue: th00
  size: 0x100000000
}
OBJECT memory_cache
OBJECT memory_cache TYPE ram {
  image: memory_cache_image
}
OBJECT memory_cache_image
OBJECT memory_cache_image TYPE image {
  queue: th00
  size: 0x2000000000
}
OBJECT memory_ciop
OBJECT memory_ciop TYPE ram {
  image: memory_ciop_image
}
OBJECT memory_ciop_image
OBJECT memory_ciop_image TYPE image {
  queue: th00
  size: 0x7f00000000
}
OBJECT phys_mem0
OBJECT phys_mem0 TYPE memory-space {
  map: ((0x0,memory_cache,0x0,0x0,0x2000000000),(0x8000000000,memory_ciop,0x0,0x0,0x7f00000000),(0xff00000000,memory0,0x0,0x0,0x100000000))
  snoop_device: swvmem0
  timing_model: swvmem0
}
OBJECT sim
OBJECT sim TYPE sim {
  continue_disabled: 0x0
  cpu_switch_time: 0x1
  instruction_profile_line_size: 0x4
  instruction_profile_mode: instruction-cache-access-trace
  time_model: "on"
}
OBJECT socket0
OBJECT socket0 TYPE pli-socket {
  close: 0x0
  cmd_intf: 0x1
  debug_level: 0x1
  enable_ras: 0x0
  force_pc: 0x1
  int_model: 0x1
  mem_model: 0x1
  open: 0x1
  pli_log: 0x0
  reg_cmp: 0x1
  replay_log: 0x0
  show_trap: 0x0
  socket: 0x32e4
  test: 0x0
  tlb_debug: 0x0
  tlb_sync: 0x1
}
OBJECT stmmu00
OBJECT stmmu00 TYPE swerver-thread-mmu {
  disable-sun4u-interrupts: 0x1
  full-swerver-decode: 0x1
  ignore_asi_0x73: 0x1
  intr_trap_type: 0x60
  ma_cmpl_trap_type: 0x74
  match_rtl: 0x1
  model-real-sfar: 0x1
  niagara-mmu: 0x1
  stream_cmpl_trap_type: 0x70
  thread-status: 0x1
}
OBJECT stmmu01
OBJECT stmmu01 TYPE swerver-thread-mmu {
  disable-sun4u-interrupts: 0x1
  full-swerver-decode: 0x1
  model-real-sfar: 0x1
  niagara-mmu: 0x1
}
OBJECT stmmu02
OBJECT stmmu02 TYPE swerver-thread-mmu {
  disable-sun4u-interrupts: 0x1
  full-swerver-decode: 0x1
  model-real-sfar: 0x1
  niagara-mmu: 0x1
}
OBJECT stmmu03
OBJECT stmmu03 TYPE swerver-thread-mmu {
  disable-sun4u-interrupts: 0x1
  full-swerver-decode: 0x1
  model-real-sfar: 0x1
  niagara-mmu: 0x1
}
OBJECT stmmu04
OBJECT stmmu04 TYPE swerver-thread-mmu {
  disable-sun4u-interrupts: 0x1
  full-swerver-decode: 0x1
  model-real-sfar: 0x1
  niagara-mmu: 0x1
}
OBJECT stmmu05
OBJECT stmmu05 TYPE swerver-thread-mmu {
  disable-sun4u-interrupts: 0x1
  full-swerver-decode: 0x1
  model-real-sfar: 0x1
  niagara-mmu: 0x1
}
OBJECT stmmu06
OBJECT stmmu06 TYPE swerver-thread-mmu {
  disable-sun4u-interrupts: 0x1
  full-swerver-decode: 0x1
  model-real-sfar: 0x1
  niagara-mmu: 0x1
}
OBJECT stmmu07
OBJECT stmmu07 TYPE swerver-thread-mmu {
  disable-sun4u-interrupts: 0x1
  full-swerver-decode: 0x1
  model-real-sfar: 0x1
  niagara-mmu: 0x1
}
OBJECT swmmu0
OBJECT swmmu0 TYPE swerver-proc-mmu {
}
OBJECT swvmem0
OBJECT swvmem0 TYPE swerver-memory {
  debug_level: 0x0
  irq: irq0
  queue: th00
  snoop: 0x0
  tso_checker: 0x1
}
OBJECT swvp0
OBJECT swvp0 TYPE swerver-processor {
  mmu: swmmu0
  thread0: th00
  thread1: th01
  thread2: th02
  thread3: th03
  thread4: th04
  thread5: th05
  thread6: th06
  thread7: th07
}
OBJECT th00
OBJECT th00 TYPE niagara2 {
  control_registers: (("mid",0x0))
  extra_irq_enable: 0x0
  freq_mhz: 0x320
  irq_bus: irqbus0
  max-trap-levels: 0x6
  mmu: stmmu00
  other_threads: (th01,th02,th03,th04,th05,th06,th07)
  physical_memory: phys_mem0
  queue: th00
  thread_id: 0x0
  va_bits: 0x30
}
OBJECT th01
OBJECT th01 TYPE niagara2 {
  control_registers: (("mid",0x1))
  extra_irq_enable: 0x0
  freq_mhz: 0x320
  irq_bus: irqbus0
  max-trap-levels: 0x6
  mmu: stmmu01
  other_threads: (th00,th02,th03,th04,th05,th06,th07)
  physical_memory: phys_mem0
  queue: th01
  thread_id: 0x1
  va_bits: 0x30
}
OBJECT th02
OBJECT th02 TYPE niagara2 {
  control_registers: (("mid",0x2))
  extra_irq_enable: 0x0
  freq_mhz: 0x320
  irq_bus: irqbus0
  max-trap-levels: 0x6
  mmu: stmmu02
  other_threads: (th00,th01,th03,th04,th05,th06,th07)
  physical_memory: phys_mem0
  queue: th02
  thread_id: 0x2
  va_bits: 0x30
}
OBJECT th03
OBJECT th03 TYPE niagara2 {
  control_registers: (("mid",0x3))
  extra_irq_enable: 0x0
  freq_mhz: 0x320
  irq_bus: irqbus0
  max-trap-levels: 0x6
  mmu: stmmu03
  other_threads: (th00,th01,th02,th04,th05,th06,th07)
  physical_memory: phys_mem0
  queue: th03
  thread_id: 0x3
  va_bits: 0x30
}
OBJECT th04
OBJECT th04 TYPE niagara2 {
  control_registers: (("mid",0x4))
  extra_irq_enable: 0x0
  freq_mhz: 0x320
  irq_bus: irqbus0
  max-trap-levels: 0x6
  mmu: stmmu04
  other_threads: (th00,th01,th02,th03,th05,th06,th07)
  physical_memory: phys_mem0
  queue: th04
  thread_id: 0x4
  va_bits: 0x30
}
OBJECT th05
OBJECT th05 TYPE niagara2 {
  control_registers: (("mid",0x5))
  extra_irq_enable: 0x0
  freq_mhz: 0x320
  irq_bus: irqbus0
  max-trap-levels: 0x6
  mmu: stmmu05
  other_threads: (th00,th01,th02,th03,th04,th06,th07)
  physical_memory: phys_mem0
  queue: th05
  thread_id: 0x5
  va_bits: 0x30
}
OBJECT th06
OBJECT th06 TYPE niagara2 {
  control_registers: (("mid",0x6))
  extra_irq_enable: 0x0
  freq_mhz: 0x320
  irq_bus: irqbus0
  max-trap-levels: 0x6
  mmu: stmmu06
  other_threads: (th00,th01,th02,th03,th04,th05,th07)
  physical_memory: phys_mem0
  queue: th06
  thread_id: 0x6
  va_bits: 0x30
}
OBJECT th07
OBJECT th07 TYPE niagara2 {
  control_registers: (("mid",0x7))
  extra_irq_enable: 0x0
  freq_mhz: 0x320
  irq_bus: irqbus0
  max-trap-levels: 0x6
  mmu: stmmu07
  other_threads: (th00,th01,th02,th03,th04,th05,th06)
  physical_memory: phys_mem0
  queue: th07
  thread_id: 0x7
  va_bits: 0x30
}
socket0.socket = 0x32e4