| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: schizo_iommu.h |
| 5 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
| 6 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
| 7 | * |
| 8 | * The above named program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public |
| 10 | * License version 2 as published by the Free Software Foundation. |
| 11 | * |
| 12 | * The above named program is distributed in the hope that it will be |
| 13 | * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public |
| 18 | * License along with this work; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
| 20 | * |
| 21 | * ========== Copyright Header End ============================================ |
| 22 | */ |
| 23 | // |
| 24 | // Copyright (C) 1994, Sun Microsystems, Inc. |
| 25 | // |
| 26 | #ifndef SCHIZO_IOMMU_H |
| 27 | #define SCHIZO_IOMMU_H |
| 28 | |
| 29 | #pragma ident "@(#)1.1 01/08/23 schizo_iommu.h" |
| 30 | |
| 31 | #define NUM_TLB_ENTRIES 16 |
| 32 | |
| 33 | #define VPN_BEGIN8 13 //VPN begins at bit13 |
| 34 | #define VPN_BEGIN64 16 //VPN begins at bit16 |
| 35 | #define BASE_ADDR_MASK 0xfffffff //28 bits |
| 36 | #define VPN_OFFSET 0x3ff //10 bits |
| 37 | #define PTR_OFFSET 10 //to shift by 10 |
| 38 | #define TSB_PTR_PADDING 3 //TTE is aligned at 8k byte boundry |
| 39 | |
| 40 | |
| 41 | #define IO_VADDR_OFFSET 13 |
| 42 | #define io_num_page_sizes 2 |
| 43 | #define num_tbl_sizes 8 |
| 44 | |
| 45 | //#define IOMMU_CNTRL_MASK 0xff007 //FIXME ??? |
| 46 | #define IOMMU_CNTRL_MASK 0xff0007 // pp 200 |
| 47 | //#define TSB_BSE_MASK_HI 0x1ff //FIXME ??? |
| 48 | #define TSB_BSE_MASK 0x7ffffffe000 // pp 204 |
| 49 | #define FLUSH_REG_MASK 0xffffe000 |
| 50 | |
| 51 | |
| 52 | /* TLB tag CAM format entry, epp 196 */ |
| 53 | typedef struct s_tlb_tag { |
| 54 | uint32_t rsvd1:27; // [63:37] reserved, read as zero |
| 55 | uint32_t context1:5; // [36:32] rw |
| 56 | uint32_t context2:7; // [31:25] rw |
| 57 | uint32_t err_stat:2; // [24:23] error status |
| 58 | uint32_t err:1; // [22] error |
| 59 | uint32_t w:1; // [21] writable |
| 60 | uint32_t s:1; // [20] streamable/consistant |
| 61 | uint32_t size:1; // [19] page size 0=8k 1=64k |
| 62 | uint32_t VA_31_13:19; // [18:00] 19bit VPN from PCI BUS |
| 63 | } s_tlb_tag; |
| 64 | |
| 65 | typedef union u_tlb_tag { |
| 66 | s_tlb_tag s; |
| 67 | uint64_t l; |
| 68 | } u_tlb_tag; |
| 69 | |
| 70 | /* TLB data RAM format entry */ |
| 71 | /* the main reason we have to split [42:13] into two is that TTE has |
| 72 | * that field cross 32bit boundary and force it to be splitted, so |
| 73 | * we have to do the same for value assignment purpose. epp 197 */ |
| 74 | typedef struct s_iotlb_data { |
| 75 | uint32_t rsvd1:31; // [63:33] reserved, read as zero |
| 76 | uint32_t v:1; // [32] valid bit |
| 77 | uint32_t u:1; // [31] reserved, read as zero |
| 78 | uint32_t c:1; // [30] is it cachable |
| 79 | uint32_t PA_42_32:11; // [42:13] PA <42:13> |
| 80 | uint32_t PA_31_13:19; // [42:13] PA <42:13> |
| 81 | } s_iotlb_data; |
| 82 | |
| 83 | typedef union u_iotlb_data { |
| 84 | s_iotlb_data s; |
| 85 | uint64_t l; |
| 86 | } u_iotlb_data; |
| 87 | |
| 88 | //Format of a tte Entry Data |
| 89 | |
| 90 | typedef struct s_tte_data { |
| 91 | uint32_t v:1; // [63] valid |
| 92 | uint32_t rsvd1:1; // [62] reserved, read as zero |
| 93 | uint32_t size:1; // [61] page size, 0 = 8kb, 1 = 64kb |
| 94 | uint32_t s:1; // [60] page is streamable |
| 95 | uint32_t rsvd2:1; // [59] reserved, read as zero |
| 96 | uint32_t context1:5; // [58:54] software use |
| 97 | uint32_t context2:7; // [53:47] software use |
| 98 | uint32_t rsvd3:4; // [46:43] reserved, read as zero |
| 99 | uint32_t PA_42_32:11; // [42:13] PA <42:13> |
| 100 | uint32_t PA_31_13:19; // [42:13] PA <42:13> |
| 101 | uint32_t soft1:6; // [12:07] software use |
| 102 | uint32_t rsvd4:2; // [06:05] reserved, read as zero |
| 103 | uint32_t c:1; // [04] cacheable |
| 104 | uint32_t rsvd5:2; // [03:02] reserved, read as zero |
| 105 | uint32_t w:1; // [01] writeable page |
| 106 | uint32_t rsvd6:1; // [00] reserved, read as zero |
| 107 | } s_tte_data; |
| 108 | |
| 109 | typedef union u_tte_data { |
| 110 | s_tte_data s; |
| 111 | uint64_t l; |
| 112 | } u_tte_data; |
| 113 | //////////////////////////////////////// |
| 114 | //All THE DIAGNOSTIC ACCESS REGISTERS // |
| 115 | ////////////////////////////////////////// |
| 116 | |
| 117 | //SBus Virtual Address Diagostic Register |
| 118 | // epp 208 |
| 119 | typedef struct s_pcibus_va_diag { |
| 120 | uint32_t rsvd1:32; //read as zero |
| 121 | uint32_t pcibus_vpn:19; //pci bus VPN -rw |
| 122 | uint32_t rsvd2:13; //read as zero |
| 123 | } s_pcibus_va_diag; |
| 124 | |
| 125 | union u_pcibus_va_diag { |
| 126 | s_pcibus_va_diag s; |
| 127 | uint64_t l; |
| 128 | } u_pcibus_va_diag; |
| 129 | |
| 130 | //Tag Compare Diagnostic Access |
| 131 | // epp 208 |
| 132 | typedef struct s_tag_cmpr_diag { |
| 133 | uint32_t rsvd1:32; //read as zero |
| 134 | uint32_t rsvd2:16; //read as zero |
| 135 | uint32_t comp:16; //tag_cmpr for each entry-r |
| 136 | } s_tag_cmpr_diag; |
| 137 | |
| 138 | union u_tag_cmpr_diag { |
| 139 | s_tag_cmpr_diag s; |
| 140 | uint64_t l; |
| 141 | } u_tag_cmpr_diag; |
| 142 | |
| 143 | //LRU_Q Diagnostic Access |
| 144 | // epp 207 |
| 145 | typedef struct s_lru_q_diag { |
| 146 | uint32_t rsvd1:32; //read as zero |
| 147 | uint32_t rsvd2:28; //read as zero |
| 148 | uint32_t lru_do:4; //lru entry selected -r |
| 149 | } s_lru_q_diag; |
| 150 | |
| 151 | union u_lru_q_diag { |
| 152 | s_lru_q_diag s; |
| 153 | uint64_t l; |
| 154 | } u_lru_q_diag; |
| 155 | |
| 156 | // Registers required for IOMMU operations |
| 157 | //------------------------------------------- |
| 158 | // epp 200 |
| 159 | typedef struct s_iommu_cntrl_reg { |
| 160 | uint32_t rsvd1:32; // [63:32] reserved, read as zero |
| 161 | uint32_t rsvd2:8; // [31:24] reserved, read as zero |
| 162 | uint32_t lru_lck_en:1; // [23] LRU lock enable |
| 163 | uint32_t lru_lck_ptr:4; // [22:19] LRU tlb entry lock pointer |
| 164 | uint32_t tsb_size:3; // [18:16] size of tsb |
| 165 | uint32_t rsvd:13; // [15:03] reserved, read as zero |
| 166 | uint32_t tbw_size:1; // [02] assumed page size |
| 167 | uint32_t mmu_de:1; // [01] Diag mode enable R:W |
| 168 | uint32_t mmu_en:1; // [00] Iommu enable R:W |
| 169 | } s_iommu_cntrl_reg; |
| 170 | |
| 171 | union u_iommu_cntrl_reg { |
| 172 | s_iommu_cntrl_reg s; |
| 173 | uint64_t l; |
| 174 | } u_iommu_cntrl_reg; |
| 175 | |
| 176 | typedef struct s_imtbr { |
| 177 | uint32_t rsvd1:21; // [63:43] reserved, read as zero |
| 178 | uint32_t base_hi:11; // [42:32] upper 11 bits of PA |
| 179 | uint32_t base_lo:19; // [31:13] "" 19 bits of PA |
| 180 | uint32_t rsvd2:13; // [12:00] read as zero R |
| 181 | } s_imtbr; |
| 182 | |
| 183 | union u_imtbr { |
| 184 | s_imtbr s; |
| 185 | uint64_t l; |
| 186 | } u_imtbr; |
| 187 | |
| 188 | typedef struct s_flush_page_reg { |
| 189 | uint32_t rsvd1:32; // [63:32] write has no effect |
| 190 | uint32_t VA:19; // [31:13] V Page no |
| 191 | uint32_t rsvd2:13; // [12:00] write has no effect |
| 192 | } s_flush_page_reg; |
| 193 | |
| 194 | union u_flush_page_reg { |
| 195 | s_flush_page_reg s; |
| 196 | uint64_t l; |
| 197 | } u_flush_page_reg; |
| 198 | |
| 199 | typedef struct s_flush_context_reg { |
| 200 | uint32_t rsvd1:32; // [63:32] write has no effect |
| 201 | uint32_t rsvd2:20; // [31:12] write has no effect |
| 202 | uint32_t context:12; // [11:0] context to flush |
| 203 | } s_flush_context_reg; |
| 204 | |
| 205 | union u_flush_context_reg { |
| 206 | s_flush_context_reg s; |
| 207 | uint64_t l; |
| 208 | } u_flush_context_reg; |
| 209 | |
| 210 | |
| 211 | #endif // SCHIZO_IOMMU_H |