sam-t2/sam/devices/schizo/include/schizo_iommu.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: schizo_iommu.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
//
// Copyright (C) 1994, Sun Microsystems, Inc.
//
#ifndef SCHIZO_IOMMU_H
#define SCHIZO_IOMMU_H

#pragma ident "@(#)1.1  01/08/23        schizo_iommu.h"

#define NUM_TLB_ENTRIES         16

#define VPN_BEGIN8                      13      //VPN begins at bit13
#define VPN_BEGIN64                     16      //VPN begins at bit16
#define BASE_ADDR_MASK                  0xfffffff       //28 bits
#define VPN_OFFSET                      0x3ff   //10 bits
#define PTR_OFFSET                      10      //to shift by 10
#define TSB_PTR_PADDING                 3       //TTE is aligned at 8k byte boundry


#define  IO_VADDR_OFFSET                13
#define  io_num_page_sizes              2
#define  num_tbl_sizes                  8

//#define IOMMU_CNTRL_MASK                0xff007 //FIXME ???
#define IOMMU_CNTRL_MASK                0xff0007        // pp 200
//#define  TSB_BSE_MASK_HI                0x1ff //FIXME ???
#define  TSB_BSE_MASK                   0x7ffffffe000   // pp 204
#define  FLUSH_REG_MASK                 0xffffe000


/* TLB tag CAM format entry, epp 196 */
typedef struct s_tlb_tag {
        uint32_t rsvd1:27;      // [63:37] reserved, read as zero
        uint32_t context1:5;    // [36:32] rw
        uint32_t context2:7;    // [31:25] rw
        uint32_t err_stat:2;    // [24:23] error status
        uint32_t err:1;         // [22]    error
        uint32_t w:1;           // [21]    writable
        uint32_t s:1;           // [20]    streamable/consistant
        uint32_t size:1;        // [19]    page size 0=8k 1=64k
        uint32_t VA_31_13:19;   // [18:00] 19bit VPN from PCI BUS
} s_tlb_tag;

typedef union u_tlb_tag {
        s_tlb_tag s;
        uint64_t l;
} u_tlb_tag;

/* TLB data RAM format entry */
/* the main reason we have to split [42:13] into two is that TTE has
 * that field cross 32bit boundary and force it to be splitted, so
 * we have to do the same for value assignment purpose. epp 197 */
typedef struct s_iotlb_data {
        uint32_t rsvd1:31;      // [63:33] reserved, read as zero
        uint32_t v:1;           // [32]    valid bit
        uint32_t u:1;           // [31]    reserved, read as zero
        uint32_t c:1;           // [30]    is it cachable
        uint32_t PA_42_32:11;   // [42:13] PA <42:13>
        uint32_t PA_31_13:19;   // [42:13] PA <42:13>
} s_iotlb_data;

typedef union u_iotlb_data {
        s_iotlb_data s;
        uint64_t l;
} u_iotlb_data;

//Format of a tte Entry Data

typedef struct s_tte_data {
        uint32_t v:1;           // [63]    valid
        uint32_t rsvd1:1;       // [62]    reserved, read as zero
        uint32_t size:1;        // [61]    page size, 0 = 8kb, 1 = 64kb
        uint32_t s:1;           // [60]    page is streamable
        uint32_t rsvd2:1;       // [59]    reserved, read as zero
        uint32_t context1:5;    // [58:54] software use
        uint32_t context2:7;    // [53:47] software use
        uint32_t rsvd3:4;       // [46:43] reserved, read as zero
        uint32_t PA_42_32:11;   // [42:13] PA <42:13>
        uint32_t PA_31_13:19;   // [42:13] PA <42:13>
        uint32_t soft1:6;       // [12:07] software use
        uint32_t rsvd4:2;       // [06:05] reserved, read as zero
        uint32_t c:1;           // [04]    cacheable
        uint32_t rsvd5:2;       // [03:02] reserved, read as zero
        uint32_t w:1;           // [01]    writeable page
        uint32_t rsvd6:1;       // [00]    reserved, read as zero
} s_tte_data;

typedef union u_tte_data {
        s_tte_data s;
        uint64_t l;
} u_tte_data;
////////////////////////////////////////
//All THE DIAGNOSTIC ACCESS REGISTERS //
//////////////////////////////////////////

//SBus Virtual Address Diagostic Register
// epp 208
typedef struct s_pcibus_va_diag {
        uint32_t rsvd1:32;      //read as zero
        uint32_t pcibus_vpn:19; //pci bus VPN -rw
        uint32_t rsvd2:13;      //read as zero
} s_pcibus_va_diag;

union u_pcibus_va_diag {
        s_pcibus_va_diag s;
        uint64_t l;
} u_pcibus_va_diag;

//Tag Compare Diagnostic Access
// epp 208
typedef struct s_tag_cmpr_diag {
        uint32_t rsvd1:32;      //read as zero
        uint32_t rsvd2:16;      //read as zero
        uint32_t comp:16;       //tag_cmpr for each entry-r
} s_tag_cmpr_diag;

union u_tag_cmpr_diag {
        s_tag_cmpr_diag s;
        uint64_t l;
} u_tag_cmpr_diag;

//LRU_Q Diagnostic Access
// epp 207
typedef struct s_lru_q_diag {
        uint32_t rsvd1:32;      //read as zero
        uint32_t rsvd2:28;      //read as zero
        uint32_t lru_do:4;      //lru entry selected -r
} s_lru_q_diag;

union u_lru_q_diag {
        s_lru_q_diag s;
        uint64_t l;
} u_lru_q_diag;

// Registers required for IOMMU operations
//-------------------------------------------
// epp 200
typedef struct s_iommu_cntrl_reg {
        uint32_t rsvd1:32;      // [63:32] reserved, read as zero
        uint32_t rsvd2:8;       // [31:24] reserved, read as zero
        uint32_t lru_lck_en:1;  // [23]    LRU lock enable
        uint32_t lru_lck_ptr:4; // [22:19] LRU tlb entry lock pointer
        uint32_t tsb_size:3;    // [18:16] size of tsb
        uint32_t rsvd:13;       // [15:03] reserved, read as zero
        uint32_t tbw_size:1;    // [02]    assumed page size
        uint32_t mmu_de:1;      // [01]    Diag mode enable R:W
        uint32_t mmu_en:1;      // [00]    Iommu enable R:W
} s_iommu_cntrl_reg;

union u_iommu_cntrl_reg {
        s_iommu_cntrl_reg s;
        uint64_t l;
} u_iommu_cntrl_reg;

typedef struct s_imtbr {
        uint32_t rsvd1:21;      // [63:43] reserved, read as zero
        uint32_t base_hi:11;    // [42:32] upper 11 bits of PA
        uint32_t base_lo:19;    // [31:13]   ""  19 bits of PA
        uint32_t rsvd2:13;      // [12:00] read as zero R
} s_imtbr;

union u_imtbr {
        s_imtbr s;
        uint64_t l;
} u_imtbr;

typedef struct s_flush_page_reg {
        uint32_t rsvd1:32;      // [63:32] write has no effect
        uint32_t VA:19;         // [31:13] V Page no
        uint32_t rsvd2:13;      // [12:00] write has no effect
} s_flush_page_reg;

union u_flush_page_reg {
        s_flush_page_reg s;
        uint64_t l;
} u_flush_page_reg;

typedef struct s_flush_context_reg {
        uint32_t rsvd1:32;      // [63:32] write has no effect
        uint32_t rsvd2:20;      // [31:12] write has no effect
        uint32_t context:12;    // [11:0] context to flush
} s_flush_context_reg;

union u_flush_context_reg {
        s_flush_context_reg s;
        uint64_t l;
} u_flush_context_reg;


#endif // SCHIZO_IOMMU_H