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* Hypervisor Software File: ncs.h
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#pragma ident "@(#)ncs.h 1.3 07/05/03 SMI"
#define MAU_STATE_UNCONFIGURED 0x0
#define MAU_STATE_RUNNING 0x1 /* mau configured & running */
#define MAU_STATE_ERROR 0xF /* mau is in the error state */
#define CWQ_STATE_UNCONFIGURED 0x0
#define CWQ_STATE_RUNNING 0x1 /* cwq configured & running */
#define CWQ_STATE_ERROR 0xF /* cwq is in the error state */
#define NCS_QSTATE_UNCONFIGURED 0
#define NCS_QSTATE_CONFIGURED 1
#define NCS_MIN_MAU_NENTRIES 2
#define NCS_MIN_CWQ_NENTRIES 2
#define NCS_MAX_CWQ_NENTRIES 64
* Queuing structure used by crypto hypervisor support
* to represent queue of requests for MAU/CWQ. Kernel
* side inserts requests into the queue which are
* subsequently picked up in the context of the
* Struct is globally kept in a per-MAU/CWQ array.
* NCS code indexes into appropriate queue
* using the ID of the MAU/CWQ (Core) on which
* it's running at the time.
typedef struct mau_queue
{
uint64_t mq_cpu_pid
; /* HV intr target */
* The MA and CWQ interrupt cookies are obtained
* via vdev_intr_register() and passed to
* vdev_intr_generate() to initiate the interrupt.
* The active field gets set via the respective
* mau/cwq_intr() routines.
typedef struct crypto_intr
{
* Saves us from doing mulx's when using a
* mau/cwq id as an index into guest.maus[]
#define GUEST_MAUS_SHIFT SHIFT_LONG
#define GUEST_CWQS_SHIFT SHIFT_LONG