* ========== Copyright Header Begin ==========================================
* Hypervisor Software File: piu_regs.h
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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* or without modification, are permitted provided that the following
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* may be used to endorse or promote products derived from this software
* without specific prior written permission.
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* ========== Copyright Header End ============================================
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
#pragma ident "@(#)piu_regs.h 1.1 07/05/03 SMI"
#define PIU_DLC_CRU_CSR_A_DMC_DBG_SEL_A_REG_ADDR 0x53000
#define PIU_DLC_CRU_CSR_A_DMC_DBG_SEL_A_REG_POR_VALUE 0x0000000000000000
#define PIU_DLC_CRU_CSR_A_DMC_DBG_SEL_B_REG_ADDR 0x53008
#define PIU_DLC_CRU_CSR_A_DMC_DBG_SEL_B_REG_POR_VALUE 0x0000000000000000
#define PIU_DLC_CRU_CSR_A_DMC_PCIE_CFG_ADDR 0x53100
#define PIU_DLC_CRU_CSR_A_DMC_PCIE_CFG_POR_VALUE 0x0000000000000000
/* Register definitions from :/verif/env/dmu/vera/csrtool/csr_a.csr_define.vri 1.3 */
#define PIU_DLC_MMU_CSR_A_CTL_ADDR 0x40000
#define PIU_DLC_MMU_CSR_A_CTL_POR_VALUE 0x0000000000000000
#define PIU_DLC_MMU_CSR_A_TSB_ADDR 0x40008
#define PIU_DLC_MMU_CSR_A_TSB_POR_VALUE 0x0000000000000000
#define PIU_DLC_MMU_CSR_A_FSH_ADDR 0x40100
#define PIU_DLC_MMU_CSR_A_FSH_POR_VALUE 0x0000000000000000
#define PIU_DLC_MMU_CSR_A_INV_ADDR 0x40108
#define PIU_DLC_MMU_CSR_A_INV_POR_VALUE 0x0000000000000000
#define PIU_DLC_MMU_CSR_A_LOG_ADDR 0x41000
#define PIU_DLC_MMU_CSR_A_LOG_POR_VALUE 0x00000000001fffff
#define PIU_DLC_MMU_CSR_A_INT_EN_ADDR 0x41008
#define PIU_DLC_MMU_CSR_A_INT_EN_POR_VALUE 0x0000000000000000
#define PIU_DLC_MMU_CSR_A_EN_ERR_ADDR 0x41010
#define PIU_DLC_MMU_CSR_A_EN_ERR_POR_VALUE 0x0000000000000000
#define PIU_DLC_MMU_CSR_A_ERR_RW1C_ALIAS_ADDR 0x41018
#define PIU_DLC_MMU_CSR_A_ERR_RW1C_ALIAS_POR_VALUE 0x0000000000000000
#define PIU_DLC_MMU_CSR_A_ERR_RW1S_ALIAS_ADDR 0x41020
#define PIU_DLC_MMU_CSR_A_ERR_RW1S_ALIAS_POR_VALUE 0x0000000000000000
#define PIU_DLC_MMU_CSR_A_FLTA_ADDR 0x41028
#define PIU_DLC_MMU_CSR_A_FLTA_POR_VALUE 0x0000000000000000
#define PIU_DLC_MMU_CSR_A_FLTS_ADDR 0x41030
#define PIU_DLC_MMU_CSR_A_FLTS_POR_VALUE 0x0000000000000000
#define PIU_DLC_MMU_CSR_A_PRFC_ADDR 0x42000
#define PIU_DLC_MMU_CSR_A_PRFC_POR_VALUE 0x0000000000000000
#define PIU_DLC_MMU_CSR_A_PRF0_ADDR 0x42008
#define PIU_DLC_MMU_CSR_A_PRF0_POR_VALUE 0x0000000000000000
#define PIU_DLC_MMU_CSR_A_PRF1_ADDR 0x42010
#define PIU_DLC_MMU_CSR_A_PRF1_POR_VALUE 0x0000000000000000
#define PIU_DLC_MMU_CSR_A_VTB_ADDR 0x46000
/* This register maps to a ram with a depth of: 64 */
#define PIU_DLC_MMU_CSR_A_VTB_POR_VALUE 0x0000000000000000
#define PIU_DLC_MMU_CSR_A_PTB_ADDR 0x47000
/* This register maps to a ram with a depth of: 64 */
#define PIU_DLC_MMU_CSR_A_PTB_POR_VALUE 0x0000000000000000
#define PIU_DLC_MMU_CSR_A_TDB_ADDR 0x48000
/* This register maps to a ram with a depth of: 512 */
/* contains x #define PIU_DLC_MMU_CSR_A_TDB_POR_VALUE 0xxxxxxxxxxxxxxxxxxxxx00000xxxxxxxxxxxxxxxxxxxxxxxxxx0000000xxxxxx */
#define PIU_DLC_MMU_CSR_A_DEV2IOTSB_ADDR 0x49000
/* This register maps to a ram with a depth of: 16 */
#define PIU_DLC_MMU_CSR_A_DEV2IOTSB_POR_VALUE 0x0000000000000000
#define PIU_DLC_MMU_CSR_A_IOTSBDESC_ADDR 0x49100
/* This register maps to a ram with a depth of: 32 */
#define PIU_DLC_MMU_CSR_A_IOTSBDESC_POR_VALUE 0x0000000000000000
/* Register definitions from :/verif/env/dmu/vera/csrtool/eqs_a.csr_define.vri 1.1 */
#define PIU_DLC_IMU_EQS_CSR_A_EQ_BASE_ADDRESS_ADDR 0x10000
#define PIU_DLC_IMU_EQS_CSR_A_EQ_BASE_ADDRESS_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_EQS_CSR_A_EQ_CTRL_SET_ADDR 0x11000
/* This register maps to a ram with a depth of: 36 */
#define PIU_DLC_IMU_EQS_CSR_A_EQ_CTRL_SET_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_EQS_CSR_A_EQ_CTRL_CLR_ADDR 0x11200
/* This register maps to a ram with a depth of: 36 */
#define PIU_DLC_IMU_EQS_CSR_A_EQ_CTRL_CLR_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_EQS_CSR_A_EQ_STATE_ADDR 0x11400
/* This register maps to a ram with a depth of: 36 */
#define PIU_DLC_IMU_EQS_CSR_A_EQ_STATE_POR_VALUE 0x0000000000000001
#define PIU_DLC_IMU_EQS_CSR_A_EQ_TAIL_ADDR 0x11600
/* This register maps to a ram with a depth of: 36 */
#define PIU_DLC_IMU_EQS_CSR_A_EQ_TAIL_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_EQS_CSR_A_EQ_HEAD_ADDR 0x11800
/* This register maps to a ram with a depth of: 36 */
#define PIU_DLC_IMU_EQS_CSR_A_EQ_HEAD_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_EQS_EQ_CTRL_SET(n) (PIU_DLC_IMU_EQS_CSR_A_EQ_CTRL_SET_ADDR+(8*n))
#define PIU_DLC_IMU_EQS_EQ_CTRL_CLR(n) (PIU_DLC_IMU_EQS_CSR_A_EQ_CTRL_CLR_ADDR+(8*n))
#define PIU_DLC_IMU_EQS_EQ_STATE(n) (PIU_DLC_IMU_EQS_CSR_A_EQ_STATE_ADDR+(8*n))
#define PIU_DLC_IMU_EQS_EQ_TAIL(n) (PIU_DLC_IMU_EQS_CSR_A_EQ_TAIL_ADDR+(8*n))
#define PIU_DLC_IMU_EQS_EQ_HEAD(n) (PIU_DLC_IMU_EQS_CSR_A_EQ_HEAD_ADDR+(8*n))
#define PIU_DLC_IMU_RDS_MSI_MSI_MAPPING(n) (0x00020000+(8*n))
#define PIU_DLC_IMU_RDS_MSI_MSI_CLEAR_REG(n) (0x00028000+(8*n))
/* Register definitions from :/verif/env/dmu/vera/csrtool/ics_a.csr_define.vri 1.3 */
#define PIU_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_ADDR 0x31000
#define PIU_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_POR_VALUE 0x0000000000007fff
#define PIU_DLC_IMU_ICS_CSR_A_IMU_INT_EN_REG_ADDR 0x31008
#define PIU_DLC_IMU_ICS_CSR_A_IMU_INT_EN_REG_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_ADDR 0x31010
#define PIU_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_ADDR 0x31018
#define PIU_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_ADDR 0x31020
#define PIU_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_ADDR 0x31028
#define PIU_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_ICS_CSR_A_IMU_SCS_ERROR_LOG_REG_ADDR 0x31030
#define PIU_DLC_IMU_ICS_CSR_A_IMU_SCS_ERROR_LOG_REG_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_ICS_CSR_A_IMU_EQS_ERROR_LOG_REG_ADDR 0x31038
#define PIU_DLC_IMU_ICS_CSR_A_IMU_EQS_ERROR_LOG_REG_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_MASK_REG_ADDR 0x31800
#define PIU_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_MASK_REG_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_STATUS_REG_ADDR 0x31808
#define PIU_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_STATUS_REG_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_ICS_CSR_A_IMU_PERF_CNTRL_ADDR 0x32000
#define PIU_DLC_IMU_ICS_CSR_A_IMU_PERF_CNTRL_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT0_ADDR 0x32008
#define PIU_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT0_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT1_ADDR 0x32010
#define PIU_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT1_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_ICS_CSR_A_MSI_32_ADDR_REG_ADDR 0x34000
#define PIU_DLC_IMU_ICS_CSR_A_MSI_32_ADDR_REG_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_ICS_CSR_A_MSI_64_ADDR_REG_ADDR 0x34008
#define PIU_DLC_IMU_ICS_CSR_A_MSI_64_ADDR_REG_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_ADDR 0x34018
#define PIU_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_POR_VALUE 0x0000000000000000
/* Register definitions from :/verif/env/dmu/vera/csrtool/intx_a.csr_define.vri 1.1 */
#define PIU_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_ADDR 0x0b000
#define PIU_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_RDS_INTX_CSR_A_INT_A_INT_CLR_REG_ADDR 0x0b008
#define PIU_DLC_IMU_RDS_INTX_CSR_A_INT_A_INT_CLR_REG_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_RDS_INTX_CSR_A_INT_B_INT_CLR_REG_ADDR 0x0b010
#define PIU_DLC_IMU_RDS_INTX_CSR_A_INT_B_INT_CLR_REG_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_RDS_INTX_CSR_A_INT_C_INT_CLR_REG_ADDR 0x0b018
#define PIU_DLC_IMU_RDS_INTX_CSR_A_INT_C_INT_CLR_REG_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_RDS_INTX_CSR_A_INT_D_INT_CLR_REG_ADDR 0x0b020
#define PIU_DLC_IMU_RDS_INTX_CSR_A_INT_D_INT_CLR_REG_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_ISS_INTERRUPT_MAPPING(n) (0x00001000+(8*n))
#define PIU_DLC_IMU_ISS_CLR_INT_REG(n) (0x00001400+(8*n))
/* Register definitions from :/verif/env/dmu/vera/csrtool/iss_a.csr_define.vri 1.1 */
#define PIU_DLC_IMU_ISS_CSR_A_INTERRUPT_RETRY_TIMER_ADDR 0x01a00
#define PIU_DLC_IMU_ISS_CSR_A_INTERRUPT_RETRY_TIMER_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_1_ADDR 0x01a10
#define PIU_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_1_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_2_ADDR 0x01a18
#define PIU_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_2_POR_VALUE 0x0000000000000000
/* Register definitions from :/verif/env/dmu/vera/csrtool/mess_a.csr_define.vri 1.1 */
#define PIU_DLC_IMU_RDS_MESS_CSR_A_ERR_COR_MAPPING_ADDR 0x30000
#define PIU_DLC_IMU_RDS_MESS_CSR_A_ERR_COR_MAPPING_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_RDS_MESS_CSR_A_ERR_NONFATAL_MAPPING_ADDR 0x30008
#define PIU_DLC_IMU_RDS_MESS_CSR_A_ERR_NONFATAL_MAPPING_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_RDS_MESS_CSR_A_ERR_FATAL_MAPPING_ADDR 0x30010
#define PIU_DLC_IMU_RDS_MESS_CSR_A_ERR_FATAL_MAPPING_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_RDS_MESS_CSR_A_PM_PME_MAPPING_ADDR 0x30018
#define PIU_DLC_IMU_RDS_MESS_CSR_A_PM_PME_MAPPING_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_RDS_MESS_CSR_A_PME_TO_ACK_MAPPING_ADDR 0x30020
#define PIU_DLC_IMU_RDS_MESS_CSR_A_PME_TO_ACK_MAPPING_POR_VALUE 0x0000000000000000
/* Register definitions from :/verif/env/dmu/vera/csrtool/msi_a.csr_define.vri 1.1 */
#define PIU_DLC_IMU_RDS_MSI_CSR_A_MSI_MAPPING_ADDR 0x20000
/* This register maps to a ram with a depth of: 256 */
#define PIU_DLC_IMU_RDS_MSI_CSR_A_MSI_MAPPING_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1C_ALIAS_ADDR 0x28000
/* This register maps to a ram with a depth of: 256 */
#define PIU_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1C_ALIAS_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1S_ALIAS_ADDR 0x28800
/* This register maps to a ram with a depth of: 256 */
#define PIU_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1S_ALIAS_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_0_REG_ADDR 0x2c000
#define PIU_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_0_REG_POR_VALUE 0x0000000000000000
#define PIU_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_1_REG_ADDR 0x2c008
#define PIU_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_1_REG_POR_VALUE 0x0000000000000000
/* Register definitions from :/verif/env/dmu/vera/csrtool/psb_a.csr_define.vri 1.2 */
#define PIU_DLC_PSB_CSR_A_PSB_DMA_ADDR 0x60000
/* This register maps to a ram with a depth of: 32 */
#define PIU_DLC_PSB_CSR_A_PSB_DMA_POR_VALUE 0x0000000000000000
#define PIU_DLC_PSB_CSR_A_PSB_PIO_ADDR 0x64000
/* This register maps to a ram with a depth of: 16 */
#define PIU_DLC_PSB_CSR_A_PSB_PIO_POR_VALUE 0x0000000000000000
/* Register definitions from :/verif/env/dmu/vera/csrtool/tsb_a.csr_define.vri 1.2 */
#define PIU_DLC_TSB_CSR_A_TSB_DMA_ADDR 0x70000
/* This register maps to a ram with a depth of: 32 */
#define PIU_DLC_TSB_CSR_A_TSB_DMA_POR_VALUE 0x0000000000000000
#define PIU_DLC_TSB_CSR_A_TSB_STS_ADDR 0x70100
#define PIU_DLC_TSB_CSR_A_TSB_STS_POR_VALUE 0x0000000000000001
/* Register definitions from :/verif/env/ilu_peu/vera/csrtool/cib_a.csr_define.vri 1.8 */
#define PIU_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_ADDR 0x51000
#define PIU_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_POR_VALUE 0x00000000000000f0
#define PIU_DLC_ILU_CIB_CSR_A_ILU_INT_EN_ADDR 0x51008
#define PIU_DLC_ILU_CIB_CSR_A_ILU_INT_EN_POR_VALUE 0x0000000000000000
#define PIU_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_ADDR 0x51010
#define PIU_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_POR_VALUE 0x0000000000000000
#define PIU_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_ADDR 0x51018
#define PIU_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_POR_VALUE 0x0000000000000000
#define PIU_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_ADDR 0x51020
#define PIU_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_POR_VALUE 0x0000000000000000
#define PIU_DLC_ILU_CIB_CSR_A_PEC_INT_EN_ADDR 0x51800
#define PIU_DLC_ILU_CIB_CSR_A_PEC_INT_EN_POR_VALUE 0x0000000000000000
#define PIU_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_ADDR 0x51808
#define PIU_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_POR_VALUE 0x0000000000000000
#define PIU_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ADDR 0x52000
#define PIU_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_POR_VALUE 0x00000003ffff0000
/* Register definitions from :/verif/env/ilu_peu/vera/csrtool/tlr_a.csr_define.vri 1.15 */
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR 0x80000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_POR_VALUE 0x0000000000000101
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_STS_ADDR 0x80008
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_STS_POR_VALUE 0x0000000000000001
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TRN_OFF_ADDR 0x80010
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TRN_OFF_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_ICI_ADDR 0x80018
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_ICI_POR_VALUE 0x00000010000200c0
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_DIAG_ADDR 0x80100
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_DIAG_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_ECC_ADDR 0x80200
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_ECC_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_ADDR 0x80208
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_ECL_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_ERB_ADDR 0x80210
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_ERB_POR_VALUE 0x0000000000001000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_ICA_ADDR 0x80218
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_ICA_POR_VALUE 0x00000010000200c0
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_ICR_ADDR 0x80220
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_ICR_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_OE_LOG_ADDR 0x81000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_OE_LOG_POR_VALUE 0x0000000000ffffff
#define PIU_PLC_TLU_CTB_TLR_CSR_A_OE_INT_EN_ADDR 0x81008
#define PIU_PLC_TLU_CTB_TLR_CSR_A_OE_INT_EN_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR_ADDR 0x81010
#define PIU_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR 0x81018
#define PIU_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1S_ALIAS_ADDR 0x81020
#define PIU_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1S_ALIAS_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR1_ADDR 0x81028
#define PIU_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR1_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR2_ADDR 0x81030
#define PIU_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR2_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR1_ADDR 0x81038
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR1_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR2_ADDR 0x81040
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR2_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_PRFC_ADDR 0x82000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_PRFC_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF0_ADDR 0x82008
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF0_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF1_ADDR 0x82010
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF1_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF2_ADDR 0x82018
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF2_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_DBG_SEL_A_ADDR 0x83000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_DBG_SEL_A_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_DBG_SEL_B_ADDR 0x83008
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_DBG_SEL_B_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_DEV_CAP_ADDR 0x90000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_DEV_CAP_POR_VALUE 0x0000000000000002
#define PIU_PLC_TLU_CTB_TLR_CSR_A_DEV_CTL_ADDR 0x90008
#define PIU_PLC_TLU_CTB_TLR_CSR_A_DEV_CTL_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_DEV_STS_ADDR 0x90010
#define PIU_PLC_TLU_CTB_TLR_CSR_A_DEV_STS_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_LNK_CAP_ADDR 0x90018
#define PIU_PLC_TLU_CTB_TLR_CSR_A_LNK_CAP_POR_VALUE 0x0000000000014c81
#define PIU_PLC_TLU_CTB_TLR_CSR_A_LNK_CTL_ADDR 0x90020
#define PIU_PLC_TLU_CTB_TLR_CSR_A_LNK_CTL_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_ADDR 0x90028
#define PIU_PLC_TLU_CTB_TLR_CSR_A_LNK_STS_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_SLT_CAP_ADDR 0x90030
#define PIU_PLC_TLU_CTB_TLR_CSR_A_SLT_CAP_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_UE_LOG_ADDR 0x91000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_UE_LOG_POR_VALUE 0x000000000017f011
#define PIU_PLC_TLU_CTB_TLR_CSR_A_UE_INT_EN_ADDR 0x91008
#define PIU_PLC_TLU_CTB_TLR_CSR_A_UE_INT_EN_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_UE_EN_ERR_ADDR 0x91010
#define PIU_PLC_TLU_CTB_TLR_CSR_A_UE_EN_ERR_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1C_ALIAS_ADDR 0x91018
#define PIU_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1C_ALIAS_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1S_ALIAS_ADDR 0x91020
#define PIU_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1S_ALIAS_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR1_ADDR 0x91028
#define PIU_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR1_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR2_ADDR 0x91030
#define PIU_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR2_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR1_ADDR 0x91038
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR1_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR2_ADDR 0x91040
#define PIU_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR2_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_CE_LOG_ADDR 0xa1000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_CE_LOG_POR_VALUE 0x00000000000011c1
#define PIU_PLC_TLU_CTB_TLR_CSR_A_CE_INT_EN_ADDR 0xa1008
#define PIU_PLC_TLU_CTB_TLR_CSR_A_CE_INT_EN_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_CE_EN_ERR_ADDR 0xa1010
#define PIU_PLC_TLU_CTB_TLR_CSR_A_CE_EN_ERR_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1C_ALIAS_ADDR 0xa1018
#define PIU_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1C_ALIAS_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1S_ALIAS_ADDR 0xa1020
#define PIU_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1S_ALIAS_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_PEU_CXPL_SERDES_REV_ADDR 0xe2000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_PEU_CXPL_SERDES_REV_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_ACKNAK_THRESH_ADDR 0xe2008
#define PIU_PLC_TLU_CTB_TLR_CSR_A_ACKNAK_THRESH_POR_VALUE 0x0000000000000043
#define PIU_PLC_TLU_CTB_TLR_CSR_A_ACKNAK_TIMER_ADDR 0xe2010
#define PIU_PLC_TLU_CTB_TLR_CSR_A_ACKNAK_TIMER_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_REPLAY_TIM_THRESH_ADDR 0xe2018
#define PIU_PLC_TLU_CTB_TLR_CSR_A_REPLAY_TIM_THRESH_POR_VALUE 0x00000000000000fc
#define PIU_PLC_TLU_CTB_TLR_CSR_A_REPLAY_TIMER_ADDR 0xe2020
#define PIU_PLC_TLU_CTB_TLR_CSR_A_REPLAY_TIMER_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_VEN_DLLP_MSG_ADDR 0xe2040
#define PIU_PLC_TLU_CTB_TLR_CSR_A_VEN_DLLP_MSG_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_FORCE_LTSSM_ADDR 0xe2050
#define PIU_PLC_TLU_CTB_TLR_CSR_A_FORCE_LTSSM_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_LINK_CFG_ADDR 0xe2058
#define PIU_PLC_TLU_CTB_TLR_CSR_A_LINK_CFG_POR_VALUE 0x0000000000000101
#define PIU_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_ADDR 0xe2060
#define PIU_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_POR_VALUE 0x00000000001b0800
#define PIU_PLC_TLU_CTB_TLR_CSR_A_LANE_SKEW_ADDR 0xe2068
#define PIU_PLC_TLU_CTB_TLR_CSR_A_LANE_SKEW_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_SYMBOL_NUM_ADDR 0xe2070
#define PIU_PLC_TLU_CTB_TLR_CSR_A_SYMBOL_NUM_POR_VALUE 0x00000000000033aa
#define PIU_PLC_TLU_CTB_TLR_CSR_A_SYMBOL_TIMER_ADDR 0xe2078
#define PIU_PLC_TLU_CTB_TLR_CSR_A_SYMBOL_TIMER_POR_VALUE 0x0000000000000500
#define PIU_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_ADDR 0xe2100
#define PIU_PLC_TLU_CTB_TLR_CSR_A_CORE_STATUS_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_LOG_EN_ADDR 0xe2108
#define PIU_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_LOG_EN_POR_VALUE 0x000000000f03ffff
#define PIU_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_EN_ADDR 0xe2110
#define PIU_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_EN_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_STS_ADDR 0xe2118
#define PIU_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_STS_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ADDR 0xe2120
#define PIU_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1S_ALIAS_ADDR 0xe2128
#define PIU_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1S_ALIAS_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_LNK_BIT_ERR_CNT_1_ADDR 0xe2130
#define PIU_PLC_TLU_CTB_TLR_CSR_A_LNK_BIT_ERR_CNT_1_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_LNK_BIT_ERR_CNT_2_ADDR 0xe2138
#define PIU_PLC_TLU_CTB_TLR_CSR_A_LNK_BIT_ERR_CNT_2_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_SERDES_PLL_ADDR 0xe2200
#define PIU_PLC_TLU_CTB_TLR_CSR_A_SERDES_PLL_POR_VALUE 0x0000000000000001
#define PIU_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_ADDR 0xe2300
/* This register maps to a ram with a depth of: 8 */
#define PIU_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_CTL_POR_VALUE 0x0000000000000552
#define PIU_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_STATUS_ADDR 0xe2380
/* This register maps to a ram with a depth of: 8 */
#define PIU_PLC_TLU_CTB_TLR_CSR_A_SERDES_RECEIVER_LANE_STATUS_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_ADDR 0xe2400
/* This register maps to a ram with a depth of: 8 */
#define PIU_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_CTL_POR_VALUE 0x00000000000001ec
#define PIU_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_STATUS_ADDR 0xe2480
/* This register maps to a ram with a depth of: 8 */
#define PIU_PLC_TLU_CTB_TLR_CSR_A_SERDES_XMITTER_LANE_STATUS_POR_VALUE 0x0000000000000000
#define PIU_PLC_TLU_CTB_TLR_CSR_A_SERDES_MACRO_TEST_CFG_ADDR 0xe2500
/* This register maps to a ram with a depth of: 2 */
#define PIU_PLC_TLU_CTB_TLR_CSR_A_SERDES_MACRO_TEST_CFG_POR_VALUE 0x0000000000000003
* Interrupt Mapping Registers
* NOTE - There are 2 interrupt mapping/clear registers "missing" in N2!
* These are for mondo's 60 and 61. There the two register
* at (40 * PCI_E_INT_xxx_STEP) + PCI_E_INT_xxx_ADDR
* and (41 * PCI_E_INT_xxx_STEP) + PCI_E_INT_xxx_ADDR
* don't exist. The PCI_E_INT_MAP_COUNT = 40 to make loops
* simplier, BUT it does include that last two registers
* for which seperate offsets are defined here.
#define PCI_E_INT_MAP_ADDR PIU_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_20_ADDR
#define PCI_E_INT_MAP_STEP 8
#define PCI_E_INT_MAP_COUNT 40
#define PCI_E_INT_MAP_MONDO_62_OFFSET (42 * PCI_E_INT_MAP_STEP)
#define PCI_E_INT_MAP_MONDO_63_OFFSET (43 * PCI_E_INT_MAP_STEP)
#define PCI_E_INT_MAP_MDO_MODE_SHIFT 63
#define PCI_E_INT_MAP_V_SHIFT 31
#define PCI_E_INT_MAP_THREADID_SHIFT 25
#define PCI_E_INT_MAP_INT_CNTRL_NUM_SHIFT 6
#define PCI_E_INT_CLEAR_ADDR PIU_DLC_IMU_ISS_CSR_A_CLR_INT_REG_20_ADDR
#define PCI_E_INT_CLEAR_STEP 8
#define PCI_E_INT_CLEAR_COUNT 40
#define PCI_E_INT_CLEAR_MONDO_62_OFFSET (42 * PCI_E_INT_CLEAR_STEP)
#define PCI_E_INT_CLEAR_MONDO_63_OFFSET (43 * PCI_E_INT_CLEAR_STEP)
#define PCI_E_INT_RETRY_TIMER_ADDR PIU_DLC_IMU_ISS_CSR_A_INTERRUPT_RETRY_TIMER_ADDR
#define PCI_E_INT_STATE_STATUS_1_ADDR PIU_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_1_ADDR
#define PCI_E_INT_STATE_STATUS_2_ADDR PIU_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_2_ADDR
#define PCI_E_INTX_STATUS_ADDR PIU_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_ADDR
#define PCI_E_INT_A_CLEAR_ADDR PIU_DLC_IMU_RDS_INTX_CSR_A_INT_A_INT_CLR_REG_ADDR
#define PCI_E_INT_B_CLEAR_ADDR PIU_DLC_IMU_RDS_INTX_CSR_A_INT_B_INT_CLR_REG_ADDR
#define PCI_E_INT_C_CLEAR_ADDR PIU_DLC_IMU_RDS_INTX_CSR_A_INT_C_INT_CLR_REG_ADDR
#define PCI_E_INT_D_CLEAR_ADDR PIU_DLC_IMU_RDS_INTX_CSR_A_INT_D_INT_CLR_REG_ADDR
#define PCI_E_EV_QUE_BASE_ADDRESS_ADDR PIU_DLC_IMU_EQS_CSR_A_EQ_BASE_ADDRESS_ADDR
#define PCI_E_EV_QUE_CTL_SET_ADDR PIU_DLC_IMU_EQS_CSR_A_EQ_CTRL_SET_ADDR
#define PCI_E_EV_QUE_CTL_SET_COUNT 36
#define PCI_E_EV_QUE_CTL_SET_STEP 8
#define PCI_E_EV_QUE_CTL_CLEAR_ADDR PIU_DLC_IMU_EQS_CSR_A_EQ_CTRL_CLR_ADDR
#define PCI_E_EV_QUE_CTL_CLEAR_COUNT 36
#define PCI_E_EV_QUE_CTL_CLEAR_STEP 8
#define PCI_E_EV_QUE_STATE_ADDR PIU_DLC_IMU_EQS_CSR_A_EQ_STATE_ADDR
#define PCI_E_EV_QUE_STATE_COUNT 36
#define PCI_E_EV_QUE_STATE_STEP 8
#define PCI_E_EV_QUE_TAIL_ADDR PIU_DLC_IMU_EQS_CSR_A_EQ_TAIL_ADDR
#define PCI_E_EV_QUE_TAIL_COUNT 36
#define PCI_E_EV_QUE_TAIL_STEP 8
#define PCI_E_EV_QUE_HEAD_ADDR PIU_DLC_IMU_EQS_CSR_A_EQ_HEAD_ADDR
#define PCI_E_EV_QUE_HEAD_COUNT 36
#define PCI_E_EV_QUE_HEAD_STEP 8
#define PCI_E_MSI_MAP_ADDR PIU_DLC_IMU_RDS_MSI_CSR_A_MSI_MAPPING_ADDR
#define PCI_E_MSI_MAP_COUNT 256
#define PCI_E_MSI_MAP_STEP 8
#define PCI_E_MSI_CLEAR_ADDR PIU_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1C_ALIAS_ADDR
#define PCI_E_MSI_CLEAR_COUNT 256
#define PCI_E_MSI_CLEAR_STEP 8
#define PCI_E_INT_MONDO_DATA_0_ADDR PIU_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_0_REG_ADDR
#define PCI_E_INT_MONDO_DATA_1_ADDR PIU_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_1_REG_ADDR
#define PCI_E_ERR_COR_MAP_ADDR PIU_DLC_IMU_RDS_MESS_CSR_A_ERR_COR_MAPPING_ADDR
#define PCI_E_ERR_NONFATAL_MAP_ADDR PIU_DLC_IMU_RDS_MESS_CSR_A_ERR_NONFATAL_MAPPING_ADDR
#define PCI_E_ERR_FATAL_MAP_ADDR PIU_DLC_IMU_RDS_MESS_CSR_A_ERR_FATAL_MAPPING_ADDR
#define PCI_E_PM_PME_MAP_ADDR PIU_DLC_IMU_RDS_MESS_CSR_A_PM_PME_MAPPING_ADDR
#define PCI_E_PME_ACK_MAP_ADDR PIU_DLC_IMU_RDS_MESS_CSR_A_PME_TO_ACK_MAPPING_ADDR
! IMU Interrupt Enable Register
! IMU Interrupt Status Register
! IMU Error Status Clear Register
! IMU Error Status Set Register
#define PCI_E_IMU_INT_ENB_ADDR PIU_DLC_IMU_ICS_CSR_A_IMU_INT_EN_REG_ADDR
#define PCI_E_IMU_INT_STAT_ADDR PIU_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_ADDR
#define PCI_E_IMU_ERR_STAT_CLR_ADDR PIU_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_ADDR
#define PCI_E_IMU_ERR_STAT_SET_ADDR PIU_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_ADDR
#define PCI_E_IMU_INT_EN_SPARE_S_SHIFT 42
#define PCI_E_IMU_INT_EN_SPARE_P_SHIFT 10
#define PCI_E_IMU_INT_EN_EQ_OVER_S_SHIFT 41
#define PCI_E_IMU_INT_EN_EQ_OVER_P_SHIFT 9
#define PCI_E_IMU_INT_EN_EQ_NOT_EN_S_SHIFT 40
#define PCI_E_IMU_INT_EN_EQ_NOT_EN_P_SHIFT 8
#define PCI_E_IMU_INT_EN_MSI_MAL_ERR_S_SHIFT 39
#define PCI_E_IMU_INT_EN_MSI_MAL_ERR_P_SHIFT 7
#define PCI_E_IMU_INT_EN_MSI_PAR_ERR_S_SHIFT 38
#define PCI_E_IMU_INT_EN_MSI_PAR_ERR_P_SHIFT 6
#define PCI_E_IMU_INT_EN_PMEACK_MES_NOT_EN_S_SHIFT 37
#define PCI_E_IMU_INT_EN_PMEACK_MES_NOT_EN_P_SHIFT 5
#define PCI_E_IMU_INT_EN_PMPME_MES_NOT_EN_S_SHIFT 36
#define PCI_E_IMU_INT_EN_PMPME_MES_NOT_EN_P_SHIFT 4
#define PCI_E_IMU_INT_EN_FATAL_MES_NOT_EN_S_SHIFT 35
#define PCI_E_IMU_INT_EN_FATAL_MES_NOT_EN_P_SHIFT 3
#define PCI_E_IMU_INT_EN_NONFATAL_MES_NOT_EN_S_SHIFT 34
#define PCI_E_IMU_INT_EN_NONFATAL_MES_NOT_EN_P_SHIFT 2
#define PCI_E_IMU_INT_EN_COR_MES_NOT_EN_S_SHIFT 33
#define PCI_E_IMU_INT_EN_COR_MES_NOT_EN_P_SHIFT 1
#define PCI_E_IMU_INT_EN_MSI_NOT_EN_S_SHIFT 32
#define PCI_E_IMU_INT_EN_MSI_NOT_EN_P_SHIFT 0
/* DMU Core and Block Interrupt Enable Register */
#define PCI_E_DMU_CORE_BLK_INT_ENB_ADDR PIU_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_MASK_REG_ADDR
#define PCI_E_DMU_INT_ENB_ADDR PIU_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_MASK_REG_ADDR
#define PCI_E_DMU_CORE_BLK_INT_EN_DMC_SHIFT 63
#define PCI_E_DMU_CORE_BLK_INT_EN_DMC_MASK 0x8000000000000000
#define PCI_E_DMU_CORE_BLK_INT_EN_DEBUG_TRIG_EN_SHIFT 62
#define PCI_E_DMU_CORE_BLK_INT_EN_DEBUG_TRIG_EN_MASK 0x4000000000000000
#define PCI_E_DMU_CORE_BLK_INT_EN_MMU_SHIFT 1
#define PCI_E_DMU_CORE_BLK_INT_EN_MMU_MASK 0x2
#define PCI_E_DMU_CORE_BLK_INT_EN_IMU_SHIFT 0
#define PCI_E_DMU_CORE_BLK_INT_EN_IMU_MASK 0x1
/* DMU Core and Block Error Status Register */
#define PCI_E_DMU_CORE_BLK_ERR_STAT_ADDR PIU_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_STATUS_REG_ADDR
#define PCI_E_DMU_ERR_STAT_ADDR PIU_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_STATUS_REG_ADDR
#define PCI_E_DMU_CORE_BLK_ERR_STAT_MMU_SHIFT 1
#define PCI_E_DMU_CORE_BLK_ERR_STAT_MMU_MASK 0x2
#define PCI_E_DMU_CORE_BLK_ERR_STAT_IMU_SHIFT 0
#define PCI_E_DMU_CORE_BLK_ERR_STAT_IMU_MASK 0x1
/* MSI 32 Bit Address Register */
#define PCI_E_MSI_32_ADDRESS_ADDR PIU_DLC_IMU_ICS_CSR_A_MSI_32_ADDR_REG_ADDR
#define PCI_E_MSI_64_ADDRESS_ADDR PIU_DLC_IMU_ICS_CSR_A_MSI_64_ADDR_REG_ADDR
! MMU Interrupt Enable Register
! MMU Interrupt Status Register
! MMU Error Status Clear Register
! MMU Error Status Set Register
#define PCI_E_MMU_INT_ENB_ADDR PIU_DLC_MMU_CSR_A_INT_EN_ADDR
#define PCI_E_MMU_INT_STAT_ADDR PIU_DLC_MMU_CSR_A_EN_ERR_ADDR
#define PCI_E_MMU_ERR_STAT_CL_ADDR PIU_DLC_MMU_CSR_A_ERR_RW1C_ALIAS_ADDR
#define PCI_E_MMU_ERR_STAT_SET_ADDR PIU_DLC_MMU_CSR_A_ERR_RW1S_ALIAS_ADDR
#define PCI_E_MMU_TRANS_FAULT_ADDR PIU_DLC_MMU_CSR_A_FLTA_ADDR
#define PCI_E_MMU_INT_EN_SUN4V_KEY_ERR_S_SHIFT 52
#define PCI_E_MMU_INT_EN_SUN4V_KEY_ERR_P_SHIFT 20
#define PCI_E_MMU_INT_EN_SUN4V_VA_ADI_UF_S_SHIFT 51
#define PCI_E_MMU_INT_EN_SUN4V_VA_ADI_UF_P_SHIFT 19
#define PCI_E_MMU_INT_EN_SUN4V_VA_OOR_S_SHIFT 50
#define PCI_E_MMU_INT_EN_SUN4V_VA_OOR_P_SHIFT 18
#define PCI_E_MMU_INT_EN_IOTSBDESC_DPE_S_SHIFT 49
#define PCI_E_MMU_INT_EN_IOTSBDESC_DPE_P_SHIFT 17
#define PCI_E_MMU_INT_EN_IOTSBDESC_INV_S_SHIFT 48
#define PCI_E_MMU_INT_EN_IOTSBDESC_INV_P_SHIFT 16
#define PCI_E_MMU_INT_EN_TBW_DPE_S_SHIFT 47
#define PCI_E_MMU_INT_EN_TBW_DPE_P_SHIFT 15
#define PCI_E_MMU_INT_EN_TBW_ERR_S_SHIFT 46
#define PCI_E_MMU_INT_EN_TBW_ERR_P_SHIFT 14
#define PCI_E_MMU_INT_EN_TBW_UDE_S_SHIFT 45
#define PCI_E_MMU_INT_EN_TBW_UDE_P_SHIFT 13
#define PCI_E_MMU_INT_EN_TBW_DME_S_SHIFT 44
#define PCI_E_MMU_INT_EN_TBW_DME_P_SHIFT 12
#define PCI_E_MMU_INT_EN_SPARE3_S_SHIFT 43
#define PCI_E_MMU_INT_EN_SPARE3_P_SHIFT 11
#define PCI_E_MMU_INT_EN_SPARE2_S_SHIFT 42
#define PCI_E_MMU_INT_EN_SPARE2_P_SHIFT 10
#define PCI_E_MMU_INT_EN_TTC_CAE_S_SHIFT 41
#define PCI_E_MMU_INT_EN_TTC_CAE_P_SHIFT 9
#define PCI_E_MMU_INT_EN_TTC_DPE_S_SHIFT 40
#define PCI_E_MMU_INT_EN_TTC_DPE_P_SHIFT 8
#define PCI_E_MMU_INT_EN_TTE_PRT_S_SHIFT 39
#define PCI_E_MMU_INT_EN_TTE_PRT_P_SHIFT 7
#define PCI_E_MMU_INT_EN_TTE_INV_S_SHIFT 38
#define PCI_E_MMU_INT_EN_TTE_INV_P_SHIFT 6
#define PCI_E_MMU_INT_EN_TRN_OOR_S_SHIFT 37
#define PCI_E_MMU_INT_EN_TRN_OOR_P_SHIFT 5
#define PCI_E_MMU_INT_EN_TRN_ERR_S_SHIFT 36
#define PCI_E_MMU_INT_EN_TRN_ERR_P_SHIFT 4
#define PCI_E_MMU_INT_EN_SPARE1_S_SHIFT 35
#define PCI_E_MMU_INT_EN_SPARE1_P_SHIFT 3
#define PCI_E_MMU_INT_EN_SPARE0_S_SHIFT 34
#define PCI_E_MMU_INT_EN_SPARE0_P_SHIFT 2
#define PCI_E_MMU_INT_EN_BYP_OOR_S_SHIFT 33
#define PCI_E_MMU_INT_EN_BYP_OOR_P_SHIFT 1
#define PCI_E_MMU_INT_EN_BYP_ERR_S_SHIFT 32
#define PCI_E_MMU_INT_EN_BYP_ERR_P_SHIFT 0
#define PCI_E_ILU_INT_ENB_ADDR PIU_DLC_ILU_CIB_CSR_A_ILU_INT_EN_ADDR
#define PCI_E_ILU_INT_STAT_ADDR PIU_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_ADDR
#define PCI_E_ILU_ERR_STAT_CL_ADDR PIU_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_ADDR
#define PCI_E_ILU_ERR_STAT_SET_ADDR PIU_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_ADDR
#define PCI_E_PEU_INT_ENB_ADDR PIU_DLC_ILU_CIB_CSR_A_PEC_INT_EN_ADDR
#define PCI_E_PEU_INT_STAT_ADDR PIU_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_ADDR
#define PCI_E_PEU_OTHER_LOG_ENB_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_OE_LOG_ADDR
#define PCI_E_PEU_OTHER_INT_ENB_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_OE_INT_EN_ADDR
#define PCI_E_PEU_OTHER_INT_STAT_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR_ADDR
#define PCI_E_PEU_OTHER_ERR_STAT_CL_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR
#define PCI_E_PEU_OTHER_ERR_STAT_SET_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1S_ALIAS_ADDR
#define PCI_E_PEU_ROE_HDR1_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR1_ADDR
#define PCI_E_PEU_ROE_HDR2_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_ROE_HDR2_ADDR
#define PCI_E_PEU_TOE_HDR1_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR1_ADDR
#define PCI_E_PEU_TOE_HDR2_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_TOE_HDR2_ADDR
#define PCI_E_PEU_UE_INT_ENB_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_UE_INT_EN_ADDR
#define PCI_E_PEU_UE_INT_STAT_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_UE_EN_ERR_ADDR
#define PCI_E_PEU_UE_STAT_CL_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1C_ALIAS_ADDR
#define PCI_E_PEU_UE_STAT_SET_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1S_ALIAS_ADDR
#define PCI_E_PEU_RUE_HDR1_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR1_ADDR
#define PCI_E_PEU_RUE_HDR2_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_RUE_HDR2_ADDR
#define PCI_E_PEU_TUE_HDR1_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR1_ADDR
#define PCI_E_PEU_TUE_HDR2_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_TUE_HDR2_ADDR
#define PCI_E_PEU_CE_INT_ENB_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_CE_INT_EN_ADDR
#define PCI_E_PEU_CE_INT_STAT_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_CE_EN_ERR_ADDR
#define PCI_E_PEU_CE_STAT_CL_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1C_ALIAS_ADDR
#define PCI_E_PEU_CE_STAT_SET_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1S_ALIAS_ADDR
#define PCI_E_PEU_CXPL_LOG_ENB_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_LOG_EN_ADDR
#define PCI_E_PEU_CXPL_INT_ENB_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_EN_ADDR
#define PCI_E_PEU_CXPL_INT_STAT_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_INT_STS_ADDR
#define PCI_E_PEU_CXPL_STAT_CL_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ADDR
#define PCI_E_PEU_CXPL_STAT_SET_ADDR PIU_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1S_ALIAS_ADDR
#define PIU_DLC_MMU_CTL PIU_DLC_MMU_CSR_A_CTL_ADDR
#define PIU_DLC_IMU_RDS_MESS_ERR_COR_MAPPING PIU_DLC_IMU_RDS_MESS_CSR_A_ERR_COR_MAPPING_ADDR
#define PIU_DLC_ILU_CIB_PEC_EN_ERR PIU_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_ADDR
#define PIU_DLC_IMU_ICS_IMU_PERF_CNT0 PIU_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT0_ADDR
#define PIU_DLC_IMU_ICS_IMU_PERF_CNT1 PIU_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT1_ADDR
#define PIU_DLC_IMU_RDS_MSI_INT_MONDO_DATA_0_REG PIU_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_0_REG_ADDR
#define PIU_DLC_IMU_RDS_MSI_INT_MONDO_DATA_1_REG PIU_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_1_REG_ADDR
#define PIU_PLC_TLU_CTB_TLR_TLU_PRF0 PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF0_ADDR
#define PIU_PLC_TLU_CTB_TLR_TLU_PRF1 PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF1_ADDR
#define PIU_PLC_TLU_CTB_TLR_TLU_PRF2 PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_PRF2_ADDR
#define PIU_PLC_TLU_CTB_TLR_TLU_PRFC PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_PRFC_ADDR
#define PIU_DLC_IMU_ICS_IMU_EQS_ERROR_LOG_REG PIU_DLC_IMU_ICS_CSR_A_IMU_EQS_ERROR_LOG_REG_ADDR
#define PIU_PLC_TLU_CTB_TLR_UE_ERR_RW1C_ALIAS PIU_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1C_ALIAS_ADDR
#define PIU_DLC_IMU_ICS_IMU_PERF_CNTRL PIU_DLC_IMU_ICS_CSR_A_IMU_PERF_CNTRL_ADDR
#define PIU_PLC_TLU_CTB_TLR_UE_ERR_RW1S_ALIAS PIU_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1S_ALIAS_ADDR
#define PIU_PLC_TLU_CTB_TLR_CE_ERR_RW1C_ALIAS PIU_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1C_ALIAS_ADDR
#define PIU_PLC_TLU_CTB_TLR_CE_ERR_RW1S_ALIAS PIU_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1S_ALIAS_ADDR
#define PIU_DLC_MMU_PRFC PIU_DLC_MMU_CSR_A_PRFC_ADDR
#define PIU_DLC_MMU_PRF0 PIU_DLC_MMU_CSR_A_PRF0_ADDR
#define PIU_DLC_MMU_PRF1 PIU_DLC_MMU_CSR_A_PRF1_ADDR
#define PIU_DLC_IMU_ICS_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS \
PIU_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_ADDR
#define PIU_DLC_CRU_DMC_DBG_SEL_A_REG PIU_DLC_CRU_CSR_A_DMC_DBG_SEL_A_REG_ADDR
#define PIU_DLC_CRU_DMC_DBG_SEL_B_REG PIU_DLC_CRU_CSR_A_DMC_DBG_SEL_B_REG_ADDR
#define PIU_DLC_IMU_ICS_IMU_PERF_CNTRL PIU_DLC_IMU_ICS_CSR_A_IMU_PERF_CNTRL_ADDR
#define PIU_DLC_IMU_ICS_IMU_INT_EN_REG PIU_DLC_IMU_ICS_CSR_A_IMU_INT_EN_REG_ADDR
#define PIU_PLC_TLU_CTB_TLR_LNK_CTL PIU_PLC_TLU_CTB_TLR_CSR_A_LNK_CTL_ADDR
#define PIU_PLC_TLU_CTB_TLR_OE_EN_ERR PIU_PLC_TLU_CTB_TLR_CSR_A_OE_EN_ERR_ADDR
#define PIU_PLC_TLU_CTB_TLR_CE_INT_EN PIU_PLC_TLU_CTB_TLR_CSR_A_CE_INT_EN_ADDR
#define PIU_PLC_TLU_CTB_TLR_OE_INT_EN PIU_PLC_TLU_CTB_TLR_CSR_A_OE_INT_EN_ADDR
#define PIU_PLC_TLU_CTB_TLR_UE_INT_EN PIU_PLC_TLU_CTB_TLR_CSR_A_UE_INT_EN_ADDR
#define PIU_PLC_TLU_CTB_TLR_OE_ERR_RW1C_ALIAS PIU_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ADDR
#define PIU_PLC_TLU_CTB_TLR_CE_LOG PIU_PLC_TLU_CTB_TLR_CSR_A_CE_LOG_ADDR
#define PIU_DLC_MMU_INT_EN PIU_DLC_MMU_CSR_A_INT_EN_ADDR
#define PIU_PLC_TLU_CTB_TLR_OE_LOG PIU_PLC_TLU_CTB_TLR_CSR_A_OE_LOG_ADDR
#define PIU_DLC_MMU_INV PIU_DLC_MMU_CSR_A_INV_ADDR
#define PIU_DLC_MMU_TSB PIU_DLC_MMU_CSR_A_TSB_ADDR
#define PIU_DLC_IMU_EQS_EQ_BASE_ADDRESS PIU_DLC_IMU_EQS_CSR_A_EQ_BASE_ADDRESS_ADDR
#define PIU_DLC_ILU_CIB_ILU_INT_EN PIU_DLC_ILU_CIB_CSR_A_ILU_INT_EN_ADDR
#define PIU_DLC_ILU_CIB_PEC_INT_EN PIU_DLC_ILU_CIB_CSR_A_PEC_INT_EN_ADDR
#define PIU_DLC_ILU_CIB_ILU_LOG_EN PIU_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_ADDR
#define PIU_DLC_IMU_ICS_DMC_INTERRUPT_MASK_REG PIU_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_MASK_REG_ADDR
#define PIU_PLC_TLU_CTB_TLR_DEV_CTL PIU_PLC_TLU_CTB_TLR_CSR_A_DEV_CTL_ADDR
#define PIU_DLC_IMU_ICS_IMU_ERROR_LOG_EN_REG PIU_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_ADDR
#define PIU_PLC_TLU_CTB_TLR_TLU_CTL PIU_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR
#define PIU_DLC_IMU_ICS_MSI_32_ADDR_REG PIU_DLC_IMU_ICS_CSR_A_MSI_32_ADDR_REG_ADDR
#define PIU_DLC_IMU_ICS_MSI_64_ADDR_REG PIU_DLC_IMU_ICS_CSR_A_MSI_64_ADDR_REG_ADDR
#define PIU_PLC_TLU_CTB_TLR_UE_LOG PIU_PLC_TLU_CTB_TLR_CSR_A_UE_LOG_ADDR
#define PIU_PCIE_A_MEM32_OFFSET_BASE 0x00002000
#define PIU_PCIE_A_MEM32_OFFSET_MASK 0x00002008
#define PIU_PCIE_A_IOCON_OFFSET_BASE 0x00002020
#define PIU_PCIE_A_IOCON_OFFSET_MASK 0x00002028
#define PIU_PCIE_A_MEM64_OFFSET_BASE 0x00002010
#define PIU_PCIE_A_MEM64_OFFSET_MASK 0x00002018
#define NCU_MMU_TTE_CACHE_FLUSH_ADDR_OFFSET 0x00002030
projects / OpenSPARC-T2-SAM / blob