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* Hypervisor Software File: cpu_errs.s
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.ident "@(#)cpu_errs.s 1.82 07/05/03 SMI"
#include <sys/asm_linkage.h>
#include <sparcv9/misc.h>
#include <sun4v/errs_defs.h>
#include <cpu_errs_defs.h>
* HW issues err. HV attempts to handle the error where appropiate.
* HV translates it to a sun4v format. Sends it to the queue.
* Macro that calls the function to dump the L2$ set diagnostic
* data into the error report.
* arg1 MUST be specified as %g1, used as arg1 to function
* arg2 MUST be specified as %g2, used as arg2 to function
* ret7 MUST be specified as %g7, used for return address
* scr1 is scratch register
#define ASMCALL_DUMP_L2_DATA_FOR_CE(arg1, arg2, scr1, ret7) \
add scr1, STRAND_CE_RPT, arg2 /* set %g2 to ce_rpt pointer */ ;\
add arg2, STRAND_EVBSC_L2_AFAR(0), arg1 ;\
ldx [arg1], arg1 /* %g1 has physical address */ ;\
ba dump_l2_set_tag_data_ecc ;\
#define SET_CPU_IN_ERROR(scr1, scr2) \
VCPU_STRUCT(scr1) /* FIXME: or strand? */ ;\
mov CPU_STATE_ERROR, scr2 ;\
stx scr2, [scr1 + CPU_STATUS]
* Queue the UE error report as a resumable error to the guest
#define ASMCALL_RQ_ERPT(E_OFFT, reg1, reg2, reg3, reg4, reg5, reg6, reg7)\
PRINT("queue RESUMABLE\r\n") ;\
add reg1, E_OFFT, reg2 /* erpt buf ptr */ ;\
ba queue_resumable_erpt /* %g1 = strand, %g2 = erpt */ ;\
* The erpt pointer should be passed in %g6 as %g6 is preserved across
* print routines. The second argument, reg1, should be %g1, which is
* used as the argument to PRINTX.
* %g6 - as erpt - pointer to the strand error buffer
* all registers are used.
#define CONSOLE_PRINT_DIAG_ERPT(erpt, reg1) \
ldx [erpt + STRAND_VBSC_ERPT + EVBSC_EHDL], reg1 /* ehdl */ ;\
ldx [erpt + STRAND_VBSC_ERPT + EVBSC_STICK], reg1 /* stick */ ;\
ldx [erpt + STRAND_VBSC_ERPT + EVBSC_CPUVER], reg1 /* cpuver */;\
PRINT("sparc_afsr = ") ;\
ldx [erpt + STRAND_VBSC_ERPT + EVBSC_SPARC_AFSR], reg1 /* sparc afsr */;\
PRINT("sparc_afar = ") ;\
ldx [erpt + STRAND_VBSC_ERPT + EVBSC_SPARC_AFAR], reg1 /* sparc afar */;\
PRINT("jbus_err_log = ") ;\
ldx [erpt + STRAND_VBSC_ERPT + EVBSC_JBI_ERR_LOG], reg1 ;\
ldx [erpt + STRAND_EVBSC_L2_AFSR(0)], reg1 ;\
ldx [erpt + STRAND_EVBSC_L2_AFSR(1)], reg1 ;\
ldx [erpt + STRAND_EVBSC_L2_AFSR(2)], reg1 ;\
ldx [erpt + STRAND_EVBSC_L2_AFSR(3)], reg1 ;\
ldx [erpt + STRAND_EVBSC_L2_AFAR(0)], reg1 ;\
ldx [erpt + STRAND_EVBSC_L2_AFAR(1)], reg1 ;\
ldx [erpt + STRAND_EVBSC_L2_AFAR(2)], reg1 ;\
ldx [erpt + STRAND_EVBSC_L2_AFAR(3)], reg1 ;\
PRINT("DRAM ESRs\r\n") ;\
ldx [erpt + STRAND_EVBSC_DRAM_AFSR(0)], reg1 ;\
ldx [erpt + STRAND_EVBSC_DRAM_AFSR(1)], reg1 ;\
ldx [erpt + STRAND_EVBSC_DRAM_AFSR(2)], reg1 ;\
ldx [erpt + STRAND_EVBSC_DRAM_AFSR(3)], reg1 ;\
PRINT("DRAM EARs\r\n") ;\
ldx [erpt + STRAND_EVBSC_L2_AFAR(0)], reg1 ;\
ldx [erpt + STRAND_EVBSC_L2_AFAR(1)], reg1 ;\
ldx [erpt + STRAND_EVBSC_L2_AFAR(2)], reg1 ;\
ldx [erpt + STRAND_EVBSC_L2_AFAR(3)], reg1 ;\
PRINT("DRAM ELRs\r\n") ;\
ldx [erpt + STRAND_EVBSC_DRAM_LOC(0)], reg1 ;\
ldx [erpt + STRAND_EVBSC_DRAM_LOC(1)], reg1 ;\
ldx [erpt + STRAND_EVBSC_DRAM_LOC(2)], reg1 ;\
ldx [erpt + STRAND_EVBSC_DRAM_LOC(3)], reg1 ;\
PRINT("DRAM ECRs\r\n") ;\
ldx [erpt + STRAND_EVBSC_DRAM_CNTR(0)], reg1 ;\
ldx [erpt + STRAND_EVBSC_DRAM_CNTR(1)], reg1 ;\
ldx [erpt + STRAND_EVBSC_DRAM_CNTR(2)], reg1 ;\
ldx [erpt + STRAND_EVBSC_DRAM_CNTR(3)], reg1 ;\
ldx [erpt + STRAND_VBSC_ERPT + EVBSC_TSTATE], reg1 /* tstate */;\
ldx [erpt + STRAND_VBSC_ERPT + EVBSC_HTSTATE], reg1 /* htstate */;\
ldx [erpt + STRAND_VBSC_ERPT + EVBSC_TPC], reg1 /* tpc */ ;\
lduh [erpt + STRAND_VBSC_ERPT + EVBSC_CPUID], reg1 /* cpuid */;\
lduh [erpt + STRAND_VBSC_ERPT + EVBSC_TT], reg1 /* tt */;\
ldub [erpt + STRAND_VBSC_ERPT + EVBSC_TL], reg1 /* tl */;\
PRINT("------END-------\r\n")
#else /* NIAGARA_BRINGUP */
#define CONSOLE_PRINT_DIAG_ERPT(erpt, reg1)
#endif /* NIAGARA_BRINGUP */
* Correctable error traps can be taken only if PSTATE.IE = 1.
* The hypervisor is run with PSTATE.IE = 0, so no CE traps
* will be taken when running in hypervisor. Therefore, CE
* trap handler is entered only from supervisor which means:
* - no need to check for %htstate.hpriv
* - no need to check for %tstate.gl == MAXGL
* Assume the CE trap taken when executing in supervisor mode.
* For CEs no error report is sent to the sun4v guest. Hence
* the sun4v guest error report members of the erpt struct
* are not filled in. Only the diagnostic error report is
* At entry, PSTATE.IE = 0.
* Register usage: where ever possible
* g4-6 : preserved across PRINT* macros
* g5 : error report pointer
* g6 : strand struct pointer
ENTRY_NP(ce_poll_entry) /* entry point for the error daemon */
stx %g7, [%g6 + STRAND_ERR_RET] ! save return address
/* get strand, CE buffer in %g6-5, they are safe across calls */
STRAND_ERPT_STRUCT(STRAND_CE_RPT, %g6, %g5) ! g6->strand, g5->strand.ce_rpt
SPINLOCK_ENTER_ERRORLOCK(%g1, %g2, %g3)
! XXX set the buffer busy flag
CONSOLE_PRINT_ESRS(%g1, %g2, %g3, %g4)
* Niagara PRM Programming Note: To minimize the possibility of
* missing notification of another error, software should clear any
* multiple error indication as soon as possible.
* Note: - hardware insures that we will not clear a non-CE error
* See PRM 12.4.2 Table 12-6.
ldxa [%g0]ASI_SPARC_ERR_STATUS, %g4 ! SPARC afsr
ldxa [%g0]ASI_SPARC_ERR_ADDR, %g3 ! SPARC afar
ldxa [%g0]ASI_SPARC_ERR_STATUS, %g1 ! re-read afsr
bnz,a %xcc, .ce_rd_sa ! no: read both again
mov %g1, %g4 ! save last status
stxa %g4, [%g0]ASI_SPARC_ERR_STATUS ! clear everything seen
stx %g4, [%g5 + STRAND_VBSC_ERPT + EVBSC_SPARC_AFSR] ! save afsr
stx %g3, [%g5 + STRAND_VBSC_ERPT + EVBSC_SPARC_AFAR] ! save afar
stx %g0, [%g5 + STRAND_VBSC_ERPT + EVBSC_JBI_ERR_LOG]
* Check to see if there is any error to process
CE_CHECK(%g6, %g4, %g1, %g2, %g3) ! strand, spesr,
bz,a %xcc, .ce_unlock_exit ! none: exit
* Generate a basic error report
* Sparc status & address are already loaded
LOAD_BASIC_ERPT(%g6, %g5, %g1, %g2)
! now we have a base diagnostic error report captured that
! can be sent to the SC or diagnosis service provider
! XXX check for TL saturation - why do this for CEs?
! Too drastic to watchdog reset a guest on a corrected error!
! rdpr %tl, %g3 ! get trap level
! cmp %g3, MAXPTL ! is it at max?
! bg,pn %xcc, 1f ! if TL > MAXPTL, watchdog reset
setx 0xdeadbeefdeadbeef,%g3, %g4
set STRAND_VBSC_ERPT + EVBSC_DIAG_BUF + DIAG_BUF_SIZE-8, %g3
cmp %g3, STRAND_VBSC_ERPT + EVBSC_DIAG_BUF
* At this point we now look for the specific errors:
lduw [%g6 + STRAND_ERR_FLAG], %g3
btst ERR_FLAG_SPARC, %g3 ! blackout?
ldx [%g5 + STRAND_VBSC_ERPT + EVBSC_SPARC_AFSR], %g3 ! sparc status
bnz %xcc, .ce_check_l2 ! yes: check l2 dram
btst %g4, %g3 ! any valid CE bit set?
bz %xcc, .ce_check_l2 ! no SPARC, check L2DRAM
mov %g5, %g2 ! g2 = cpu.ce_erpt
btst %g4, %g3 ! is IRC set?
btst %g4, %g3 ! is FRC set?
btst %g4, %g3 ! is DTC set?
btst %g4, %g3 ! is DDC set?
btst %g4, %g3 ! is IDC set?
btst %g4, %g3 ! is ITC set?
! SPARC ESR may have a CE bit and/or MEC bit set
btst %g4, %g3 ! MEC bit set?
! should not get here as all CE conditions have been tested
PRINT("NOTE: Sparc CE: failed to find error bit set!!")
! set up %g1 as first arg to irc_check()
ldx [%g5 + STRAND_VBSC_ERPT + EVBSC_SPARC_AFAR], %g1 ! arg1 = EAR
HVCALL(irc_check) ! %g2 is return value
! let storm protection throttle irc and iru reports
PRINT("persistent IRC error\r\n")
ba .ce_sparc_storm ! finish up
clr %g1 ! no print or send
! send the sparc_err_ebl reg to the diag eng
ldxa [%g0]ASI_SPARC_ERR_EN, %g1
stx %g1, [%g5 + EVBSC_DIAG_BUF + DIAG_BUF_REG_INFO]
ba,a .ce_send_sparc_erpt ! send report & finish up
! Default CE error handler.
! This just sends the CE diagnostic error report to the
! vBSC to generate an FMA error report.
DUMP_ICACHE_INFO(STRAND_CE_RPT, %g1, %g5, %g3, %g4, %g2, %g6, %g7)
DUMP_ICACHE_INFO(STRAND_CE_RPT, %g1, %g5, %g3, %g4, %g2, %g6, %g7)
DUMP_DCACHE_INFO(STRAND_CE_RPT, %g6, %g5, %g1, %g2, %g3, %g4, %g7)
DUMP_DCACHE_INFO(STRAND_CE_RPT, %g6, %g5, %g1, %g2, %g3, %g4, %g7)
* Float Register Correctable:
! set up %g1 as first arg to frc_check()
ldx [%g5 + STRAND_VBSC_ERPT + EVBSC_SPARC_AFAR], %g1
! let storm protection throttle frc and fru reports
PRINT("persistent FRC error\r\n")
ba .ce_sparc_storm ! finish up
clr %g1 ! no print or send
! send the sparc_err_ebl reg to the diag eng
ldxa [%g0]ASI_SPARC_ERR_EN, %g1
stx %g1, [%g5 + EVBSC_DIAG_BUF + DIAG_BUF_REG_INFO]
ba,a .ce_send_sparc_erpt ! send report & finish up
ba,a .ce_send_sparc_erpt ! send report & finish up
* Note: this path is taken also for "MEC only" and "nothing found".
* It will throttle "false" interrupts.
add %g6, STRAND_CE_RPT, %g5 ! g5 -> strand.ce_rpt
SET_STRAND_RPTFLAGS(%g6, %g1)
* This code prevents more than one error every time period from
* the group: SPARC Register File & L1$
lduw [%g6 + STRAND_ERR_FLAG], %g2
btst ERR_FLAG_SPARC, %g2 ! handler installed?
bnz,pn %xcc, .ce_sparc_storm_done ! yes
bset ERR_FLAG_SPARC, %g2 ! no: set it
STRAND2CONFIG_STRUCT(%g6, %g1) ! ->configp
ldx [%g1 + CONFIG_CE_BLACKOUT], %g1
brz,a,pn %g1, .ce_sparc_storm_done ! zero: blackout disabled
stw %g2, [%g6 + STRAND_ERR_FLAG] ! flag as installed
HVCALL(err_set_sparc_bits) ! g2 = handler address
set CEEN, %g3 ! g3 = arg 0 : bit(s) to set
clr %g4 ! g4 = arg 1 : not used
HVCALL(cyclic_add_rel) /* ( del_tick, address, arg0, arg1 ) */
/* g6->strand, g5->ce_rpt */
* L2DRAM errors are global and may not be valid for this cpu.
* Process if PID == ERRORSTEER, or this cpu was sent the error.
DUMP_L2_DRAM_ERROR_LOGS(%g6, %g5, %g1, %g2, %g3, %g4, %g7)
* Only one error in one bank will be processed
* each pass through here.
* Note: storm prevention will block processing of banks
! go through each L2 bank and check for valid CE bits
CE_CHECK_L2_ESR(0, %g6, %g4, %g1, %g2)
bz %xcc, .ce_check_l2_b1 ! check next bank
SET_STRAND_L2BANK(0, %g6, %g7) ! save bank#
! dump all of the l2 info. must pass the registers as is
DUMP_L2_SET_TAG_DATA(0, STRAND_CE_RPT, %g6, %g5, %g1, %g2)
! dram data here since all L2 esr need it
ldx [%g6 + STRAND_CE_RPT + STRAND_EVBSC_L2_AFSR(0)], %g4 ! l2esr
setx L2_ESR_CE_NO_EAR_BITS, %g1, %g2
CLEAR_DRAM_CONTENTS(0, STRAND_CE_RPT, %g6, %g5)
DUMP_DRAM_CONTENTS(0, STRAND_CE_RPT, %g6, %g5, %g1, %g2)
CLEAR_L2_ESR(0, %g4, %g1, %g2)
PROCESS_CE_IN_L2_ESR(0, %g6, %g5, %g4, %g1, %g2, %g3)
/* 6->strand 5->erpt 4=flags: action */
CE_CHECK_L2_ESR(1, %g6, %g4, %g1, %g2)
bz %xcc, .ce_check_l2_b2 ! check next bank
SET_STRAND_L2BANK(1, %g6, %g7) ! save bank#
! dump all of the l2 info. must pass the registers as is
DUMP_L2_SET_TAG_DATA(1, STRAND_CE_RPT, %g6, %g5, %g1, %g2)
! dram data here since all L2 esr need it
ldx [%g6 + STRAND_CE_RPT + STRAND_EVBSC_L2_AFSR(1)], %g4 ! l2esr
setx L2_ESR_CE_NO_EAR_BITS, %g1, %g2
CLEAR_DRAM_CONTENTS(0, STRAND_CE_RPT, %g6, %g5)
DUMP_DRAM_CONTENTS(1, STRAND_CE_RPT, %g6, %g5, %g1, %g2)
CLEAR_L2_ESR(1, %g4, %g1, %g2)
PROCESS_CE_IN_L2_ESR(1, %g6, %g5, %g4, %g1, %g2, %g3)
CE_CHECK_L2_ESR(2, %g6, %g4, %g1, %g2)
bz %xcc, .ce_check_l2_b3 ! check next bank
SET_STRAND_L2BANK(2, %g6, %g7) ! save bank#
! dump all of the l2 info. must pass the registers as is
DUMP_L2_SET_TAG_DATA(2, STRAND_CE_RPT, %g6, %g5, %g1, %g2)
! dram data here since all L2 esr need it
ldx [%g6 + STRAND_CE_RPT + STRAND_EVBSC_L2_AFSR(2)], %g4 ! l2esr
setx L2_ESR_CE_NO_EAR_BITS, %g1, %g2
CLEAR_DRAM_CONTENTS(0, STRAND_CE_RPT, %g6, %g5)
DUMP_DRAM_CONTENTS(2, STRAND_CE_RPT, %g6, %g5, %g1, %g2)
CLEAR_L2_ESR(2, %g4, %g1, %g2)
PROCESS_CE_IN_L2_ESR(2, %g6, %g5, %g4, %g1, %g2, %g3)
CE_CHECK_L2_ESR(3, %g6, %g4, %g1, %g2)
SET_STRAND_L2BANK(3, %g6, %g7) ! save bank#
! dump all of the l2 info. must pass the registers as is
DUMP_L2_SET_TAG_DATA(3, STRAND_CE_RPT, %g6, %g5, %g1, %g2)
! dram data here since all L2 esr need it
ldx [%g6 + STRAND_CE_RPT + STRAND_EVBSC_L2_AFSR(3)], %g4 ! l2esr
setx L2_ESR_CE_NO_EAR_BITS, %g1, %g2
CLEAR_DRAM_CONTENTS(0, STRAND_CE_RPT, %g6, %g5)
DUMP_DRAM_CONTENTS(3, STRAND_CE_RPT, %g6, %g5, %g1, %g2)
CLEAR_L2_ESR(3, %g4, %g1, %g2)
PROCESS_CE_IN_L2_ESR(3, %g6, %g5, %g4, %g1, %g2, %g3)
brlz %g4, .ce_no_error ! no error found - exit now
SET_STRAND_RPTFLAGS(%g6, %g4)
* This code prevents more than one error every six seconds from
* the groups: L2$, DRAM Banks. Since the enables are system wide
* we use the error enable bits to indicate the blackout period.
* The callback flag is used to indicate if the handler is enabled
* There is a very small window where multiple interrupts can be
* delivered to more than one cpu.
* Only one will get through this set successfully.
GET_STRAND_L2BANK(%g6, %g4)
BCLR_L2_BANK_EEN(%g4, CEEN, %g1, %g2) ! g4 = bank#
bz %xcc, .ce_l2dram_storm_done ! already disabled
mov ERR_FLAG_L2DRAM, %g1 ! L2DRAM flag
sll %g1, %g4, %g1 ! << bank#
lduw [%g6 + STRAND_ERR_FLAG], %g2 ! installed flags
btst %g1, %g2 ! handler installed?
bnz,pn %xcc, .ce_l2dram_storm_done ! yes
bset %g1, %g2 ! no: set it
STRAND2CONFIG_STRUCT(%g6, %g1) ! ->configp
ldx [%g1 + CONFIG_CE_BLACKOUT], %g1
brz,a,pn %g1, .ce_l2dram_storm_done ! zero: blackout disabled
stw %g2, [%g6 + STRAND_ERR_FLAG] ! handler installed
HVCALL(err_set_l2_bits) ! g2 = handler address
mov CEEN, %g3 ! g3 = arg 0 : bit(s) to set
! g4 = arg 1 : B5-0: bank #
HVCALL(cyclic_add_rel) /* ( del_tick, address, arg0, arg1 ) */
GET_STRAND_RPTFLAGS(%g6, %g4) ! g4: flags: action
btst ERR_SEND_DIAG, %g4 ! send diag report?
bz %xcc, .ce_unlock_exit ! no
add %g6, STRAND_CE_RPT + STRAND_VBSC_ERPT, %g1 ! erpt.vbsc
add %g6, STRAND_CE_RPT + STRAND_UNSENT_PKT, %g2 ! erpt.unsent flag
mov EVBSC_SIZE, %g3 ! size
HVCALL(send_diag_erpt) ! g4-6 clobbered
SET_STRAND_RPTFLAGS(%g6, %g0) ! clear report flags
ba,a .ce_unlock_exit ! handler epilogue
! XXX CEs should never watchdog_reset a guest???
! XXX It should also not inadvertently let a guest run at TL > MAXPTL
! send the error report to the diagnostic service provider
* Sparc and L2DRAM checked with no error to report:
! Some other thread beat us to it, or we don't own it, or
! the blackout(s) have left us nothing to report.
PRINT("NOTE: No Reportable Error\r\n")
* The CE error handlers return here after handling the error.
/* MUST leave Sparc CEEN enabled to get L2DRAM interrupts! */
ldxa [%g0]ASI_SPARC_ERR_EN, %g1 ! get current
bset CEEN, %g1 ! enable CEEN
stxa %g1, [%g0] ASI_SPARC_ERR_EN ! ..
* With CE storm prevention, the CEEN will be reenabled by the
* hstick_match handler when errors stop.
SPINLOCK_EXIT_ERRORLOCK(%g1) ! release lock
ldx [%g6 + STRAND_ERR_RET], %g7 ! get return address
brnz,a %g7, .ce_return ! valid: clear it & return
stx %g0, [%g6+ STRAND_ERR_RET] ! ..
! NULL: return from interrupt
retry ! return from CE interrupt
* Disrupting uncorrectable error handler.
* All of these errors are resumable errors to the guest. I.e. they
* are not nonresumable errors.
* At entry, PSTATE.IE = 0, so no furthur disrupting error traps.
* The CE error report buffer is used for reporting.
* Check for DBU in DRAM ESR
CHECK_DRAM_ERROR(DRAM_ESR_DBU, %g1, %g2, %g3, %g4)
bnz,pn %xcc, .fatal_reset_dbu ! yes: bail now
/* get strand, CE buffer in %g6-5, they are safe across calls */
STRAND_ERPT_STRUCT(STRAND_CE_RPT, %g6, %g5) ! g6->strand, g5->strand.ce_rpt
* We do not idle all strands if the scrubber got a UE
CHECK_L2_ERROR(L2_ESR_LDSU, %g1, %g2, %g3)
bnz,pn %xcc, .dis_ue_no_idle
mov ERR_FLAG_STRANDS_NOT_IDLED, %g1
CHECK_DRAM_ERROR(DRAM_ESR_DSU, %g1, %g2, %g3, %g4)
bnz,pn %xcc, .dis_ue_no_idle
mov ERR_FLAG_STRANDS_NOT_IDLED, %g1
SPINLOCK_IDLE_ALL_STRAND(%g6, %g1, %g2, %g3, %g4)
! At this point, this is the only strand executing
lduw [%g6 + STRAND_ERR_FLAG], %g2 ! installed flags
bclr ERR_FLAG_STRANDS_NOT_IDLED, %g2 ! reset STRANDS_IDLED
stw %g2, [%g6 + STRAND_ERR_FLAG] ! ..
CONSOLE_PRINT_ESRS(%g1, %g2, %g3, %g4)
* Niagara PRM Programming Note: To minimize the possibility of
* missing notification of an error, software should any multiple
* error indication as soon as possible.
ldxa [%g0]ASI_SPARC_ERR_STATUS, %g4 ! SPARC afsr
ldxa [%g0]ASI_SPARC_ERR_ADDR, %g3 ! SPARC afar
ldxa [%g0]ASI_SPARC_ERR_STATUS, %g1 ! re-read afsr
bnz,a %xcc, .dis_ue_rd_sa ! no: read both again
mov %g1, %g4 ! save last status
stxa %g4, [%g0]ASI_SPARC_ERR_STATUS ! clear SPARC afsr
stx %g4, [%g5 + STRAND_VBSC_ERPT + EVBSC_SPARC_AFSR]
stx %g3, [%g5 + STRAND_VBSC_ERPT + EVBSC_SPARC_AFAR]
stx %g0, [%g5 + STRAND_VBSC_ERPT + EVBSC_JBI_ERR_LOG]
* Generate a basic error report
* Sparc status & address are already loaded
LOAD_BASIC_ERPT(%g6, %g5, %g1, %g2)
mov %g5, %g2 ! strand.ue_erpt
setx 0xdeadbeefdeadbeef,%g3, %g4
set STRAND_VBSC_ERPT + EVBSC_DIAG_BUF + DIAG_BUF_SIZE-8, %g3
cmp %g3, STRAND_VBSC_ERPT + EVBSC_DIAG_BUF
/* Dump the L2 and DRAM registers also */
! %g1 has strand pointer, %g2 has &ce_rpt - pointer to error report
DUMP_L2_DRAM_ERROR_LOGS(%g1, %g2, %g3, %g4, %g5, %g6, %g7)
! go through each L2 bank and check for valid UE bits
DIS_UE_CHECK_L2_ESR(0, %g1, %g2, %g3, %g4) ! %g1 = L2ESR
bz %xcc, .dis_ue_check_l2_b1 ! check next bank
/* save the state of the line */
SAVE_L2_LINE_STATE(0, STRAND_CE_RPT, %g1, %g2)
DUMP_L2_SET_TAG_DATA(0, STRAND_CE_RPT, %g1, %g2, %g1, %g2)
ldx [%g2 + STRAND_EVBSC_L2_AFSR(0)], %g4 ! l2esr
CLEAR_L2_ESR(0, %g4, %g5, %g6) ! clear L2 ESR
PROCESS_DIS_UE_IN_L2_ESR(0, %g1, %g2, %g3, %g4, %g5, %g6, %g7, \
.dis_ue_err_ret, .ue_resume_exit)
DIS_UE_CHECK_L2_ESR(1, %g1, %g2, %g3, %g4) ! %g1 = L2ESR
bz %xcc, .dis_ue_check_l2_b2 ! check next bank
/* save the state of the line */
SAVE_L2_LINE_STATE(1, STRAND_CE_RPT, %g1, %g2)
DUMP_L2_SET_TAG_DATA(1, STRAND_CE_RPT, %g1, %g2, %g1, %g2)
ldx [%g2 + STRAND_EVBSC_L2_AFSR(1)], %g4 ! l2esr
CLEAR_L2_ESR(1, %g4, %g5, %g6) ! clear L2 ESR
PROCESS_DIS_UE_IN_L2_ESR(1, %g1, %g2, %g3, %g4, %g5, %g6, %g7, \
.dis_ue_err_ret, .ue_resume_exit)
DIS_UE_CHECK_L2_ESR(2, %g1, %g2, %g3, %g4) ! %g1 = L2ESR
bz %xcc, .dis_ue_check_l2_b3 ! check next bank
/* save the state of the line */
SAVE_L2_LINE_STATE(2, STRAND_CE_RPT, %g1, %g2)
DUMP_L2_SET_TAG_DATA(2, STRAND_CE_RPT, %g1, %g2, %g1, %g2)
ldx [%g2 + STRAND_EVBSC_L2_AFSR(2)], %g4 ! l2esr
CLEAR_L2_ESR(2, %g4, %g5, %g6) ! clear L2 ESR
PROCESS_DIS_UE_IN_L2_ESR(2, %g1, %g2, %g3, %g4, %g5, %g6, %g7, \
.dis_ue_err_ret, .ue_resume_exit)
DIS_UE_CHECK_L2_ESR(3, %g1, %g2, %g3, %g4) ! %g1 = L2ESR
bz %xcc, .dis_ue_no_error ! XXX spurious?
/* save the state of the line */
SAVE_L2_LINE_STATE(3, STRAND_CE_RPT, %g1, %g2)
DUMP_L2_SET_TAG_DATA(3, STRAND_CE_RPT, %g1, %g2, %g1, %g2)
ldx [%g2 + STRAND_EVBSC_L2_AFSR(3)], %g4 ! l2esr
CLEAR_L2_ESR(3, %g4, %g5, %g6) ! clear L2 ESR
PROCESS_DIS_UE_IN_L2_ESR(3, %g1, %g2, %g3, %g4, %g5, %g6, %g7, \
.dis_ue_err_ret, .ue_resume_exit)
! All banks checked, now return
ba,a .dis_ue_err_ret ! UE handler epilogue
PRINT("NO DIS UE ERROR\r\n")
! some other thread beat us to it.
! no bits in L2, simply return (XXX send a service error report?)
add %g6, STRAND_CE_RPT + STRAND_VBSC_ERPT, %g1 ! erpt.vbsc
add %g6, STRAND_CE_RPT + STRAND_UNSENT_PKT, %g2 ! erpt.unsent flag
mov EVBSC_SIZE, %g3 ! size
ba,a .dis_ue_err_ret ! CE handler epilogue
* General handling of UEs
* if HTSTATE[TL].GL == MAXPGL
* reset chip and partitions
* else if HTSTATE.PRIV == 1
* reset chip and partitions
* else if TL > MAXPTL then watchdog_reset
* else call common handler
* Uncorrectable error traps can be taken any time NCEEN
* in the SPARC error status register is set.
* UEs can occur when executing in the hypervisor, supervisor,
* XXX UEs when executing in hypervisor resets the system XXX
* TL overflow causes guest to be reset
ENTRY_NP(ue_poll_entry) /* entry point for the error daemon */
stx %g7, [%g6 + STRAND_ERR_RET] ! save return address
* Check for global register saturation and save the current
* global register set if necessary.
* Check for DBU in DRAM ESR
CHECK_DRAM_ERROR(DRAM_ESR_DBU, %g1, %g2, %g3, %g4)
bnz,pn %xcc, .fatal_reset_dbu ! yes: bail now
/* get strand, UE buffer in %g6-5, they are safe across calls */
STRAND_ERPT_STRUCT(STRAND_UE_RPT, %g6, %g5) ! g6->strand, g5->strand.ue_rpt
* check to see if UE occurred in hypervisor
* We check early in order to avoid a deadlock situation.
* in the previous trap, we were handling either a dis UE or a CE
bnz %xcc, .ue_get_status_addr ! UE in hypervisor
SPINLOCK_IDLE_ALL_STRAND(%g6, %g1, %g2, %g3, %g4)
! At this point, this is the only strand executing
ldxa [%g0]ASI_SPARC_ERR_STATUS, %g1 ! SPARC afsr
set SPARC_ESR_NCU, %g4 ! Ifetch/Load from IO space bit
bnz %xcc, .skip_print_esrs ! skip printing ESRs
CONSOLE_PRINT_ESRS(%g1, %g2, %g3, %g4)
* Niagara PRM Programming Note: To minimize the possibility of
* missing notification of an error, software should clear the
* error indication as soon as possible.
ldxa [%g0]ASI_SPARC_ERR_STATUS, %g4 ! SPARC afsr
ldxa [%g0]ASI_SPARC_ERR_ADDR, %g3 ! SPARC afar
ldxa [%g0]ASI_SPARC_ERR_STATUS, %g1 ! re-read afsr
bnz,a %xcc, .ue_rd_sa ! no: read both again
mov %g1, %g4 ! save last status
stxa %g4, [%g0]ASI_SPARC_ERR_STATUS ! clear everything seen
stx %g4, [%g5 + STRAND_VBSC_ERPT + EVBSC_SPARC_AFSR]
stx %g3, [%g5 + STRAND_VBSC_ERPT + EVBSC_SPARC_AFAR]
stx %g0, [%g5 + STRAND_VBSC_ERPT + EVBSC_JBI_ERR_LOG]
* Check to see if there is any error to process
UE_CHECK(SPARC_UE_MEU_BITS, L2_ESR_UE_BITS, %g4, %g1, %g2, %g3)
bz,a %xcc, .ue_resume_exit ! none: exit
* Generate a basic error report
* Sparc status & address are already loaded
LOAD_BASIC_ERPT(%g6, %g5, %g1, %g2)
mov %g5, %g2 ! strand.ue_erpt
setx 0xdeadbeefdeadbeef,%g3, %g4
set STRAND_VBSC_ERPT + EVBSC_DIAG_BUF + DIAG_BUF_SIZE-8, %g3
cmp %g3, STRAND_VBSC_ERPT + EVBSC_DIAG_BUF
! set error descriptor to UE resumable
set EDESC_UE_RESUMABLE, %g3
st %g3, [%g2 + STRAND_SUN4V_ERPT + ESUN4V_EDESC]
! check SPARC ESR for thread-specific errors
ldx [%g2 + STRAND_VBSC_ERPT + EVBSC_SPARC_AFSR], %g3
set SPARC_UE_MEU_BITS, %g4
btst %g4, %g3 ! any UE or MEU bit set?
bz %xcc, .ue_dump_l2 ! no UEs, check L2
! a UE/MEU bit is set in the SPARC ESR. If it is LDAU, then
! it is L2$/DRAM related.
set SPARC_ESR_LDAU, %g4 ! LDAU bit
btst %g4, %g3 ! LDAU set?
set SPARC_ESR_NCU, %g4 ! NCU bit
set SPARC_ESR_IRU, %g4 ! IRU bit
set SPARC_ESR_FRU, %g4 ! FRU bit
* check to see if UE occurred in hypervisor
* We check early in order to avoid a deadlock situation.
* in the previous trap, we were handling either a dis UE or a CE
bnz %xcc, .hpriv_ue ! UE in hypervisor
set SPARC_ESR_MAU, %g4 ! MAU bit
set SPARC_ESR_IMDU, %g4 ! IMDU bit
btst %g4, %g3 ! IMDU set?
set SPARC_ESR_IMTU, %g4 ! IMTU bit
btst %g4, %g3 ! IMTU set?
set SPARC_ESR_DMTU, %g4 ! DMTU bit
btst %g4, %g3 ! DMTU set?
set SPARC_ESR_DMDU, %g4 ! DMDU bit
btst %g4, %g3 ! DMDU set?
set SPARC_ESR_DMSU, %g4 ! DMSU bit
btst %g4, %g3 ! DMSU set?
set SPARC_ESR_MEU, %g4 ! MEU bit
bnz %xcc, .ue_just_meu_err
! Should not get here as all UE bits have been tested
ba,a .ue_send_resume_exit
* FRU: Float Register File uncorrectable ECC error
! If the error is unrecoverable, mark the cpu in error. Else
! fill out the ue error report in cpu structure. send service
! entity diagnosis report, then call precise_ue_err_ret. In
! precise_ue_err_ret, it will queue the error report to guest.
STRAND_ERPT_STRUCT(STRAND_UE_RPT, %g2, %g2) ! ->cpu.ue_rpt
ldx [%g2 + STRAND_VBSC_ERPT + EVBSC_SPARC_AFAR], %g1
HVCALL(clear_fregerr) ! %g1 = input, g2 = output
!! %g2 contains a 0 if we got FRU after FRC for a persistent error
brnz %g2, .ue_not_from_frc ! it is a new FRU
! Took an FRU trap from the FRC handler reread. Return to FRC handler
PRINT("FRU FROM FRC DIAG\r\n");
SPINLOCK_RESUME_ALL_STRAND(%g6, %g1, %g2, %g3, %g4)
done ! complete reread of reg
* check to see if UE occurred in hypervisor
bnz %xcc, .hpriv_ue ! UE in hypervisor
HVCALL(fru_check) ! g2 = status
! %g2 contains whether the error is transient, persistent or a failed RF
cmp %g2, RF_TRANSIENT ! transient?
bne .ue_fru_cpu ! no: unrecoverable
! FRU is recoverable, send a nonresumable error to the guest
SET_ERPT_EDESC_EATTR(STRAND_UE_RPT, EATTR_FRF,
EDESC_PRECISE_NONRESUMABLE, %g1, %g2, %g3)
CLEAR_SPARC_ESR(STRAND_UE_RPT, SPARC_ESR_FRU, %g1, %g2, %g3, %g4)
/* FRU is unrecoverable, mark CPU in error */
PRINT("CPU in ERROR -FRU\r\n")
! Set the CPU_ERROR status flag
SET_CPU_IN_ERROR(%g1, %g2)
SET_ERPT_EDESC_EATTR(STRAND_UE_RPT, EATTR_CPU,
EDESC_UE_RESUMABLE, %g1, %g2, %g3)
ba,a .ue_send_resume_exit
* IMDU: ITLB Data Parity Error (precise)
* Detected on instruction translation as well as with loads
* to ASI_ITLB_DATA_ACCESS_REG.
add %g1, STRAND_UE_RPT, %g2 ! %g2 = strand.ue_rpt
! dump the ITLB entries into cpu.ue_rpt.diag_buf
DUMP_ITLB(%g1, %g2, %g3, %g4, %g5, %g6, %g7)
stxa %g0, [%g1] ASI_TLB_INVALIDATE
#if 0 /* { FIXME: no longer required */
! log the TLB entries on the console
CONSOLE_PRINT_TLB_DATA("ITLB Tag Data\r\n", %g1, %g2, %g3, %g4, \
! For bringup, dump out the TLB entries after demap page
add %g1, STRAND_UE_RPT, %g2 ! %g2 = strand.ue_rpt
add %g2, 0x400, %g2 ! use the second 1KB area
! dump the ITLB entries into strand diag buffer area
DUMP_ITLB(%g1, %g2, %g3, %g4, %g5, %g6, %g7)
! log the TLB entries on the console for bringup
CONSOLE_PRINT_TLB_DATA_2("ITLB Tag Data\r\n", %g1, %g2, %g3, \
ba,a .ue_send_resume_exit ! resumable error
* IMTU: ITLB Tag Parity Error
* Parity error when accessed via a load from ASI_ITLB_TAG_READ
* Action: Reset the platform.
! Can't dump tlb since there is no safe mechanism
ba,a .ue_send_rpt_and_abort ! reset
* DMTU: DTLB Tag Parity Error
* Parity error when accessed via a load from ASI_DTLB_TAG_READ
* Action: reset the platform.
! Can't dump tlb since there is no safe mechanism
ba,a .ue_send_rpt_and_abort ! reset
* DMDU: DTLB Data Parity Error on Load and Atomics
* Parity error on atomic or load translation as well
* as with loads to ASI_DTLB_DATA_ACCESS_REG.
add %g1, STRAND_UE_RPT, %g2 ! %g2 = strand.ue_rpt
! dump the DTLB entries into the strand diag buffer
DUMP_DTLB(%g1, %g2, %g3, %g4, %g5, %g6, %g7)
! log the TLB data on the console
CONSOLE_PRINT_TLB_DATA("DTLB Tag Data\r\n", %g1, %g2, %g3, %g4, \
stxa %g0, [%g1] ASI_TLB_INVALIDATE
#if 0 /* { FIXME: no longer required */
! For bringup, dump out the TLB entries after demap page
add %g1, STRAND_UE_RPT, %g2 ! %g2 = strand.ue_rpt
add %g2, 1024, %g2 ! use next 1KB area
! dump the dtlb entries into the strand diag buffer
DUMP_DTLB(%g1, %g2, %g3, %g4, %g5, %g6, %g7)
! log the tlb entries on the console for bringup
CONSOLE_PRINT_TLB_DATA_2("DTLB Tag Data\r\n", %g1, %g2, %g3, \
ba,a .ue_send_resume_exit ! resumable UE
* IRU: IRF Uncorrectable ECC Error
STRAND_ERPT_STRUCT(STRAND_UE_RPT, %g2, %g2)
ldx [%g2 + STRAND_VBSC_ERPT + EVBSC_SPARC_AFAR], %g1
HVCALL(clear_iregerr) ! %g1 = input, %g2 = output
!! %g2 = 0 if we got IRU after IRC for a persistent error bit
brnz %g2, .ue_not_from_irc ! it is a new IRU
! Took an IRU trap from the IRC handler reread. Return to IRC handler
PRINT("IRU FROM IRC DIAG\r\n")
SPINLOCK_RESUME_ALL_STRAND(%g6, %g1, %g2, %g3, %g4)
done ! complete reread of reg
* check to see if UE occurred in hypervisor
bnz %xcc, .hpriv_ue ! UE in hypervisor
HVCALL(iru_check) ! g2 = status
cmp %g2, RF_TRANSIENT ! transient?
bne .ue_iru_cpu ! no: unrecoverable
! IRU is recoverable, send a nonresumable error to the guest
SET_ERPT_EDESC_EATTR(STRAND_UE_RPT, EATTR_IRF,
EDESC_PRECISE_NONRESUMABLE, %g1, %g2, %g3)
CLEAR_SPARC_ESR(STRAND_UE_RPT, SPARC_ESR_IRU, %g1, %g2, %g3, %g4)
! send the sparc_err_ebl reg to the diag eng
STRAND_ERPT_STRUCT(STRAND_UE_RPT, %g1, %g2)
ldxa [%g0]ASI_SPARC_ERR_EN, %g3
stx %g3, [%g2 + STRAND_VBSC_ERPT + EVBSC_DIAG_BUF + DIAG_BUF_REG_INFO]
ba,a .sendnr_ue_resume_exit
! IRU is unrecoverable, mark CPU in error
PRINT("CPU in ERROR - IRU\r\n")
! Set the CPU_ERROR status flag
SET_CPU_IN_ERROR(%g1, %g2)
SET_ERPT_EDESC_EATTR(STRAND_UE_RPT, EATTR_CPU,
EDESC_UE_RESUMABLE, %g1, %g2, %g3)
* DMSU: DTLB Data Parity Error on Store
* Parity error on store translation.
stxa %g0, [%g1] ASI_TLB_INVALIDATE
add %g1, STRAND_UE_RPT, %g2 ! %g2 = strand.ue_rpt
! dump the DTLB entries into the strand diag buffer
DUMP_DTLB(%g1, %g2, %g3, %g4, %g5, %g6, %g7)
! log the TLB data on the console
CONSOLE_PRINT_TLB_DATA("DTLB Tag Data\r\n", %g1, %g2, %g3, %g4, \
#if 0 /* { FIXME: no longer required */
! For bringup we dump the TLB after the demap operation
add %g1, STRAND_UE_RPT, %g2 ! %g2 = strand.ue_rpt
add %g2, 1024, %g2 ! use the next 1KB area
DUMP_DTLB(%g1, %g2, %g3, %g4, %g5, %g6, %g7)
! log the dtlb to the console
CONSOLE_PRINT_TLB_DATA_2("DTLB Tag Data\r\n", %g1, %g2, %g3, \
ba,a .ue_send_resume_exit ! resumable error
* MEU: Multiple Uncorrectable Error bit
* Sometimes only the MEU bit will be set. It is treated as
ba,a .ue_send_resume_exit ! resumable UE
add %g6, STRAND_UE_RPT + STRAND_VBSC_ERPT, %g1 ! erpt.vbsc
set STRAND_UE_RPT + STRAND_UNSENT_PKT, %g2
add %g6, %g2, %g2 ! erpt.unsent flag
mov EVBSC_SIZE, %g3 ! size
SPINLOCK_RESUME_ALL_STRAND(%g6, %g1, %g2, %g3, %g4)
* NCU: IO Load/Instruction Fetch Error
ldx [%g1 + %g2], %g2 ! strand.io_prot
brz %g2, 1f ! if zero, no error protection
! under i/o error protection
! set the i/o error flag in the cpu structure and complete the
stx %g3, [%g1 + %g2] ! strand.io_error = 1
! clear JBI_ERR_LOG, JBI_ERR_OVF
setx JBI_ERR_LOG, %g3, %g4
stx %g5, [%g4] ! clear JBI_ERROR_LOG
setx JBI_ERR_OVF, %g3, %g4
stx %g5, [%g4] ! clear JBI_ERROR_OVF
SPINLOCK_RESUME_ALL_STRAND(%g1, %g3, %g4, %g5, %g6)
done ! complete the instruction
! collect all diagnostic data
add %g1, STRAND_UE_RPT, %g2 ! %g2 = strand.ue_rpt
DUMP_JBI_SSI(%g1, %g2, %g3, %g4, %g5, %g6, %g7)
! clear JBI_ERR_LOG, JBI_ERR_OVF, SSI_LOG
setx JBI_ERR_LOG, %g3, %g4
stx %g5, [%g4] ! clear JBI_ERROR_LOG
setx JBI_ERR_OVF, %g3, %g4
stx %g5, [%g4] ! clear JBI_ERROR_OVF
PRINT("NO ERROR LOGGED IN JBI SSI LOG\r\n")
CONSOLE_PRINT_JBI_SSI("JBI SSI Log\r\n", %g1, %g2, %g3, %g4, \
STRAND_ERPT_STRUCT(STRAND_UE_RPT, %g6, %g1)
inc STRAND_VBSC_ERPT, %g1 ! erpt.vbsc
set STRAND_UE_RPT + STRAND_UNSENT_PKT, %g2
add %g6, %g2, %g2 ! erpt.unsent flag
mov EVBSC_SIZE, %g3 ! size
SET_ERPT_EDESC_EATTR(STRAND_UE_RPT, EATTR_PIO, \
EDESC_PRECISE_NONRESUMABLE, %g4, %g5, %g6)
STRAND_ERPT_STRUCT(STRAND_UE_RPT, %g1, %g2)
ldx [%g2 + STRAND_VBSC_ERPT + EVBSC_SPARC_AFAR], %g3 ! VA
stx %g3, [%g2 + STRAND_SUN4V_ERPT + ESUN4V_ADDR]
ba,a precise_ue_err_ret ! UE error epilogue
ba,a .sendnr_ue_resume_exit ! non-resumable UE epilogue
* Precise UEs that are nonresumable errors get here.
* Here the diagnostic erpt is sent before executing
.sendnr_ue_resume_exit: ! non-resumable UE epilogue
add %g6, STRAND_UE_RPT + STRAND_VBSC_ERPT, %g1 ! erpt.vbsc
set STRAND_UE_RPT + STRAND_UNSENT_PKT, %g2
add %g6, %g2, %g2 ! erpt.unsent flag
mov EVBSC_SIZE, %g3 ! size
ba,a precise_ue_err_ret ! UE error epilogue
! %g1 has the strand pointer, %g2 has the UE error report buffer
DUMP_L2_DRAM_ERROR_LOGS(%g1, %g2, %g3, %g4, %g5, %g6, %g7)
* check to see if UE occurred in hypervisor
* We check early in order to avoid a deadlock situation.
* in the previous trap, we were handling either a dis UE or a CE
bnz %xcc, .hpriv_ue ! UE in hypervisor
! check for privileged TL overflow
rdpr %tl, %g1 ! get trap level
cmp %g1, MAXPTL ! is it at max?
bgu,pn %xcc, .tl_overflow ! TL > MAXPTL
! check for SPARC_ESR.LDAU
! go through each L2 bank and check for valid UE bits
UE_CHECK_L2_ESR(0, %g1, %g2, %g3, %g4) ! %g1 = L2ESR
bz %xcc, .ue_check_l2_b1 ! check next bank
SAVE_L2_LINE_STATE(0, STRAND_UE_RPT, %g1, %g2)
DUMP_L2_SET_TAG_DATA(0, STRAND_UE_RPT, %g1, %g2, %g1, %g2)
ldx [%g2 + STRAND_EVBSC_L2_AFSR(0)], %g4 ! l2esr
CLEAR_L2_ESR(0, %g4, %g5, %g6) ! clear L2 ESR
PROCESS_UE_IN_L2_ESR(0, %g1, %g2, %g3, %g4, %g5, %g6, %g7, \
.sendnr_ue_resume_exit, .ue_senddiag_resume_exit, \
UE_CHECK_L2_ESR(1, %g1, %g2, %g3, %g4) ! %g1 = L2ESR
bz %xcc, .ue_check_l2_b2 ! check next bank
SAVE_L2_LINE_STATE(1, STRAND_UE_RPT, %g1, %g2)
DUMP_L2_SET_TAG_DATA(1, STRAND_UE_RPT, %g1, %g2, %g1, %g2)
ldx [%g2 + STRAND_EVBSC_L2_AFSR(1)], %g4 ! l2esr
CLEAR_L2_ESR(1, %g4, %g5, %g6) ! clear L2 ESR
PROCESS_UE_IN_L2_ESR(1, %g1, %g2, %g3, %g4, %g5, %g6, %g7, \
.sendnr_ue_resume_exit, .ue_senddiag_resume_exit, \
UE_CHECK_L2_ESR(2, %g1, %g2, %g3, %g4) ! %g1 = L2ESR
bz %xcc, .ue_check_l2_b3 ! check next bank
SAVE_L2_LINE_STATE(2, STRAND_UE_RPT, %g1, %g2)
DUMP_L2_SET_TAG_DATA(2, STRAND_UE_RPT, %g1, %g2, %g1, %g2)
ldx [%g2 + STRAND_EVBSC_L2_AFSR(2)], %g4 ! l2esr
CLEAR_L2_ESR(2, %g4, %g5, %g6) ! clear L2 ESR
PROCESS_UE_IN_L2_ESR(2, %g1, %g2, %g3, %g4, %g5, %g6, %g7, \
.sendnr_ue_resume_exit, .ue_senddiag_resume_exit, \
UE_CHECK_L2_ESR(3, %g1, %g2, %g3, %g4) ! %g1 = L2ESR
bz %xcc, .ue_no_error ! XXX spurious?
SAVE_L2_LINE_STATE(3, STRAND_UE_RPT, %g1, %g2)
DUMP_L2_SET_TAG_DATA(3, STRAND_UE_RPT, %g1, %g2, %g1, %g2)
ldx [%g2 + STRAND_EVBSC_L2_AFSR(3)], %g4 ! l2esr
CLEAR_L2_ESR(3, %g4, %g5, %g6) ! clear L2 ESR
PROCESS_UE_IN_L2_ESR(3, %g1, %g2, %g3, %g4, %g5, %g6, %g7, \
.sendnr_ue_resume_exit, .ue_senddiag_resume_exit, \
! All banks checked, now return
! some other thread beat us to it.
! no bits in L2, simply return (XXX send a service error report?)
* Precise UEs that are resumable errors get here.
* Here the diagnostic erpt is sent before executing
add %g6, STRAND_UE_RPT + STRAND_VBSC_ERPT, %g1 ! erpt.vbsc
set STRAND_UE_RPT + STRAND_UNSENT_PKT, %g2
add %g6, %g2, %g2 ! erpt.unsent flag
mov EVBSC_SIZE, %g3 ! size
ba,a .ue_resume_exit ! resumable UE epilogue
add %g6, STRAND_UE_RPT + STRAND_VBSC_ERPT, %g1 ! erpt.vbsc
set STRAND_UE_RPT + STRAND_UNSENT_PKT, %g2
add %g6, %g2, %g2 ! erpt.unsent flag
mov EVBSC_SIZE, %g3 ! size
add %g6, STRAND_UE_RPT + STRAND_VBSC_ERPT, %g1 ! erpt.vbsc
set STRAND_UE_RPT + STRAND_UNSENT_PKT, %g2
add %g6, %g2, %g2 ! erpt.unsent flag
mov EVBSC_SIZE, %g3 ! size
HV_PRINT_SPINLOCK_ENTER(%g1, %g2, %g3)
HV_PRINT_NOTRAP("UE in hypervisor - reset the system\r\n")
HV_PRINT_NOTRAP("TPC: 0x")
HV_PRINT_NOTRAP("TT: 0x")
HV_PRINT_NOTRAP("TSTATE: 0x")
HV_PRINT_SPINLOCK_EXIT(%g1)
SPINLOCK_RESUME_ALL_STRAND(%g6, %g1, %g2, %g3, %g4)
.err_resume_bad_guest_err_q:
SET_CPU_IN_ERROR(%g1, %g2)
SET_ERPT_EDESC_EATTR(STRAND_UE_RPT, EATTR_CPU,
EDESC_UE_RESUMABLE, %g1, %g2, %g3)
ba,a .ue_send_resume_exit ! resumable UE
.fatal_reset_dbu: /* this is where we take the system down! */
! don't care how we got here, stop everything now
PRINT("Reset the System: sir 0 %o0=1 fatal error\r\n")
mov SIR_TYPE_FATAL_DBU, %o0
* Disrupting UE error handler epilogue
* The disrupting UE error handlers return here after handling
* NCEEN was not disabled, so disrupting UE handler did not
* mask any UEs. But we could have hit some CEs or other
* disrupting UEs whose trap will be taken when we return.
* Here we queue up the resumable error report to the guest.
* Disrupting UEs use the CE error buffer
PRINT("DIS UE_ERR_RET\r\n")
/* send diag report to vbsc */
add %g6, STRAND_CE_RPT + STRAND_VBSC_ERPT, %g1
add %g6, STRAND_CE_RPT + STRAND_UNSENT_PKT, %g2 ! erpt.unsent flag
* Check if this error needs to be re-routed
* Find which L2 ESR is set and check whether the
* error requires re-routing. If the ESR is non-zero
* but not re-routing, continue as normal.
setx L2_ESR_REROUTED_BITS, %g5, %g4
add %g6, STRAND_CE_RPT, %g6
ldx [%g6 + STRAND_EVBSC_L2_AFSR(0)], %g5
bnz,pt %xcc, .dis_ue_err_ret_rerouting
brnz,pt %g5, .dis_ue_err_ret_no_rerouting
ldx [%g6 + STRAND_EVBSC_L2_AFSR(1)], %g5
bnz,pt %xcc, .dis_ue_err_ret_rerouting
brnz,pt %g5, .dis_ue_err_ret_no_rerouting
ldx [%g6 + STRAND_EVBSC_L2_AFSR(2)], %g5
bnz,pt %xcc, .dis_ue_err_ret_rerouting
brnz,pt %g5, .dis_ue_err_ret_no_rerouting
ldx [%g6 + STRAND_EVBSC_L2_AFSR(3)], %g5
bnz,pn %xcc, .dis_ue_err_ret_rerouting
ba .dis_ue_err_ret_no_rerouting
* re-route an error report
* 1. Get the PA of the error from the diag report
* 2. determine whch guest this PA belongs to
.dis_ue_err_ret_rerouting:
* Need to get the PA from either the DRAM or L2 EAR
setx (L2_ESR_DAU | L2_ESR_DSU), %g3, %g2
be,pt %xcc, .dis_ue_err_ret_rerouting_l2
mulx %g1, EVBSC_DRAM_AFAR_INCR, %g1
add %g1, EVBSC_DRAM_AFAR, %g1
ldx [%g6 + %g1], %g4 ! PA
ba .dis_ue_err_ret_rerouting_find_guest
.dis_ue_err_ret_rerouting_l2:
mulx %g1, EVBSC_L2_AFAR_INCR, %g1
add %g1, EVBSC_L2_AFAR, %g1
ldx [%g6 + %g1], %g4 ! PA
.dis_ue_err_ret_rerouting_find_guest:
* Find the guest which owns this PA.
* For each guest loop through the ra2pa_segment array and check the
* PA against the base/limit
ldx [%g2 + CONFIG_GUESTS], %g2 ! &guests[0]
set NGUESTS - 1, %g3 ! %g3 guest loop counter
! PA2RA_CONV(guestp, paddr, raddr, scr1, scr2)
PA2RA_CONV(%g2, %g4, %g6, %g1, %g5)
! we got a valid RA (%g6), so this is the guest for this PA
add %g2, %g5, %g2 ! guest++
! no guest found for this PA
ba .dis_ue_err_ret_no_rerouting
! is it for the guest we are running on ?
be .dis_ue_err_ret_no_rerouting
! go and finish re-routing this error
* send resumable error report on this CPU
.dis_ue_err_ret_no_rerouting:
ASMCALL_RQ_ERPT(STRAND_CE_RPT, %g1, %g2, %g3, %g4, %g5, %g6, %g7)
#if 1 /* XXXX DEAD CODE */
* Precise UE but ressumable error handler epilogue
* The precise UE error handlers return here after handling the error
* A resumable error will be queued to the affected guest.
ENTRY_NP(precise_ue_res_ret)
PRINT("RES UE_ERR_RET\r\n")
! Call the function to queue the resumable report
ASMCALL_RQ_ERPT(STRAND_UE_RPT, %g1, %g2, %g3, %g4, %g5, %g6, %g7)
.ue_senddiag_resume_exit:
add %g6, STRAND_UE_RPT + STRAND_VBSC_ERPT, %g1 ! erpt.vbsc
set STRAND_UE_RPT + STRAND_UNSENT_PKT, %g2
add %g6, %g2, %g2 ! erpt.unsent flag
mov EVBSC_SIZE, %g3 ! size
! See if CPU is in ERROR and handle the case
IS_CPU_IN_ERROR(%g1, %g2)
! Mark the corresponding strand in error
* Check whether the UE error handler idled the
lduw [%g6 + STRAND_ERR_FLAG], %g2
btst ERR_FLAG_STRANDS_NOT_IDLED, %g2
bnz %xcc, .ue_continue_not_idled ! strands were not idled
bclr ERR_FLAG_STRANDS_NOT_IDLED, %g2 ! reset STRANDS_IDLED
SPINLOCK_RESUME_ALL_STRAND(%g6, %g1, %g2, %g3, %g4)
ba .ue_continue_idled ! flag is not set,
nop ! so skip clearing it
stw %g2, [%g6 + STRAND_ERR_FLAG] ! ..
ldx [%g6 + STRAND_ERR_RET], %g7 ! get return address
brnz,a %g7, .ue_return ! valid: clear it & return
stx %g0, [%g6+ STRAND_ERR_RET] ! ..
! NULL: return from interrupt
retry ! return from UE interrupt
* Precise UE error handler epilogue
* The precise UE error handlers return here after handling the error
* A nonresumable error will be queued to the affected guest.
ENTRY_NP(precise_ue_err_ret)
PRINT("precise_ue_err_ret\r\n")
! queue nonresumable error report
STRAND_ERPT_STRUCT(STRAND_UE_RPT, %g1, %g2)
* Translate error address
* When EATTR_PIO, the error PA is in the RA field of the erpt.
* For others, check the four L2 AFARs to find a non-zero
lduw [%g2 + STRAND_SUN4V_ERPT + ESUN4V_ATTR], %g4
bz,pt %xcc, .precise_ue_err_ret_mem
/* No affected memory region */
stw %g0, [%g2 + STRAND_SUN4V_ERPT + ESUN4V_SZ]
ldx [%g2 + STRAND_SUN4V_ERPT + ESUN4V_ADDR], %g4
CPU_ERR_IO_PA_TO_RA(%g1, %g4, %g4, %g3, %g5, %g6, .precise_ue_err_ret_io)
stw %g4, [%g2 + STRAND_SUN4V_ERPT + ESUN4V_SZ]
ldx [%g2 + STRAND_EVBSC_L2_AFAR(0)], %g4
ldx [%g2 + STRAND_EVBSC_L2_AFAR(1)], %g4
ldx [%g2 + STRAND_EVBSC_L2_AFAR(2)], %g4
ldx [%g2 + STRAND_EVBSC_L2_AFAR(3)], %g4
mov CPU_ERR_INVALID_RA, %g4
VCPU_STRUCT(%g1) /* FIXME: or strand? */
CPU_ERR_PA_TO_RA(%g1, %g4, %g4, %g5, %g6)
stx %g4, [%g2 + STRAND_SUN4V_ERPT + ESUN4V_ADDR]
HVCALL(queue_nonresumable_erpt)
SPINLOCK_RESUME_ALL_STRAND(%g1, %g3, %g4, %g5, %g6)
ba,pt %xcc, nonresumable_error_trap
SET_SIZE(precise_ue_err_ret)
#if STRAND_SUN4V_ERPT != 0
#error "STRAND_SUN4V_ERPT must be 0"
* Queue a resumable error report on this CPU
* %g1 contains pointer to the STRAND structure
* %g2 contains pointer to the error report
* (STRAND_SUN4V_ERPT *must* be 0x0 for this to be called generically)
* XXX If there is no free entry in the resumable error queue
* print a message and return. XXX
ENTRY_NP(queue_resumable_erpt)
ldx [%g1 + CPU_ERRQR_BASE_RA], %g3 ! get q base RA
brnz %g3, 1f ! if base RA is zero, skip
PRINT("RQ NOT ALLOC\r\n")
! The resumable error queue is not allocated/initialized
! simply return. No guest is there to receive it.
* Translate error address
* When EATTR_PIO, the error PA is in the RA field of the erpt.
* For others, check the four L2 AFARs to find a non-zero
lduw [%g2 + STRAND_SUN4V_ERPT + ESUN4V_ATTR], %g4
bz,pt %xcc, .dis_ue_err_ret_mem
/* No affected memory region */
stw %g0, [%g2 + STRAND_SUN4V_ERPT + ESUN4V_SZ]
ldx [%g2 + STRAND_SUN4V_ERPT + ESUN4V_ADDR], %g4
CPU_ERR_IO_PA_TO_RA(%g1, %g4, %g4, %g3, %g5, %g6, .dis_ue_err_ret_io)
stw %g4, [%g2 + STRAND_SUN4V_ERPT + ESUN4V_SZ]
ldx [%g2 + STRAND_EVBSC_L2_AFAR(0)], %g4
ldx [%g2 + STRAND_EVBSC_L2_AFAR(1)], %g4
ldx [%g2 + STRAND_EVBSC_L2_AFAR(2)], %g4
ldx [%g2 + STRAND_EVBSC_L2_AFAR(3)], %g4
mov CPU_ERR_INVALID_RA, %g4
VCPU_STRUCT(%g1) /* FIXME: or strand? */
CPU_ERR_PA_TO_RA(%g1, %g4, %g4, %g5, %g6)
stx %g4, [%g2 + STRAND_SUN4V_ERPT + ESUN4V_ADDR]
* If this is a MEM error report, ensure that it has a valid
ld [%g2 + STRAND_SUN4V_ERPT + ESUN4V_ATTR], %g4 ! attr
ldx [%g2 + STRAND_SUN4V_ERPT + ESUN4V_ADDR], %g4 ! ra
cmp %g4, CPU_ERR_INVALID_RA
! not for this guest, return
mov ERROR_RESUMABLE_QUEUE_TAIL, %g3
ldxa [%g3]ASI_QUEUE, %g5 ! %g5 = rq_tail
add %g5, 0x40, %g6 ! %g6 = rq_next = rq_tail++
ldx [%g1 + CPU_ERRQR_MASK], %g4
and %g6, %g4, %g6 ! %g6 = rq_next mod
mov ERROR_RESUMABLE_QUEUE_HEAD, %g3
ldxa [%g3] ASI_QUEUE, %g4 ! %g4 = rq_head
cmp %g6, %g4 ! head = ++tail?
mov ERROR_RESUMABLE_QUEUE_TAIL, %g3
stxa %g6, [%g3] ASI_QUEUE ! new tail = rq_next
! write up the queue record
ldx [%g1 + CPU_ERRQR_BASE], %g4
add %g5, %g4, %g3 ! %g3 = base + tail
ldx [%g2 + STRAND_SUN4V_ERPT + ESUN4V_G_EHDL], %g4 ! ehdl
ldx [%g2 + STRAND_SUN4V_ERPT + ESUN4V_G_STICK], %g4 ! stick
ld [%g2 + STRAND_SUN4V_ERPT + ESUN4V_EDESC], %g4 ! edesc
ld [%g2 + STRAND_SUN4V_ERPT + ESUN4V_ATTR], %g4 ! attr
ldx [%g2 + STRAND_SUN4V_ERPT + ESUN4V_ADDR], %g4 ! ra
ld [%g2 + STRAND_SUN4V_ERPT + ESUN4V_SZ], %g4 ! sz
lduh [%g2 + STRAND_SUN4V_ERPT + ESUN4V_G_CPUID], %g4 ! cpuid
lduh [%g2 + STRAND_SUN4V_ERPT + ESUN4V_G_SECS], %g4
stuh %g4, [%g3 + 0x26] ! pad/secs
stx %g0, [%g3 + 0x28] ! word5
stx %g0, [%g3 + 0x30] ! word6
stx %g0, [%g3 + 0x38] ! word7
! The resumable error queue is full.
SET_SIZE(queue_resumable_erpt)
* Queue a nonresumable error report on this CPU
* %g2 contains pointer to the error report
* %g1, %g3 - %g6 clobbered
* Check to see what is the guest state:
* switch(guestp->state) {
* case GUEST_STATE_SUSPENDED:
* case GUEST_STATE_NORMAL:
* oldtail = [ERROR_NONRESUMABLE_QUEUE_TAIL]ASI_QUEUE
* qnr_mask =vpup->errqnr_mask;
* newtail = (oldtail + qsize) & mask;
* head = [ERROR_NONRESUMABLE_QUEUE_HEAD]ASI_QUEUE
* if (vcpup->cpu_errqnr_base_ra == 0 || (head == newhead)) {
* case GUEST_STATE_EXITING:
* case GUEST_STATE_STOPPED:
* case GUEST_STATE_UNCONFIGURED:
* This routine just moves the erpt to the queue, it does not
ENTRY_NP(queue_nonresumable_erpt)
! Get the guest structure this vcpu belongs
VCPU2GUEST_STRUCT(%g1, %g5)
! Determine the guest state
lduw [%g5 + GUEST_STATE], %g4
set GUEST_STATE_SUSPENDED, %g3
be,pn %xcc, .check_vcpu_queues
set GUEST_STATE_NORMAL, %g3
be,pn %xcc, .check_vcpu_queues
set GUEST_STATE_EXITING, %g3
be,pn %xcc, .drop_nrq_pkt
set GUEST_STATE_STOPPED, %g3
be,pn %xcc, .drop_nrq_pkt
set GUEST_STATE_UNCONFIGURED, %g3
be,pn %xcc, .drop_nrq_pkt
ldx [%g1 + CPU_ERRQNR_BASE_RA], %g3 ! get q base RA
brz,pn %g3, .queue_nonresumable_bad_queue
mov ERROR_NONRESUMABLE_QUEUE_TAIL, %g3
ldxa [%g3]ASI_QUEUE, %g5 ! %g5 = rq_tail
add %g5, 0x40, %g6 ! %g6 = rq_next = rq_tail++
ldx [%g1 + CPU_ERRQNR_MASK], %g4
and %g6, %g4, %g6 ! %g6 = rq_next mod
mov ERROR_NONRESUMABLE_QUEUE_HEAD, %g3
ldxa [%g3] ASI_QUEUE, %g4 ! %g4 = rq_head
cmp %g6, %g4 ! head = ++tail?
be,pn %xcc, .queue_nonresumable_full_queue
mov ERROR_NONRESUMABLE_QUEUE_TAIL, %g3
* Deliver NR error pkt to guest
stxa %g6, [%g3]ASI_QUEUE ! new tail = rq_next
ldx [%g1 + CPU_ERRQNR_BASE], %g4
add %g5, %g4, %g3 ! %g3 = base + tail
ldx [%g2 + STRAND_SUN4V_ERPT + ESUN4V_G_EHDL], %g4 ! ehdl
ldx [%g2 + STRAND_SUN4V_ERPT + ESUN4V_G_STICK], %g4 ! stick
ld [%g2 + STRAND_SUN4V_ERPT + ESUN4V_EDESC], %g4 ! edesc
ld [%g2 + STRAND_SUN4V_ERPT + ESUN4V_ATTR], %g4 ! attr
ldx [%g2 + STRAND_SUN4V_ERPT + ESUN4V_ADDR], %g4 ! ra
ld [%g2 + STRAND_SUN4V_ERPT + ESUN4V_SZ], %g4 ! sz
lduh [%g2 + STRAND_SUN4V_ERPT + ESUN4V_G_CPUID], %g4 ! cpuid
stuh %g0, [%g3 + 0x26] ! pad
stx %g0, [%g3 + 0x28] ! word5
stx %g0, [%g3 + 0x30] ! word6
stx %g0, [%g3 + 0x38] ! word7
PRINT("queue_nonresumable_erpt: entry enqueued\r\n")
* The guest is not in the proper state to receive pkts
* Drop packet by just returning
PRINT("no guest to deliver NR error pkt. Dropping it\r\n")
.queue_nonresumable_full_queue:
* The nonresumable error queue is full.
PRINT("queue_nonresumable_erpt: nrq full - exiting guest\r\n")
ba,a .queue_nonresumable_reset
.queue_nonresumable_bad_queue:
* The nonresumable error queue is not allocated/initialized
PRINT("NRQ NOT ALLOC - exiting guest\r\n")
.queue_nonresumable_reset:
ba,a .err_resume_bad_guest_err_q
SET_SIZE(queue_nonresumable_erpt)
STRAND_ERPT_STRUCT(STRAND_UE_RPT, %g6, %g5) ! g6->strand, g5->strand.ue_rpt
SPINLOCK_IDLE_ALL_STRAND(%g6, %g1, %g2, %g3, %g4)
! At this point, this is the only strand executing
* Generate a basic error report
LOAD_BASIC_ERPT(%g6, %g5, %g1, %g2)
* Clear unused diag buf fields
stx %g0, [%g5 + STRAND_VBSC_ERPT + EVBSC_SPARC_AFSR]
stx %g0, [%g5 + STRAND_VBSC_ERPT + STRAND_EVBSC_L2_AFSR(0)]
stx %g0, [%g5 + STRAND_VBSC_ERPT + STRAND_EVBSC_L2_AFSR(1)]
stx %g0, [%g5 + STRAND_VBSC_ERPT + STRAND_EVBSC_L2_AFSR(2)]
stx %g0, [%g5 + STRAND_VBSC_ERPT + STRAND_EVBSC_L2_AFSR(3)]
stx %g0, [%g5 + STRAND_VBSC_ERPT + STRAND_EVBSC_DRAM_AFSR(0)]
stx %g0, [%g5 + STRAND_VBSC_ERPT + STRAND_EVBSC_DRAM_AFSR(1)]
stx %g0, [%g5 + STRAND_VBSC_ERPT + STRAND_EVBSC_DRAM_AFSR(2)]
stx %g0, [%g5 + STRAND_VBSC_ERPT + STRAND_EVBSC_DRAM_AFSR(3)]
* Store JBUS error data in error report
DUMP_JBI_SSI(%g6, %g5, %g3, %g4, %g1, %g2, %g7)
* Clear the JBI errors logged in the erpt
STRAND_ERPT_STRUCT(STRAND_UE_RPT, %g6, %g5) ! g6->strand, g5->strand.ue_rpt
ldx [%g5 + STRAND_VBSC_ERPT + EVBSC_JBI_ERR_LOG], %g1
setx JBI_ERR_LOG, %g3, %g2
ldx [%g5 + STRAND_VBSC_ERPT + EVBSC_DIAG_BUF + JS_JBI_ERR_OVF], %g4
setx JBI_ERR_OVF, %g3, %g2
or %g1, %g4, %g1 ! combine primary and overflow for fatal check
CPU_PUSH(%g1, %g2, %g3, %g4) /* save JBI_ERR_LOG|JVI_ERR_OVF */
add %g6, STRAND_UE_RPT + STRAND_VBSC_ERPT, %g1 ! erpt.vbsc
set STRAND_UE_RPT + STRAND_UNSENT_PKT, %g2
add %g6, %g2, %g2 ! erpt.unsent flag
mov EVBSC_SIZE, %g3 ! size
SPINLOCK_RESUME_ALL_STRAND(%g6, %g1, %g2, %g3, %g4)
stx %g0, [%g2 + INT_CTL + INT_CTL_DEV_OFF(IOBDEV_SSIERR)]
* Get saved JBI error log register and check for fatal errors
CPU_POP(%g1, %g2, %g3, %g4)
bnz,pn %xcc, .ue_jbus_err_fatal
* Not a fatal JBI error, we sent the info to vbsc so just
* return to whatever this strand was doing.
* irc_check(uint64_t sparc_ear) [Non-LEAF]
* Checks whether the IRC error is transient or persistent.
* Before we re-read the register in error, we set the irc_ear
* in the CPU struct to the SPARC EAR value, which has the reg#
* and the syndrome. A zero syndrome is not possible for error,
* therefore irc_ear == 0 means IRC trap didn't set it.
* (Note %g0 like other registers can generate errors.)
* If the IRU trap is taken because of a persistent uncorrectable error,
* the IRU trap handler will check the irc_ear field with the SPARC_EAR
* logged. If they are the same, then IRU trap handler clears the
* irc_ear field and returns.
* %g1 - input - SPARC EAR - clobbered
* %g2 - output (RF_TRANSIENT, RF_PERSISTENT)
stx %g1, [%g6 + STRAND_REGERR] ! CPU.irc_ear = sparc EAR (!=0)
mov %g7, %g6 ! save return address
HVCALL(irf_reread) ! %g1 has SPARC EAR
mov %g6, %g7 ! restore return address
STRAND_STRUCT(%g6) ! restore g6->strand
ldx [%g6 + STRAND_REGERR], %g2 ! read STRAND.irc_ear
brz %g2, .irc_ret ! persistent error
! transient error. H/W has fixed it now after the reread
! get back to interrupted program
stx %g0, [%g6 + STRAND_REGERR] ! clear irc_ear
mov RF_TRANSIENT, %g2 ! return transient
* int iru_check(uint64_t sparc_ear) [Non-Leaf]
* Check whether the IRU error is transient, persistent
* or if the integer register file is flaky.
* clear_irf_ue(sparc_ear);
* if (SPARC_ESR.IRU == 0) {
* if (SPARC_EAR == sparc_ear)
* %g1 - input - SPARC EAR - clobbered
* %g2 - output (RF_TRANSIENT, RF_PERSISTENT, RF_FAILURE)
mov %g7, %g6 ! save return address
HVCALL(clear_irf_ue) ! %g1 has SPARC EAR
HVCALL(irf_reread) ! %g1 has SPARC EAR
mov %g6, %g7 ! restore return address
STRAND_STRUCT(%g6) ! restore strand
! check SPARC ESR for IRU error
ldxa [%g0]ASI_SPARC_ERR_STATUS, %g4 ! get SPARC ESR
set SPARC_ESR_IRU, %g3 ! IRU bit
btst %g3, %g4 ! check for IRU
mov RF_TRANSIENT, %g2 ! return transient
ldxa [%g0]ASI_SPARC_ERR_ADDR, %g2 ! get SPARC EAR
ldx [%g5 + STRAND_VBSC_ERPT + EVBSC_SPARC_AFAR], %g1 ! saved EAR
xor %g2, %g1, %g2 ! Are they the same?
andcc %g2, SPARC_EAR_IREG_MASK, %g2 ! (ignore non-register bits)
mov RF_FAILURE, %g2 ! return reg file failure
stxa %g4, [%g0]ASI_SPARC_ERR_STATUS ! yes: clear SPARC ESR
mov RF_PERSISTENT, %g2 ! return persistent error
* void irf_reread(uint64_t sparc_ear) [LEAF function]
* Caller: IRC or IRU handler
* Re-read integer register in error
* %g1 - input - SPARC_EAR
and %g1, SPARC_EAR_IREG_MASK, %g2
srlx %g2, SPARC_EAR_IREG_SHIFT, %g2 ! %g2 has int reg num
! %g2 has the int reg# in error.
! Current window is pointing to the window of the reg in error
! get the register number within the set
and %g2, 0x1f, %g2 ! mask off GL/CWP
cmp %g2, 8 ! is reg# < 8?
bl .glob ! yes, then global reg
! Now re-read the register in error
rd %pc, %g3 ! get reread instr base addr
! an array of instruction blocks indexed by register number to
! reread the non-global register reported in error.
or %g0, %o0, %o0 ! reread %o0
or %g0, %o1, %o1 ! reread %o1
or %g0, %o2, %o2 ! reread %o2
or %g0, %o3, %o3 ! reread %o3
or %g0, %o4, %o4 ! reread %o4
or %g0, %o5, %o5 ! reread %o5
or %g0, %o6, %o6 ! reread %o6
or %g0, %o7, %o7 ! reread %o7
or %g0, %l0, %l0 ! reread %l0
or %g0, %l1, %l1 ! reread %l1
or %g0, %l2, %l2 ! reread %l2
or %g0, %l3, %l3 ! reread %l3
or %g0, %l4, %l4 ! reread %l4
or %g0, %l5, %l5 ! reread %l5
or %g0, %l6, %l6 ! reread %l6
or %g0, %l7, %l7 ! reread %l7
or %g0, %i0, %i0 ! reread %i0
or %g0, %i1, %i1 ! reread %i1
or %g0, %i2, %i2 ! reread %i2
or %g0, %i3, %i3 ! reread %i3
or %g0, %i4, %i4 ! reread %i4
or %g0, %i5, %i5 ! reread %i5
or %g0, %i6, %i6 ! reread %i6
or %g0, %i7, %i7 ! reread %i7
sub %g2, 8, %g2 ! skip globals
sllx %g2, 3, %g2 ! offset = reg# * 8
add %g3, %g2, %g3 ! %g3 = instruction block addr
ldxa [%g0]ASI_SPARC_ERR_EN, %g2 ! save current in %g2
andn %g2, CEEN, %g4 ! disable CEEN
stxa %g4, [%g0] ASI_SPARC_ERR_EN ! ..
jmp %g3 + SZ_INSTR ! jmp to reread register
! restore gl from value in %o0, and restore %o0
wrpr %o0, %gl ! restore %gl
mov %g4, %o0 ! restore %o0
! Here, we check the iregerr field after the reread. If it
! is zero, then we know it is a persistent uncorrectable error.
! If it is nonzero, then we know it is a transient error.
stxa %g2, [%g0] ASI_SPARC_ERR_EN ! restore CEEN
! %g2 has the register number
! now re-read the global register in error
rd %pc, %g3 ! reread instruction base addr
! an array of instructions blocks indexed by global register number
! to reread the global register reported in error.
! %gl points to the error global set
or %g0, %g0, %g0 ! reread %g0 (yay!)
or %g0, %g1, %g1 ! reread %g1
or %g0, %g2, %g2 ! reread %g2
or %g0, %g3, %g3 ! reread %g3
or %g0, %g4, %g4 ! reread %g4
or %g0, %g5, %g5 ! reread %g5
or %g0, %g6, %g6 ! reread %g6
or %g0, %g7, %g7 ! reread %g7
sllx %g2, 3, %g2 ! offset (2 instrs)
add %g3, %g2, %g3 ! %g3 = instruction entry
ldxa [%g0]ASI_SPARC_ERR_EN, %g2 ! save current in %g2
andn %g2, CEEN, %g4 ! disable CEEN
stxa %g4, [%g0] ASI_SPARC_ERR_EN ! ..
mov %o0, %g4 ! save %o0 in %g4
rdpr %gl, %o0 ! save %gl in %o0
and %g1, SPARC_EAR_GL_MASK, %g1 ! get global set from EAR
srlx %g1, SPARC_EAR_GL_SHIFT, %g1 ! %g1 has %gl value
jmp %g3 + SZ_INSTR ! jump to reread global
wrpr %g1, %gl ! set gl to error gl
/* clear_iregerr(sparc_ear) [LEAF Function]
* Clear CPU.iregerr if the IRU register in error == CPU.iregerr
* Return 0 if CPU.iregerr matches, and 1 if no match
* %g2 - output - 0 if CPU.iregerr matches, 1 if no match
ldx [%g6 + STRAND_REGERR], %g3 ! %g3 = STRAND.iregerr
! compare the register number from EAR
xor %g3, %g1, %g3 ! Are they the same?
andcc %g3, SPARC_EAR_IREG_MASK, %g3 ! (ignore non-register bits)
bz %xcc, .ireg_match ! yes, then clear
mov 1, %g2 ! return 1 for no match
! %g4 has CPU.iregerr address
! IRU was taken from IRC trap handler reread attempt
stx %g0, [%g6 + STRAND_REGERR] ! clear STRAND.iregerr
mov %g0, %g2 ! return 0 for ireg match
* void clear_irf_ue(uint64_t sparc_ear)
* Clear the UE in the integer register file
* %g1 - input - SPARC EAR
and %g1, SPARC_EAR_IREG_MASK, %g2
srlx %g2, SPARC_EAR_IREG_SHIFT, %g2 ! %g2 has int reg num
! get the register number within the set
and %g2, 0x1f, %g2 ! mask off GL/CWP
cmp %g2, 8 ! is reg# < 8?
bl .glob_ue ! yes, then global reg
! Now clear the register in error
rd %pc, %g3 ! get clear instr base addr
! an array of instruction blocks indexed by register number to
! clear the non-global register reported in error.
sub %g2, 8, %g2 ! skip globals
sllx %g2, 3, %g2 ! offset = reg# * 8
add %g3, %g2, %g3 ! %g3 = instruction block addr
jmp %g3 + SZ_INSTR ! jmp to clear register
! restore gl from value in %o0, and restore %o0
wrpr %o0, %gl ! restore %gl
mov %g4, %o0 ! restore %o0
! Here, we check the iregerr field after the reread. If it
! is zero, then we know it is a persistent uncorrectable error.
! If it is nonzero, then we know it is a transient error.
! %g2 has the gl + register number
! now re-read the global register in error
rd %pc, %g3 ! get clear instr base addr
! an array of instructions blocks indexed by global register number
! to clear the global register reported in error.
! %gl points to the error global set
mov %g0, %g0 ! clear %g0 (yay!)
sllx %g2, 3, %g2 ! offset (2 instrs)
add %g3, %g2, %g3 ! %g3 = instruction entry
mov %o0, %g4 ! save %o0 in %g4
rdpr %gl, %o0 ! save %gl in %o0
and %g1, SPARC_EAR_GL_MASK, %g2 ! get global set from EAR
srlx %g2, SPARC_EAR_GL_SHIFT, %g2 ! %g2 has %gl value
jmp %g3 + SZ_INSTR ! jump to clear global
wrpr %g2, %gl ! set gl to error gl
* frc_check(uint64_t sparc_ear) [Non-Leaf]
* Check whether the FRC error is transient or persistent.
* Before we re-read the register in error, we set the frc_ear
* in the CPU struct to the SPARC EAR value, which has the reg#
* and the syndrome. A zero syndrome is not possible for error,
* therefore frc_ear == 0 means FRC trap didn't set it.
* (Note %g0 like other registers can generate errors.)
* If the FRU trap is taken because of a persistent uncorrectable error,
* the FRU trap handler will check the frc_ear field with the SPARC_EAR
* logged. If they are the same, then FRU trap handler clears the
* frc_ear field and returns.
* %g1 - input - SPARC EAR - clobbered
* %g2 - output (RF_TRANSIENT, RF_PERSISTENT)
stx %g1, [%g6 + STRAND_REGERR] ! strand.frc_ear = sparc EAR (!=0)
* It is possible that FPRS.FEF was disabled when we took the
* disrupting trap caused by the FP CE. We must ensure that FPRS.FEF
* is enabled before calling frf_reread().
* Note that the Sparc V9 spec mandates that PSTATE.PEF be enabled
* when we take a trap if there is an FPU present. As this error
* condition can only occur with an FPU we do not need to verify
btst FPRS_FEF, %g5 ! FPRS.FEF set ?
bz,a,pn %xcc, 1f ! no: set it
wr %g5, FPRS_FEF, %fprs ! yes: annulled
mov %g7, %g6 ! save return address
HVCALL(frf_reread) ! %g1 has SPARC EAR,
wr %g5, %g0, %fprs ! restore FPRS
mov %g6, %g7 ! restore return address
STRAND_ERPT_STRUCT(STRAND_CE_RPT, %g6, %g5) ! g6->strand, g5->strand.ce_rpt
ldx [%g6 + STRAND_REGERR], %g2 ! read strand.frc_ear
brz %g2, .frc_ret ! persistent error
! transient error. H/W has fixed it now after the reread
! get back to interrupted program
stx %g0, [%g6 + STRAND_REGERR] ! clear frc_ear
mov RF_TRANSIENT, %g2 ! return transient
* fru_check(uint64_t sparc_ear) [Non-Leaf]
* Check whether the FRU error is transient or persistent
* or if the floating point register file is failing.
* clear_frf_ue(sparc_ear);
* if (SPARC_ESR.FRU == 0) {
* if (SPARC_EAR == sparc_ear)
* %g1 - input - SPARC EAR - clobbered
* %g2 - output (RF_TRANSIENT, RF_PERSISTENT, RF_FAILURE)
mov %g7, %g6 ! save return address
HVCALL(clear_frf_ue) ! %g1 has SPARC EAR
HVCALL(frf_reread) ! %g1 has SPARC EAR
mov %g6, %g7 ! restore return address
STRAND_STRUCT(%g6) ! restore strand
! check SPARC ESR for FRU error
ldxa [%g0]ASI_SPARC_ERR_STATUS, %g4 ! get SPARC ESR
set SPARC_ESR_FRU, %g3 ! FRU bit
btst %g3, %g4 ! check for FRU
mov RF_TRANSIENT, %g2 ! return transient
ldxa [%g0]ASI_SPARC_ERR_ADDR, %g2 ! get SPARC EAR
ldx [%g5 + STRAND_VBSC_ERPT + EVBSC_SPARC_AFAR], %g1 ! saved EAR
xor %g2, %g1, %g2 ! Are they the same?
andcc %g2, SPARC_EAR_FPREG_MASK, %g2 ! (ignore non-register bits)
mov RF_FAILURE, %g2 ! return reg file failure
stxa %g4, [%g0]ASI_SPARC_ERR_STATUS ! yes: clear SPARC ESR
mov RF_PERSISTENT, %g2 ! return persistent
* IRF Uncorrectible ECC Error
* if (clear_iregerr(sparc_ear) == MATCH from IRC) {
* if (iru_check(sparc_ear) == RF_PERSISTENT) {
* CPU.status = mark CPU in ERROR;
* if ((CPUnext = avail(partID)) != NULL) {
* x_call(CPUnext, I_AM_IN_ERROR);
* q_service_error_report(spi);
* stop_self(); - watchdog reset later?
* q_sun4v_error_report(nrq);
* q_service_error_report(spi);
* jmp nonresumable_error trap handler
* frf_reread(uint64_t sparc_ear) [LEAF function]
* Reread the FRF register in error.
* %g1 - input - SPARC EAR
and %g1, SPARC_EAR_FPREG_MASK, %g2
srlx %g2, SPARC_EAR_FPREG_SHIFT, %g2 ! %g2 has 6-bit fpreg number
! Now reread the register in error
rd %pc, %g3 ! %g3 = base address
! an array of instruction blocks indexed by register number to
! reread the floating-point register reported in error
! The first 32 entries use single-precision register
! The next 32 entries reread the double-precision register
fmovs %f0, %f0 ! reread %f0
fmovs %f1, %f1 ! reread %f1
fmovs %f2, %f2 ! reread %f2
fmovs %f3, %f3 ! reread %f3
fmovs %f4, %f4 ! reread %f4
fmovs %f5, %f5 ! reread %f5
fmovs %f6, %f6 ! reread %f6
fmovs %f7, %f7 ! reread %f7
fmovs %f8, %f8 ! reread %f8
fmovs %f9, %f9 ! reread %f9
fmovs %f10, %f10 ! reread %f10
fmovs %f11, %f11 ! reread %f11
fmovs %f12, %f12 ! reread %f12
fmovs %f13, %f13 ! reread %f13
fmovs %f14, %f14 ! reread %f14
fmovs %f15, %f15 ! reread %f15
fmovs %f16, %f16 ! reread %f16
fmovs %f17, %f17 ! reread %f17
fmovs %f18, %f18 ! reread %f18
fmovs %f19, %f19 ! reread %f19
fmovs %f20, %f20 ! reread %f20
fmovs %f21, %f21 ! reread %f21
fmovs %f22, %f22 ! reread %f22
fmovs %f23, %f23 ! reread %f23
fmovs %f24, %f24 ! reread %f24
fmovs %f25, %f25 ! reread %f25
fmovs %f26, %f26 ! reread %f26
fmovs %f27, %f27 ! reread %f27
fmovs %f28, %f28 ! reread %f28
fmovs %f29, %f29 ! reread %f29
fmovs %f30, %f30 ! reread %f30
fmovs %f30, %f31 ! reread %f31
! double precision register pairs, reread both of them on errors
fmovd %f32, %f32 ! reread %f32
fmovd %f32, %f32 ! reread %f32
fmovd %f34, %f34 ! reread %f34
fmovd %f34, %f34 ! reread %f34
fmovd %f36, %f36 ! reread %f36
fmovd %f36, %f36 ! reread %f36
fmovd %f38, %f38 ! reread %f38
fmovd %f38, %f38 ! reread %f38
fmovd %f40, %f40 ! reread %f40
fmovd %f40, %f40 ! reread %f40
fmovd %f42, %f42 ! reread %f42
fmovd %f42, %f42 ! reread %f42
fmovd %f44, %f44 ! reread %f44
fmovd %f44, %f44 ! reread %f44
fmovd %f46, %f46 ! reread %f46
fmovd %f46, %f46 ! reread %f46
fmovd %f48, %f48 ! reread %f48
fmovd %f48, %f48 ! reread %f48
fmovd %f50, %f50 ! reread %f50
fmovd %f50, %f50 ! reread %f50
fmovd %f52, %f52 ! reread %f52
fmovd %f52, %f52 ! reread %f52
fmovd %f54, %f54 ! reread %f54
fmovd %f54, %f54 ! reread %f54
fmovd %f56, %f56 ! reread %f56
fmovd %f56, %f56 ! reread %f56
fmovd %f58, %f58 ! reread %f58
fmovd %f58, %f58 ! reread %f58
fmovd %f60, %f60 ! reread %f60
fmovd %f60, %f60 ! reread %f60
fmovd %f62, %f62 ! reread %f62
fmovd %f62, %f62 ! reread %f62
! %g2 has freg number, %g3 has base address-4
sllx %g2, 3, %g2 ! offset = freg# * 8
add %g3, %g2, %g3 ! %g3 = instruction block addr
ldxa [%g0]ASI_SPARC_ERR_EN, %g2 ! save current in %g2
andn %g2, CEEN, %g4 ! disable CEEN
stxa %g4, [%g0] ASI_SPARC_ERR_EN ! ..
jmp %g3 + SZ_INSTR ! jmp to reread register
stxa %g2, [%g0] ASI_SPARC_ERR_EN ! restore CEEN
* clear_fregerr(sparc_ear) [LEAF Function]
* Clear cpu.fregerr if the FRU register in error == cpu.fregerr
* Return 0 if cpu.fregerr matches, and 1 if no match
* %g2 - output - 0 if cpu.fregerr matches, 1 if no match
ldx [%g6 + STRAND_REGERR], %g3 ! %g3 = strand.fregerr
! get register number from EAR
xor %g3, %g1, %g3 ! Are they the same?
andcc %g3, SPARC_EAR_FPREG_MASK, %g3 ! (ignore non-register bits)
bz %xcc, .freg_match ! yes, then clear
mov 1, %g2 ! return 1 for no match
! %g4 has cpu.fregerr address
! FRU was taken from FRC trap handler reread attempt
stx %g0, [%g6 + STRAND_REGERR] ! clear strand.fregerr
mov %g0, %g2 ! return 0 for freg match
* clear_frf_ue(uint64_t sparc_ear) [LEAF function]
* Clear the UE in the floating-point register file
and %g1, SPARC_EAR_FPREG_MASK, %g2
srlx %g2, SPARC_EAR_FPREG_SHIFT, %g2 ! %g2 has 6-bit fpreg number
! Now clear the register in error
rd %pc, %g3 ! %g3 = base address
! an array of instruction blocks indexed by register number to
! clear the floating-point register reported in error
! The first 32 entries use single-precision register
! The next 32 entries clear the double-precision register
! double precision register pairs, clear both of them on errors
! %g2 has freg number, %g3 has base address-4
sllx %g2, 3, %g2 ! offset = freg# * 8
add %g3, %g2, %g3 ! %g3 = instruction block addr
jmp %g3 + SZ_INSTR ! jmp to clear register
* FRC Uncorrectible ECC Error
* FRU Error Handler: Check for persistent error
* if (fru_check(sparc_ear) == RF_TRANSIENT) {
* q_sun4v_error_report(nrq);
* q_service_error_report(spi);
* jmp nonresumable_error trap handler;
* CPU.status = mark CPU in ERROR;
* if ((CPUnext = avail(partID)) != NULL) {
* x_call(CPUnext, I_AM_IN_ERROR);
* q_service_error_report(spi);
* stop_self(); causes watchdog reset later?
* Handler to set bit(s) in the SPARC Error Enable Register
* Called to get handler callback address (avoid relocation problems)
ENTRY_NP(err_set_sparc_bits)
RETURN_HANDLER_ADDRESS(%g2) ! in %g2
* Callback from interrupt:
* This will re-enable the Sparc interrupts.
.err_set_sparc_bits: /* This is the actual function entry */
ldxa [%g0]ASI_SPARC_ERR_STATUS, %g3 ! SPARC afsr
btst %g1, %g3 ! is a CE pending?
bz .err_set_sparc_1 ! no:
or %g1, %g2, %g1 ! yes: include PRIV
and %g3, %g1, %g3 ! just the CE bits
stxa %g3, [%g0]ASI_SPARC_ERR_STATUS ! clear SPARC CE afsr bits
lduw [%g3 + STRAND_ERR_FLAG], %g1 ! installed flags
bclr ERR_FLAG_SPARC, %g1 ! reset SPARC ESR
stw %g1, [%g3 + STRAND_ERR_FLAG] ! ..
ldxa [%g0]ASI_SPARC_ERR_EN, %g3 ! get current
or %g3, %g5, %g3 ! set bit(s)
stxa %g3, [%g0]ASI_SPARC_ERR_EN ! store back
SET_SIZE(err_set_sparc_bits)
* Handler to set bit(s) in the L2 Error Enable Register
* This will re-enable the L2/DRAM interrupts.
* Called to get handler callback address (avoid relocation problems)
ENTRY_NP(err_set_l2_bits)
RETURN_HANDLER_ADDRESS(%g2) ! in %g2
* Callback from interrupt:
.err_set_l2_bits: /* This is the actual function entry */
and %g2, NO_L2_BANKS - 1, %g6 ! bank #
setx DRAM_ESR_CE_BITS | DRAM_ESR_MEC, %g1, %g2
setx DRAM_ESR_BASE, %g1, %g3 ! DRAM base
sllx %g6, DRAM_BANK_SHIFT, %g4 ! + bank offset
ldx [%g3 + %g4], %g1 ! get ESR[bank]
and %g1, %g2, %g1 ! reset CE bits only
setx L2_ESR_CE_BITS | L2_ESR_VEC, %g1, %g2
setx L2_ESR_BASE, %g1, %g3 ! L2 base
sll %g6, L2_BANK_SHIFT, %g4 ! + bank offset
ldx [%g3 + %g4], %g1 ! get ESR[bank]
and %g1, %g2, %g1 ! reset CE bits only
mov ERR_FLAG_L2DRAM, %g1 ! L2DRAM flag
sll %g1, %g6, %g1 ! << bank#
lduw [%g3 + STRAND_ERR_FLAG], %g2 ! installed flags
bclr %g1, %g2 ! reset L2DRAM[bank]
stw %g2, [%g3 + STRAND_ERR_FLAG] ! ..
BSET_L2_BANK_EEN(%g6, %g5, %g2, %g3) ! L2 Bank EEN[%g6] |= %g5
SET_SIZE(err_set_l2_bits)
* Poll to detect errors that did not cause an interrupt for one
* Most common cause: L2/DRAM error from prefetch.
* Called to get handler callback address (avoid relocation problems)
ENTRY_NP(err_poll_daemon)
RETURN_HANDLER_ADDRESS(%g2) ! in %g2
* Callback from interrupt:
* %g3: Interrupt Tick Time
* Get strand, CE buffer in %g6-5, they are safe across calls
stx %g3, [%g6 + STRAND_ERR_POLL_ITT] ! save interrupt tick time
stx %g7, [%g6 + STRAND_ERR_POLL_RET] ! save return address
* Look for Sparc errors: test only,
* the error handler will do the work
ldxa [%g0]ASI_SPARC_ERR_STATUS, %g4 ! SPARC afsr
UE_CHECK(SPARC_UE_MEU_BITS, L2_ESR_UE_BITS, %g4, %g1, %g2, %g3)
bz %xcc, .err_poll_no_ue ! no
HVCALL(ue_poll_entry) ! yes: go process
ba,a .err_poll_sparc ! and re-check Sparc status
CE_CHECK(%g6, %g4, %g1, %g2, %g3) ! cpup, spesr,
bz %xcc, .err_poll_no_ce ! no
HVCALL(ce_poll_entry) ! yes
ba,a .err_poll_sparc ! go re-check Sparc status
STRAND2CONFIG_STRUCT(%g6, %g1) ! ->config
ldx [%g1 + CONFIG_CE_POLL_TIME], %g1 ! g1 = time interval
brz %g1, 9f ! disabled: branch
ldx [%g6 + STRAND_ERR_POLL_ITT], %g2 ! this interrupt tick time
add %g1, %g2, %g1 ! abs time for next poll
HVCALL(err_poll_daemon) ! g2 = handler address
clr %g3 ! g3 = arg 0 : n/a
clr %g4 ! g4 = arg 1 : n/a
HVCALL(cyclic_add_abs) /* ( abs_tick, address, arg0, arg1 ) */
ldx [%g6 + STRAND_ERR_POLL_RET], %g7 ! restore return address
SET_SIZE(err_poll_daemon)
* Function to start error polling daemon:
* 1 - failed (already running)
ENTRY_NP(err_poll_daemon_start)
stx %g7, [%g6 + STRAND_ERR_POLL_RET] ! save return address
lduw [%g6 + STRAND_ERR_FLAG], %g2
btst ERR_FLAG_POLLD, %g2 ! handler flags
bnz,a %xcc, 9f ! poll deamon installed?
mov 1, %g1 ! yes: return "running"
bset ERR_FLAG_POLLD, %g2 ! set it
stw %g2, [%g6 + STRAND_ERR_FLAG] ! store
* Install the callback handler: just start at now + ce_poll_time
STRAND2CONFIG_STRUCT(%g6, %g1) ! ->config
ldx [%g1 + CONFIG_CE_POLL_TIME], %g1 ! g1 = cycle time in ticks
HVCALL(err_poll_daemon) ! g2 = handler address
clr %g3 ! g3 = arg 0 : error bits
HVCALL(cyclic_add_rel) /* ( del_tick, address, arg0, arg1 ) */
ldx [%g6 + STRAND_ERR_POLL_RET], %g7 ! restore return address
clr %g1 ! status = success
SET_SIZE(err_poll_daemon_start)
#if EVBSC_L2_AFSR_INCR == 8
#define EVBSC_L2_AFSR_SHIFT 3
#error "EVBSC_L2_AFSR_INCR is not 8"
#if EVBSC_L2_AFAR_INCR == 8
#define EVBSC_L2_AFAR_SHIFT 3
#error "EVBSC_L2_AFAR_INCR is not 8"
* This function determines if an error is transient, sticky or
* permanent. We only check disposition on Memory CE's. Hence,
* we only work the L2 error registers.
* The algorithm to classify the error is as follows:
* 1) Displacement flush the E$ line corresponding to %addr.
* The first ldxa guarantees that the %addr is no longer in
* M, O, or E (goes to I or S (if instruction fetch also
* 2) "Write" the data using a ldx %addrm %scr CAS %addr,%scr,%scr.
* The casxa guarantees a transition from I to M or S to M.
* There are two possibilities that the sequence does not act
* - the line is displaced between the ld and the cas:
* we still have the correct value in %scr and the cas will
* reload the line - this is OK since the ld was to get the
* value, no to get the line in the cache.
* - the line is written between the ld and the cas:
* the intent to modify the line has effectively succeeded
* 3) Displacement flush the E$ line corresponding to %addr.
* The second ldxa pushes the M line out of the ecache,
* into the writeback buffers, on the way to memory.
* 4) The "membar #Sync" pushes the cache line out of
* the writeback buffers onto the bus, on the way to
* XXX - Need to handle race with HW scrubber
ENTRY_NP(err_determine_disposition)
CPU_PUSH(%g7, %g4, %g5, %g6) ! save return address
! Read and save the current enable
GET_L2_BANK_EEN(%g6, %g5, %g4)
CPU_PUSH(%g5, %g3, %g4, %g2) ! save for later
BCLR_L2_BANK_EEN(%g6, CEEN, %g4, %g3)
! get err address into %g1
add %g1, STRAND_CE_RPT + STRAND_VBSC_ERPT, %g1
sllx %g6, EVBSC_L2_AFAR_SHIFT, %g4
add %g4, EVBSC_L2_AFAR, %g2
! Mask AFAR to get only valid bits
and %g1, ~L2_EAR_DRAM_MASK, %g1
! l2_flush_line garbles %g6. Save %g6 which
CPU_PUSH(%g6, %g3, %g4, %g2) ! save for later
* displace and cause a write back
* Niagara works differently than previous generations.
* On previous generations, a cas will mark the line dirty,
* regardless of the success of the compare.
* In Niagara, the line only gets mark dirty if the swap occurs.
* Hence, we need to first load the value and store it back via the cas
! push cache line out of the write back buffers
CPU_POP(%g6, %g2, %g3, %g4)
* Read the errs registers again and compare them with our saved
* version. If they are the same, then error is persistent
setx L2_ESR_DRAM_CE_BITS, %g3, %g2
setx L2_ESR_BASE, %g3, %g5 ! L2 base
sll %g6, L2_BANK_SHIFT, %g4 ! + bank offset
ldx [%g5 + %g4], %g5 ! get ESR[bank]
and %g5, %g2, %g5 ! compare only CEs
add %g3, STRAND_CE_RPT + STRAND_VBSC_ERPT, %g3
sllx %g6, EVBSC_L2_AFSR_SHIFT, %g4
add %g4, EVBSC_L2_AFSR, %g4
ldx [%g3 + %g4], %g4 ! orig AFSR
and %g4, %g2, %g4 ! only CEs
! clear the disposition to have none
stx %g2, [%g3 + EVBSC_DIAG_BUF + DRAM_DISPOSITION]
! now check afar and see if same.
! %g1 still contains the stored afar
setx L2_EAR_BASE, %g4, %g5 ! L2 base
sll %g6, L2_BANK_SHIFT, %g4 ! + bank offset
and %g4, ~L2_EAR_DRAM_MASK, %g4
stx %g4, [%g3 + EVBSC_DIAG_BUF + DRAM_DISPOSITION]
sllx %g6, EVBSC_L2_AFSR_SHIFT, %g4
add %g4, EVBSC_L2_AFSR, %g4
ldx [%g3 + %g4], %g4 ! orig AFSR
setx L2_ESR_BASE, %g2, %g5 ! L2 base
sll %g6, L2_BANK_SHIFT, %g2 ! + bank offset
stx %g4, [%g5 + %g2] ! clear ESR[bank]
* Read data again. data should now come from memory. We check
* for errors. If the saved version and new errs registers are the
* same then it is a stuck bit
* %g1 still contains our stored afar
setx L2_ESR_DRAM_CE_BITS, %g5, %g2
setx L2_ESR_BASE, %g4, %g5 ! L2 base
sll %g6, L2_BANK_SHIFT, %g4 ! + bank offset
ldx [%g5 + %g4], %g5 ! get ESR[bank]
and %g5, %g2, %g5 ! compare only CEs
sllx %g6, EVBSC_L2_AFSR_SHIFT, %g4
add %g4, EVBSC_L2_AFSR, %g4
ldx [%g3 + %g4], %g4 ! orig AFSR
and %g4, %g2, %g4 ! only CEs
! now check afar and see if same.
! %g1 still contains the stored afar
setx L2_EAR_BASE, %g4, %g5 ! L2 base
sll %g6, L2_BANK_SHIFT, %g4 ! + bank offset
and %g4, ~L2_EAR_DRAM_MASK, %g4
ldx [%g3 + EVBSC_DIAG_BUF + DRAM_DISPOSITION], %g2
stx %g2, [%g3 + EVBSC_DIAG_BUF + DRAM_DISPOSITION]
CPU_POP(%g5, %g2, %g3, %g4)
sllx %g6, L2_BANK_SHIFT, %g3 ! bank offset
add %g2, %g3, %g2 ! bank address
stx %g5, [%g2] ! restore value
CPU_POP(%g7, %g1, %g2, %g3)
SET_SIZE(err_determine_disposition)
* All other strands are idle
* - search for another "good" strand
* - flag as halted (bit mask)
* - Remove cyclic (Error Daemon)
* - handoff interrupt steering
* - notify good strand to finish rest of work
* - send resumable error to guest
* %g6 should not be clobbered
ENTRY_NP(strand_in_error)
! Remove this cpu from the active bitmask and add it to halted
ldub [%g5 + STRAND_ID], %g5
ROOT_STRUCT(%g2) ! config ptr
! clear this strand from the active list
ldx [%g2 + CONFIG_STACTIVE], %g3
stx %g3, [%g2 + CONFIG_STACTIVE]
! set this cpu in the halted list
ldx [%g2 + CONFIG_STHALT], %g3
stx %g3, [%g2 + CONFIG_STHALT]
! find another idle strand for re-targetting
ldx [%g2 + CONFIG_STIDLE], %g3
bnz,a %xcc, .found_a_strand
bne,pn %xcc, .find_strand
* No usable active strands are left in the
* system, force host exit
* handoff L2 Steering CPU
* If we are the steering cpu, migrate it to our chosen one
!! %g6 - target strand ID
setx L2_CONTROL_REG, %g3, %g4
ldx [%g4], %g2 ! current setting
srlx %g2, L2_ERRORSTEER_SHIFT, %g3
and %g3, (NSTRANDS - 1), %g3
cmp %g3, %g5 ! is this steering strand ?
! It is the L2 Steering strand. Migrate responsibility to tgt strand
sllx %g3, L2_ERRORSTEER_SHIFT, %g3
andn %g3, %g2, %g2 ! remove this strand
sllx %g6, L2_ERRORSTEER_SHIFT, %g3
!! %g2 - target strand ID
STRAND_PUSH(%g1, %g3, %g4)
STRAND_PUSH(%g2, %g3, %g4)
HVCALL(ssi_intr_redistribution)
* XXX err_poll_daemon (collapse into heartbeat?)
* Disable heartbeat interrupts if they're on this cpu.
* cpu_in_error_finish will invoke heartbeat_enable on the
* remote cpu if the heartbeat was disabled.
STRAND_PUSH(%g1, %g3, %g4)
STRAND_PUSH(%g2, %g3, %g4)
HVCALL(heartbeat_disable)
* if this guest owns a fire bus, redirect
ldx [%g4 + CONFIG_PCIE_BUSSES], %g4
ldx [%g4 + PCIE_DEVICE_GUESTP], %g5
ldx [%g4 + PCIE_DEVICE_GUESTP + PCIE_DEVICE_SIZE], %g5
STRAND_PUSH(%g1, %g3, %g4)
STRAND_PUSH(%g2, %g3, %g4)
HVCALL(fire_intr_redistribution)
STRAND_PUSH(%g1, %g3, %g4)
STRAND_PUSH(%g2, %g3, %g4)
HVCALL(fire_err_intr_redistribution)
STRAND_PUSH(%g1, %g3, %g4)
STRAND_PUSH(%g2, %g3, %g4)
HVCALL(vdev_intr_redistribution)
* Now pick another VCPU in this guest to target the erpt
* Ensure that the VCPU is not bound to the strand in error
add %g2, GUEST_VCPUS, %g2
!! %g1 - this vcpu struct
!! %g2 - array of vcpus in guest
ldx [%g2], %g4 ! vcpu struct
brz,pn %g4, .find_cpu_continue
be,pn %xcc, .find_cpu_continue
! check whether this CPU is running guest code ?
ldx [%g4 + CPU_STATUS], %g6
cmp %g6, CPU_STATE_RUNNING
bne,pt %xcc, .find_cpu_continue
! check the error queues.. if not set, not a good candidate
ldx [%g4 + CPU_ERRQR_BASE], %g6
brz,pt %g6, .find_cpu_continue
* find the strand this vcpu is ON, make sure it is idle
* NOTE: currently this check is not necessary, more
* likely when we have sub-strand scheduling
!! %g1 - this vcpu struct
!! %g2 - curr vcpu in guest vcpu array
!! %g4 - target vcpus struct
STRAND_STRUCT(%g5) ! this strand
ldx [%g4 + CPU_STRAND], %g6 ! vcpu->strand
be,pn %xcc, .find_cpu_continue
! check if the target strand is IDLE
ldub [%g6 + STRAND_ID], %g6 ! vcpu->strand->id
VCPU2ROOT_STRUCT(%g1, %g5)
ldx [%g5 + CONFIG_STIDLE], %g5
bnz,pt %xcc, .found_a_cpu
add %g2, GUEST_VCPUS_INCR, %g2
bne,pn %xcc, .find_cpu_loop
! If we got here, we didn't find a good tgt cpu
! do not send an erpt, exit the guest
!! %g4 - target vcpu struct
* This cpu has most of the information to send to the Guest.
* We copy from this cpu err rpt to the tgt's err rpt
STRAND_STRUCT(%g1) ! this strand
STRAND2ERPT_STRUCT(STRAND_UE_RPT, %g1, %g1)
ldx [%g4 + CPU_STRAND], %g2 ! tgt_vcpu->strand
STRAND2ERPT_STRUCT(STRAND_CE_RPT, %g2, %g3)
! copy info to tgt cpu ce err buf
ldx [%g1 + STRAND_SUN4V_ERPT + ESUN4V_G_EHDL], %g4 ! ehdl
stx %g4, [%g3 + STRAND_SUN4V_ERPT + ESUN4V_G_EHDL]
ldx [%g1 + STRAND_SUN4V_ERPT + ESUN4V_G_STICK], %g4 ! stick
stx %g4, [%g3 + STRAND_SUN4V_ERPT + ESUN4V_G_STICK]
ld [%g1 + STRAND_SUN4V_ERPT + ESUN4V_EDESC], %g4 ! edesc
st %g4, [%g3 + STRAND_SUN4V_ERPT + ESUN4V_EDESC]
ld [%g1 + STRAND_SUN4V_ERPT + ESUN4V_ATTR], %g4 ! attr
st %g4, [%g3 + STRAND_SUN4V_ERPT + ESUN4V_ATTR]
ldx [%g1 + STRAND_SUN4V_ERPT + ESUN4V_ADDR], %g4 ! ra
stx %g4, [%g3 + STRAND_SUN4V_ERPT + ESUN4V_ADDR]
ld [%g1 + STRAND_SUN4V_ERPT + ESUN4V_SZ], %g4 ! sz
st %g4, [%g3 + STRAND_SUN4V_ERPT + ESUN4V_SZ]
lduh [%g1 + STRAND_SUN4V_ERPT + ESUN4V_G_CPUID], %g4 ! cpuid
stuh %g4, [%g3 + STRAND_SUN4V_ERPT + ESUN4V_G_CPUID]
lduh [%g1 + STRAND_SUN4V_ERPT + ESUN4V_G_SECS], %g4
stuh %g4, [%g3 + STRAND_SUN4V_ERPT + ESUN4V_G_SECS]
* Send a xcall to the target strand so it can finish the work
ldub [%g2 + STRAND_ID], %g6 ! tgt strand id
sllx %g6, INT_VEC_DIS_VCID_SHIFT, %g5
or %g5, VECINTR_CPUINERR, %g5
stxa %g5, [%g0]ASI_INTR_UDB_W
SPINLOCK_RESUME_ALL_STRAND(%g6, %g1, %g2, %g3, %g4)
! remove self from idle list
ldub [%g1 + STRAND_ID], %g6 /* phys id */
ldx [%g6 + CONFIG_STIDLE], %g5
stx %g5, [%g6 + CONFIG_STIDLE]
ldub [%g1 + STRAND_ID], %g6 /* phys id */
INT_VEC_DSPCH_ONE(INT_VEC_DIS_TYPE_IDLE, %g6, %g3, %g4)
* Paranoia!! If we get here someone else resumed this strand
* hvabort to catch the mistake
SET_SIZE(strand_in_error)
setx JBI_ERR_LOG, %g1, %g2
* Clear the INT_CTL.MASK bit for the SSI
stx %g0, [%g2 + INT_CTL + INT_CTL_DEV_OFF(IOBDEV_SSIERR)]
* re-route an error report (cont'd)
* 3. select one of the active CPUs for that guest
* 4. Copy the data from the error erport into that
* 5. Send a VECINTR_ERROR_XCALL to that CPU
/* FIXME: re-whack this for vcpu/strand split */
ENTRY_NP(cpu_reroute_error)
* find first live cpu in guest->vcpus
* Then deliver the error to that vcpu, and interrupt
* the strand it is running on to make that happen.
add %g2, GUEST_VCPUS, %g2
be,pn %xcc, cpu_reroute_error_exit
mulx %g3, GUEST_VCPUS_INCR, %g5
! check whether this CPU is running guest code ?
ldx [%g1 + CPU_STATUS], %g5
cmp %g5, CPU_STATE_RUNNING
ldx [%g1 + CPU_STRAND], %g1
* It is possible that the CPUs rerouted data is already in use.
* We use the rerouted_addr field as a spinlock. The target CPU
* will set this to 0 after reading the error data allowing us
* to re-use the rerouting fields.
* See cpu_err_rerouted() below.
set STRAND_REROUTED_ADDR, %g2
! get the data out of the current STRAND's ce_rpt buf and store
! in the target STRAND struct
STRAND_ERPT_STRUCT(STRAND_CE_RPT, %g6, %g5) ! g6->strand, g5->strand.ce_rpt
ldx [%g5 + STRAND_SUN4V_ERPT + ESUN4V_G_EHDL], %g6
set STRAND_REROUTED_EHDL, %g4
lduw [%g5 + STRAND_SUN4V_ERPT + ESUN4V_ATTR], %g6
set STRAND_REROUTED_ATTR, %g4
ldx [%g5 + STRAND_SUN4V_ERPT + ESUN4V_G_STICK], %g6
! STICK is probably not necssary. I doubt if FMA checks
! both EHDL/STICK when looking for duplicate reports,
! but it doesn't kill us to do it.
set STRAND_REROUTED_STICK, %g4
! send an x-call to the target CPU
ldub [%g1 + STRAND_ID], %g3
sllx %g3, IVDR_THREAD, %g3
mov VECINTR_ERROR_XCALL, %g5
stxa %g3, [%g0]ASI_INTR_UDB_W
! error is re-routed, get out of here
SPINLOCK_RESUME_ALL_STRAND(%g6, %g1, %g2, %g3, %g4)
ldx [%g6 + STRAND_ERR_RET], %g7 ! get return address
brnz,a %g7, .ue_return ! valid: clear it & return
stx %g0, [%g6 + STRAND_ERR_RET] ! ..
SET_SIZE(cpu_reroute_error)
* An error has been re-routed to this STRAND.
* The EHDL/ADDR/STICK/ATTR have been stored in the STRAND struct
* by the STRAND that originally detected the error.
* Note: STICK may not be strictly necessary
ENTRY_NP(cpu_err_rerouted)
STRAND_ERPT_STRUCT(STRAND_CE_RPT, %g6, %g5) ! g6->strand, g5->strand.ce_rpt
#ifdef DEBUG_ERROR_REROUTING
PRINT("Error Re-routed to CPU strand ");
ldub [%g6 + STRAND_ID], %g4
set STRAND_REROUTED_EHDL, %g4
stx %g4, [%g5 + STRAND_SUN4V_ERPT + ESUN4V_G_EHDL]
set STRAND_REROUTED_STICK, %g4
stx %g4, [%g5 + STRAND_SUN4V_ERPT + ESUN4V_G_STICK]
set STRAND_REROUTED_ATTR, %g4
stw %g4, [%g5 + STRAND_SUN4V_ERPT + ESUN4V_ATTR]
! keep ADDR after EHDL/STICK/ATTR to avoid race
set STRAND_REROUTED_ADDR, %g4
! Clear the strand->rerouted-addr field now to let other
! Translate the PA to a guest RA
CPU_ERR_PA_TO_RA(%g6, %g1, %g4, %g2, %g3)
stx %g1, [%g5 + STRAND_SUN4V_ERPT + ESUN4V_ADDR]
ldub [%g6 + CPU_VID], %g4 /* guest cpuid */
stuh %g4, [%g5 + STRAND_SUN4V_ERPT + ESUN4V_G_CPUID]
set EDESC_UE_RESUMABLE, %g4
stw %g4, [%g5 + STRAND_SUN4V_ERPT + ESUN4V_EDESC]
st %g4, [%g5 + STRAND_SUN4V_ERPT + ESUN4V_SZ]
* gueue a resumable error report and return
ASMCALL_RQ_ERPT(STRAND_CE_RPT, %g1, %g2, %g3, %g4, %g5, %g6, %g7)
SET_SIZE(cpu_err_rerouted)
HV_PRINT_NOTRAP("ABORT: Failure 0x");
HV_PRINT_NOTRAP(", contacting vbsc\r\n");
ba,pt %xcc, vbsc_hv_abort
HV_PRINT_NOTRAP(", spinning\r\n");
! intended never to return
projects / OpenSPARC-T2-SAM / blob