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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / legion / src / procs / sunsparc / libniagara2 / include / niagara2.h
/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: niagara2.h
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _NIAGARA2_H_
#define _NIAGARA2_H_
#pragma ident "@(#)niagara2.h 1.50 07/10/12 SMI"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef NIAGARA2 /* { */
#include "niagara2_err_trap.h"
#if INTERNAL_BUILD
#include "stream_ma.h"
#endif
/*
* Niagara2 specific definitions
*/
#include "niagara2_device.h"
/*
* This table describes the trap behaviour for Niagara2 ..
* based on the existing state (User, Priv, Hyper mode),
* and to which state the trap is to be delivered.
* Moreover, what is the priority of the trap type.
*
* The definition is based on N2 PRM, Rev. 1.0
*/
typedef enum {
SS_trap_NONE = -1,
SS_trap_legion_save_state = 0x0, /* Reserved on real HW */
SS_trap_power_on_reset = 0x1,
SS_trap_watchdog_reset = 0x2,
SS_trap_externally_initiated_reset = 0x3,
SS_trap_software_initiated_reset = 0x4,
SS_trap_RED_state_exception = 0x5,
/* 0x6 Reserved */
N2_trap_store_error = 0x7,
SS_trap_IAE_privilege_violation = 0x8,
SS_trap_instruction_access_MMU_miss = 0x9,
SS_trap_instruction_access_error = 0xa,
SS_trap_IAE_unauth_access = 0xb,
SS_trap_IAE_NFO_page = 0xc,
N2_trap_instruction_address_range = 0xd,
N2_trap_instruction_real_range = 0xe,
/* 0xf Reserved */
SS_trap_illegal_instruction = 0x10,
SS_trap_privileged_opcode = 0x11,
SS_trap_unimplemented_LDD = 0x12,
SS_trap_unimplemented_STD = 0x13,
SS_trap_DAE_invalid_ASI = 0x14,
SS_trap_DAE_privilege_violation = 0x15,
SS_trap_DAE_nc_page = 0x16,
SS_trap_DAE_NFO_page = 0x17,
/* 0x18-0x1f Reserved */
SS_trap_fp_disabled = 0x20,
SS_trap_fp_exception_ieee_754 = 0x21,
SS_trap_fp_exception_other = 0x22,
SS_trap_tag_overflow = 0x23,
SS_trap_clean_window = 0x24,
/* 0x25-0x27 clean_window reserved */
SS_trap_division_by_zero = 0x28,
SS_trap_internal_processor_error = 0x29,
SS_trap_instruction_invalid_TSB_entry = 0x2a,
SS_trap_data_invalid_TSB_entry = 0x2b,
/* 0x2c Reserved */
N2_trap_mem_real_range = 0x2d,
N2_trap_mem_address_range = 0x2e,
/* 0x2f Reserved */
SS_trap_DAE_so_page = 0x30,
SS_trap_data_access_MMU_miss = 0x31,
SS_trap_data_access_error = 0x32,
SS_trap_data_access_protection = 0x33,
SS_trap_mem_address_not_aligned = 0x34,
SS_trap_LDDF_mem_address_not_aligned = 0x35,
SS_trap_STDF_mem_address_not_aligned = 0x36,
SS_trap_privileged_action = 0x37,
SS_trap_LDQF_mem_address_not_aligned = 0x38,
SS_trap_STQF_mem_address_not_aligned = 0x39,
/* 0x3a Reserved */
N2_trap_unsupported_page_size = 0x3b,
N2_trap_control_word_queue_interrupt = 0x3c,
N2_trap_modular_arithmetic_interrupt = 0x3d,
SS_trap_instruction_real_translation_miss = 0x3e,
SS_trap_data_real_translation_miss = 0x3f,
SS_trap_sw_recoverable_error = 0x40,
SS_trap_interrupt_level_1 = 0x41,
SS_trap_interrupt_level_2 = 0x42,
SS_trap_interrupt_level_3 = 0x43,
SS_trap_interrupt_level_4 = 0x44,
SS_trap_interrupt_level_5 = 0x45,
SS_trap_interrupt_level_6 = 0x46,
SS_trap_interrupt_level_7 = 0x47,
SS_trap_interrupt_level_8 = 0x48,
SS_trap_interrupt_level_9 = 0x49,
SS_trap_interrupt_level_a = 0x4a,
SS_trap_interrupt_level_b = 0x4b,
SS_trap_interrupt_level_c = 0x4c,
SS_trap_interrupt_level_d = 0x4d,
SS_trap_interrupt_level_e = 0x4e,
SS_trap_interrupt_level_f = 0x4f,
/* SS_trap_pic_overflow = 0x4f,
* (shares TT 0x4f with interrupt_level_15)
*/
/* 0x50-0x5d Reserved */
SS_trap_hstick_match = 0x5e,
SS_trap_trap_level_zero = 0x5f,
SS_trap_interrupt_vector_trap = 0x60,
SS_trap_RA_watchpoint = 0x61,
SS_trap_VA_watchpoint = 0x62,
SS_trap_hw_corrected_error = 0x63,
SS_trap_fast_instruction_access_MMU_miss = 0x64,
/* 0x65-0x67 Reserved */
SS_trap_fast_data_access_MMU_miss = 0x68,
/* 0x69-0x6b Reserved */
SS_trap_fast_data_access_protection = 0x6c,
/* 0x6d-0x6f Reserved */
/* 0x70 Reserved */
SS_trap_instruction_access_MMU_error = 0x71,
SS_trap_data_access_MMU_error = 0x72,
/* 0x73 Reserved */
SS_trap_control_transfer_instruction = 0x74,
SS_trap_instruction_VA_watchpoint = 0x75,
SS_trap_instruction_breakpoint = 0x76,
/* 0x77-0x7b Reserved */
SS_trap_cpu_mondo_trap = 0x7c,
SS_trap_dev_mondo_trap = 0x7d,
SS_trap_resumable_error = 0x7e,
SS_trap_nonresumable_error = 0x7f,
SS_trap_spill_0_normal = 0x80,
SS_trap_spill_1_normal = 0x84,
SS_trap_spill_2_normal = 0x88,
SS_trap_spill_3_normal = 0x8c,
SS_trap_spill_4_normal = 0x90,
SS_trap_spill_5_normal = 0x94,
SS_trap_spill_6_normal = 0x98,
SS_trap_spill_7_normal = 0x9c,
SS_trap_spill_0_other = 0xa0,
SS_trap_spill_1_other = 0xa4,
SS_trap_spill_2_other = 0xa8,
SS_trap_spill_3_other = 0xac,
SS_trap_spill_4_other = 0xb0,
SS_trap_spill_5_other = 0xb4,
SS_trap_spill_6_other = 0xb8,
SS_trap_spill_7_other = 0xbc,
SS_trap_fill_0_normal = 0xc0,
SS_trap_fill_1_normal = 0xc4,
SS_trap_fill_2_normal = 0xc8,
SS_trap_fill_3_normal = 0xcc,
SS_trap_fill_4_normal = 0xd0,
SS_trap_fill_5_normal = 0xd4,
SS_trap_fill_6_normal = 0xd8,
SS_trap_fill_7_normal = 0xdc,
SS_trap_fill_0_other = 0xe0,
SS_trap_fill_1_other = 0xe4,
SS_trap_fill_2_other = 0xe8,
SS_trap_fill_3_other = 0xec,
SS_trap_fill_4_other = 0xf0,
SS_trap_fill_5_other = 0xf4,
SS_trap_fill_6_other = 0xf8,
SS_trap_fill_7_other = 0xfc,
/* trap 0x100-0x17f, */
SS_trap_trap_instruction = 0x100,
/* htrap 0x180-0x1ff, */
SS_trap_htrap_instruction = 0x180,
SS_trap_illegal_value = 0x200
} ss_trap_type_t;
typedef struct TRAP_PRIORITY {
ss_trap_type_t trap_type;
char * trap_namep;
uint_t priority;
tflag_t from_user;
tflag_t from_priv;
tflag_t from_hyperpriv;
} ss_trap_list_t;
extern ss_trap_list_t ss_trap_list[];
/*
* ASI's as implemented by Niagara2
*
* The definition is based on table 9-2, Chapter 9 of N2 PRM, Rev. 1.0
*/
typedef enum {
/* MANDATORY SPARC V9 ASIs */
SS_ASI_NUCLEUS = 0x4 , /* RW Implicit Address Space, nucleus context, TL>0 */
SS_ASI_NUCLEUS_LITTLE = 0xc , /* RW Implicit Address Space, nucleus context, TL>0 (LE) */
SS_ASI_AS_IF_USER_PRIMARY = 0x10, /* RW Primary Address Space, user privilege */
SS_ASI_AS_IF_USER_SECONDARY = 0x11, /* RW Secondary Address Space, user privilege */
SS_ASI_AS_IF_USER_PRIMARY_LITTLE = 0x18, /* RW Primary Address Space, user privilege (LE) */
SS_ASI_AS_IF_USER_SECONDARY_LITTLE = 0x19, /* RW Secondary Address Space, user privilege (LE) */
SS_ASI_PRIMARY = 0x80, /* RW Implicit Primary Address space */
SS_ASI_SECONDARY = 0x81, /* RW Implicit Secondary Address space */
SS_ASI_PRIMARY_NO_FAULT = 0x82, /* R Primary Address space, no fault */
SS_ASI_SECONDARY_NO_FAULT = 0x83, /* R Secondary Address space, no fault */
SS_ASI_PRIMARY_LITTLE = 0x88, /* RW Implicit Primary Address space (LE) */
SS_ASI_SECONDARY_LITTLE = 0x89, /* RW Implicit Secondary Address space (LE) */
SS_ASI_PRIMARY_NO_FAULT_LITTLE = 0x8A, /* R Primary Address space, no fault (LE) */
SS_ASI_SECONDARY_NO_FAULT_LITTLE = 0x8B, /* R Secondary Address space, no fault (LE) */
/* SunSPARC EXTENDED (non-V9) ASIs */
OLD_SS_ASI_PHYS_USE_EC = 0x14, /* RW physical address, non-allocating in L1 cache */
OLD_SS_ASI_PHYS_BYPASS_EC_WITH_EBIT = 0x15, /* RW Same as ASI_PHYS_USE_EC for memory addresses. For IO addresses, physical address, non-cacheable, with side-effect */
SS_ASI_REAL_MEM = 0x14, /* RW physical address, non-allocating in L1 cache */
SS_ASI_REAL_IO = 0x15, /* RW Same as ASI_PHYS_USE_EC for memory addresses. For IO addresses, physical address, non-cacheable, with side-effect */
SS_ASI_BLOCK_AS_IF_USER_PRIMARY = 0x16, /* RW 64B block load/store, primary address space, user privilege */
SS_ASI_BLOCK_AS_IF_USER_SECONDARY = 0x17, /* RW 64B block load/store, secondary address space, user privilege */
OLD_SS_ASI_PHYS_USE_EC_LITTLE = 0x1C, /* RW physical address, non-allocating in L1 cache */
OLD_SS_ASI_PHYS_BYPASS_EC_WITH_EBIT_LITTLE = 0x1D, /* RW Same as ASI_PHYS_USE_EC_LITTLE for memory addresses. For IO addresses, physical address, non-cacheable, with side-effect (LE) */
SS_ASI_REAL_MEM_LITTLE = 0x1C, /* RW physical address, non-allocating in L1 cache */
SS_ASI_REAL_IO_LITTLE = 0x1D, /* RW Same as ASI_PHYS_USE_EC_LITTLE for memory addresses. For IO addresses, physical address, non-cacheable, with side-effect (LE) */
SS_ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE = 0x1E, /* RW 64B block load/store, primary address space, user privilege (LE) */
SS_ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE = 0x1F, /* RW 64B block load/store, secondary address space, user privilege (LE) */
SS_ASI_SCRATCHPAD = 0x20, /* Scratchpad Registers */
SS_ASI_MMU = 0x21, /* MMU Registers */
SS_ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_P = 0x22, /* Block initializing store/128b atomic LDDA, primary address, user privilege */
SS_ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_S = 0x23, /* Block initializing store/128b atomic LDDA, secondary address, user privilege */
SS_ASI_QUAD_LDD = 0x24, /* 128b atomic LDDA */
SS_ASI_QUEUE = 0x25, /* Mondo Queue Pointers */
SS_ASI_QUAD_LDD_REAL = 0x26, /* 128b atomic LDDA, real address */
SS_ASI_NUCLEUS_BLK_INIT_ST_QUAD_LDD = 0x27, /* Block initializing store/128b atomic LDDA */
SS_ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_P_LITTLE = 0x2A, /* Block initializing store/128b atomic LDDA, primary address, user priv (LE) */
SS_ASI_AS_IF_USER_BLK_INIT_ST_QUAD_LDD_S_LITTLE = 0x2B, /* Block initializing store, secondary address, user privilege (LE) */
SS_ASI_QUAD_LDD_LITTLE = 0x2C, /* 128b atomic LDDA (LE) */
SS_ASI_QUAD_LDD_REAL_LITTLE = 0x2E, /* 128b atomic LDDA, real address (LE) */
SS_ASI_NUCLEUS_BLK_INIT_ST_QUAD_LDD_LITTLE = 0x2F, /* Block initializing store/128b atomic LDDA (LE) */
SS_ASI_AS_IF_PRIV_PRIMARY = 0x30, /* FIXME - add support */
SS_ASI_AS_IF_PRIV_SECONDARY = 0x31, /* FIXME - add support */
SS_ASI_AS_IF_PRIV_NUCLEUS = 0x36, /* FIXME - add support */
SS_ASI_AS_IF_PRIV_PRIMARY_LITTLE = 0x38, /* FIXME - add support */
SS_ASI_AS_IF_PRIV_SECONDARY_LITTLE = 0x39, /* FIXME - add support */
SS_ASI_AS_IF_PRIV_NUCLEUS_LITTLE = 0x3E, /* FIXME - add support */
SS_ASI_STREAM_MA = 0x40, /* Asynchronous Streaming Control Register */
SS_ASI_CMP = 0x41, /* CMP Specific Register */
SS_ASI_LSU_DIAG_REG = 0x42, /* Diagnostic / Control register */
SS_ASI_ERROR_INJECT_REG = 0x43, /* Error Injection Register */
SS_ASI_LSU_CONTROL_REG = 0x45, /* Load/Store Unit Control Register */
SS_ASI_DCACHE_DATA = 0x46, /* Dcache data array diagnostics access */
SS_ASI_DCACHE_TAG = 0x47, /* Dcache tag and valid bit diagnostics access */
N2_ASI_IRF_ECC_REG = 0x48, /* IRF ECC diagnostic access */
N2_ASI_FRF_ECC_REG = 0x49, /* FRF ECC diagnostic access */
N2_ASI_STB_ACCESS = 0x4A, /* Store buffer diagnostic access */
N2_ASI_DESR = 0x4C, /* Disrupting Error Status Register */
N2_ASI_SPACE_PWR_MGMT = 0x4E, /* Sparc power management register */
SS_ASI_HYP_SCRATCHPAD = 0x4F, /* RW 0-38 Y Hypervisor Scratchpad */
SS_ASI_IMMU = 0x50, /* IMMU control register */
N2_ASI_MRA_ACCESS = 0x51, /* 0-FF8: Hardware Tablewalk MMU Register Array Access */
N2_ASI_MMU_REAL_RANGE = 0x52, /* 108-120: MMU TSB Real Range register 0,1,2,3
208-220: MMU TSB Physical Offset register 0, 1, 2, 3 */
N2_ITLB_PROBE = 0x53, /* ITBL Probe */
SS_ASI_ITLB_DATA_IN_REG = 0x54, /* IMMU data in register */
SS_ASI_ITLB_DATA_ACCESS_REG = 0x55, /* IMMU TLB Data Access Register */
SS_ASI_ITLB_TAG_READ_REG = 0x56, /* IMMU TLB Tag Read Register */
SS_ASI_IMMU_DEMAP = 0x57, /* IMMU TLB Demap */
SS_ASI_DMMU = 0x58, /* DMMU control register */
N2_SCRATCHPAD_ACCESS = 0x59, /* Scratchpad Register Diagnostic Access register */
N2_TICK_ACCESS = 0x5A, /* Tick Register Diagnostic Access register */
N2_TSA_ACCESS = 0x5B, /* TSA Diagnostic Access register */
SS_ASI_DTLB_DATA_IN_REG = 0x5C, /* DMMU data in register */
SS_ASI_DTLB_DATA_ACCESS_REG = 0x5D, /* DMMU TLB Data Access Register */
SS_ASI_DTLB_TAG_READ_REG = 0x5E, /* DMMU TLB Tag Read Register */
SS_ASI_DMMU_DEMAP = 0x5F, /* DMMU TLB Demap */
SS_ASI_CMP_CORE_INTR_ID = 0x63, /* 0: Core Interrupt ID
10: Core ID */
SS_ASI_ICACHE_INSTR = 0x66, /* Icache data array diagnostics access */
SS_ASI_ICACHE_TAG = 0x67, /* Icache tag and valid bit diagnostics access */
N2_ASI_INTR_RECEIVE = 0x72, /* Interrupt Receive Register */
N2_ASI_INTR_W = 0x73, /* Interrupt Vector Dispatch Register */
N2_ASI_INTR_R = 0x74, /* Incoming Vector Register */
SS_ASI_PST8_P = 0xC0, /* 8 bit partial pri */
SS_ASI_PST8_S = 0xC1, /* 8 bit partial sec */
SS_ASI_PST16_P = 0xC2, /* 16 bit partial pri */
SS_ASI_PST16_S = 0xC3, /* 16 bit partial sec */
SS_ASI_PST32_P = 0xC4, /* 32 bit partial pri */
SS_ASI_PST32_S = 0xC5, /* 32 bit partial sec */
SS_ASI_PST8_PL = 0xC8, /* 8 bit partial pri LE */
SS_ASI_PST8_SL = 0xC9, /* 8 bit partial sec LE */
SS_ASI_PST16_PL = 0xCA, /* 16 bit partial pri LE */
SS_ASI_PST16_SL = 0xCB, /* 16 bit partial sec LE */
SS_ASI_PST32_PL = 0xCC, /* 32 bit partial pri LE */
SS_ASI_PST32_SL = 0xCD, /* 32 bit partial sec LE */
SS_ASI_FL8_P = 0xD0, /* float 8 bit partial pri */
SS_ASI_FL8_S = 0xD1, /* float 8 bit partial sec */
SS_ASI_FL16_P = 0xD2, /* float 16 bit partial pri */
SS_ASI_FL16_S = 0xD3, /* float 16 bit partial sec */
SS_ASI_FL8_PL = 0xD8, /* float 8 bit partial pri LE*/
SS_ASI_FL8_SL = 0xD9, /* float 8 bit partial sec LE*/
SS_ASI_FL16_PL = 0xDA, /* float 16 bit partial pri LE */
SS_ASI_FL16_SL = 0xDB, /* float 16 bit partial sec LE */
SS_ASI_BLK_COMMIT_P = 0xE0, /* any type of access causes data_access_exception */
SS_ASI_BLK_COMMIT_S = 0xE1, /* any type of access causes data_access_exception */
SS_ASI_BLK_INIT_ST_QUAD_LDD_P = 0xE2, /* Block initializing store/128b atomic LDDA, primary address */
SS_ASI_BLK_INIT_ST_QUAD_LDD_S = 0xE3, /* Block initializing store/128b atomic LDDA, secondary address */
SS_ASI_BLK_INIT_ST_QUAD_LDD_P_LITTLE = 0xEA, /* Block initializing store/128b atomic LDDA, primary address (LE) */
SS_ASI_BLK_INIT_ST_QUAD_LDD_S_LITTLE = 0xEB, /* Block initializing store/128b atomic LDDA, secondary address (LE) */
SS_ASI_BLK_P = 0xF0, /* 64B block load/store, primary address */
SS_ASI_BLK_S = 0xF1, /* 64B block load/store, secondary address */
SS_ASI_BLK_PL = 0xF8, /* 64B block load/store, primary address (LE) */
SS_ASI_BLK_SL = 0xF9 /* 64B block load/store, secondary address (LE) */
} ss_asi_t;
/*
* I/D-Cache size
*/
#define SS_ICACHE_SIZE 0x4000 /* 16K instn cache with 32B lines */
#define SS_DCACHE_SIZE 0x2000 /* 8K data cache with 16B lines */
/*
* L1 I-Cache Diagnostic Access, table 28-8,10, sections 28.5 of N2 PRM, Rev. 1.0
* (different from N1)
*/
#define SS_ICACHE_DATA_LINEWORD_BITS 0xff8 /* line[11:6]word[5:3]rsv2[2:0]*/
#define SS_ICACHE_DATA_WAY_BITS 0x7000 /* way[14:12] */
#define SS_ICACHE_TAG_LINE_BITS 0xfc0 /* line[11:6]rsvd2[5:0] */
#define SS_ICACHE_TAG_WAY_BITS 0x7000 /* way[14:12] */
/*
* D-Cache Diagnostic Access Sections 28.6 of N2 PRM, Rev. 1.0
* (same as N1)
*/
#define SS_DCACHE_DATA_BITS 0x1ff8 /* way[12:11]line[10:4]word[3]rsv2[2:0] */
#define SS_DCACHE_DATA_TAG_BITS 0x7ffffff800 /* tag[39:11] */
#define SS_DCACHE_TAG_WAYLINE_BITS 0x1ff0 /* way[12:11]line[10:4]rsvd1[3:0] */
/*
* Macros used to map strands (virtual cores) into internal strands:
* core = num / 8;
* strand = num % 8;
* idx = str_to_idx[num]
*/
#define STRANDSPERCORE 8 /* architectural, needed to match registers */
#define CORESPERCHIP 8
#define STRANDS_PER_CHIP (STRANDSPERCORE * CORESPERCHIP)
#define VALID_CORE_MASK 0xffffffffffffffffull
#define NO_STRAND ((uint_t)-1)
#define STRANDID2IDX(npp, s) \
(((uint_t)(s) < STRANDS_PER_CHIP) ? (npp)->str_to_idx[s] : NO_STRAND)
#define VALIDIDX(npp, tidx) \
((uint_t)(tidx) != NO_STRAND)
/*
* MMU TSB config register for Niagara 2
*/
typedef struct {
uint64_t data; /* 64 bit value of the register */
bool_t enable; /* bit 63 */
bool_t use_context_0; /* bit 62 */
bool_t use_context_1; /* bit 61 */
tvaddr_t tsb_base; /* bits <39:13> */
bool_t ra_not_pa; /* bit 8 */
uint_t page_size; /* bits <6:4> */
uint_t tag_match_shift;
uint_t tsb_size; /* bits <3:0> */
uint8_t *tsb_base_sim; /* in sim tsb_base */
} ss_tsb_info_t;
#define INVALID_SCRATCHPAD(addr) \
(((addr)>=0x20 && (addr)<=0x2f) || ((addr)>=0x3f))
#define INVALID_HYP_SCRATCHPAD(addr) ((addr)>=0x3f)
#define SSR_HSCRATCHPAD_INDEX (SSR_ScratchPad0)
/*
* per strand mmu registers for Niagara 2
*/
struct SS_MMU {
bool_t enabled; /* force real or virtual translations in priv/user mode */
bool_t is_immu; /* indicate IMMU or DMMU translation */
tvaddr_t fault_addr;
uint64_t tag_access_reg; /* content of ASI_MMU_TAG_ACCESS */
uint64_t watchpoint;
};
/*
* Four types of demap operation are provided for Niagara 2
*/
enum SS_DEMAP {
NA_demap_page = 0x0,
NA_demap_context = 0x1,
NA_demap_all = 0x2,
NA_demap_all_page = 0x3
};
/*
* Error registers specific for Niagara 2
*/
struct SS_ERROR {
uint8_t isfsr; /* IMMU synchronous fault status, ASI=0x50, VA=0x18 */
uint8_t dsfsr; /* DMMU synchronous fault status, ASI=0x58, VA=0x18 */
uint64_t desr; /* disrupting error status, ASI=0x4C, VA=0x0 */
uint64_t dfesr; /* deferred error status, ASI=0x4C, VA=0x8 */
tvaddr_t dsfar; /* synchronous fault address, ASI=0x58, VA=0x18 */
uint64_t cerer; /* core error recording enable ASI=0x4C, VA=0x10 */
uint64_t inject;
};
#if ERROR_INJECTION
#include "niagara2_error.h"
#endif
/*
* macros used to determine the virtual core and strand Ids for Niagara 2
*/
#define SS_COREID_SHIFT 3
#define SS_STRANDID_MASK MASK64(2,0) /* strand Id stored in bits 2:0 */
/*
* Strand structure for Niagara 2
*/
typedef struct SS_STRAND {
ss_trap_type_t pending_precise_tt;
ss_trap_type_t pending_async_tt;
bool_t flag_queue_irq[4]; /* see na_qnum_t */
na_queue_t nqueue[4]; /* see na_qnum_t */
bool_t mmu_bypass; /* no translation if hpstate in RED or HPriv modes */
/* IRQ lock is used whenever a irq vector bit needs
* to be set or cleared. Pre examining irq_vector
* should not require holding the lock, but
* attention must be set *after* vector modification.
*/
pthread_mutex_t irq_lock;
uint64_t irq_vector; /* bit63 = highest priority */
#define INTR_VEC_MASK MASK64(5,0)
uint16_t pri_context; /* primary context 0 */
uint16_t sec_context; /* secondary context 0 */
uint16_t pri_context1; /* primary context 1 */
uint16_t sec_context1; /* secondary context 1 */
uint16_t partid; /* partition ID */
SS_CORE_NUM_FIELDS
uint8_t hwtw_config; /* hardware tablewalk config */
uint64_t real_range_reg[4]; /* real range (RPN -> PPN) */
uint64_t phy_off_reg[4]; /* physical offset */
uint64_t itlb_probe; /* itlb probe */
uint64_t strand_reg[SSR_Num_Regs];
ss_tsb_info_t mmu_zero_ctxt_tsb_config[4]; /* zero context tsb config */
ss_tsb_info_t mmu_nonzero_ctxt_tsb_config[4]; /* nonzero context tsb config */
ss_tlb_t * dtlbp; /* the D-TLB this strand uses */
ss_tlb_t * itlbp; /* the I-TLB this strand uses */
/* the MMU fault status registers ... */
ss_mmu_t dmmu;
ss_mmu_t immu;
ss_l1_cache_t * icachep; /* the instn cache this strand uses */
ss_l1_cache_t * dcachep; /* the data cache this strand uses */
#if ERROR_TRAP_GEN /* { */
cpu_error_reg_t *cpu_err_regp;
#endif /* } ERROR_TRAP_GEN */
/* Error handling registers */
ss_error_t error;
/* Other control registers */
uint64_t lsu_control_raw;
/*
* per CPU performance counters
*/
uint32_t pic0;
uint32_t pic1;
uint64_t pcr;
uint64_t pic0_sample_base;
uint64_t pic1_sample_base;
} ss_strand_t;
/*
* ASI_CMP registers shared by each Niagara 2 physical core
*/
typedef struct NIAGARA2_CMP_REGS {
uint64_t core_enable_status;
uint64_t xir_steering;
bool_t tick_enable;
uint64_t core_running_status;
} niagara2_cmp_regs_t;
/*
* Niagara2 processor itself - composed of strands, TLBs and
* other state.
*/
typedef uint64_t sparc_power_mgmt_t;
#ifdef VFALLS /* { */
typedef union {
uint32_t all;
struct {
uint8_t rsvd;
uint8_t multi_chip;
uint8_t lfu;
uint8_t zambezi;
} flags;
} global_add_stat_t;
#define GLOBAL_ADDRESSING_FLAG_EN 0xff
#define GLOBAL_ADDRESSING_FLAG_DIS 0x0
#define GLOBAL_ADDRESSING_ENABLE 0xffffffff
#define GLOBAL_ADDRESSING_CHECK(_osp, _pseudo_dev) do { \
ss_proc_t *onpp; \
onpp = (ss_proc_t *)_osp->config_procp->procp; \
if (onpp->global_addressing_ok.all < GLOBAL_ADDRESSING_ENABLE) { \
fatal ("[0x%llx] (pc=0x%llx)\tGlobal addressing of "_pseudo_dev \
" not allowed. Please check that this is a multinode " \
"config and lfu and (optionally) Zambezi registers " \
"are correctly setup.\n", _osp->gid, _osp->pc); \
} \
} while (0)
#endif /* } */
struct SS_PROC {
config_proc_t * config_procp; /* points back to generic type */
/* data private for a Niagara2 cpu */
uint64_t clkfreq;
uint64_t core_mask;
uint_t nwins;
uint_t nglobals;
uint_t maxtl;
uint64_t ver;
bool_t has_fpu;
bool_t crypto_synchronous;
tvaddr_t rstv_addr; /* Red State Trap Vector base - copied into v9 info */
uint_t str_to_idx[STRANDS_PER_CHIP]; /* strand/ss_strandp idx */
uint_t nstrands; /* array size for strand/ss_strandp */
sparcv9_cpu_t** strand;
/* linear array of strand specific info for this Niagara2 proc */
ss_strand_t * ss_strandp;
sparc_power_mgmt_t *sparc_power_mgmtp; /* array of power mgmt registers/asis - one per core */
niagara2_cmp_regs_t cmp_regs; /* CMP registers, each shared by all virtual cores */
pthread_mutex_t cmp_lock;
bool_t tick_stop;
pthread_mutex_t tick_en_lock;
uint_t nitlb;
uint_t ndtlb;
ss_tlb_t * itlbp; /* linear array of I tlbs - one per core */
ss_tlb_t * dtlbp; /* linear array of D tlbs - one per core */
ss_tlb_spec_t itlbspec; /* parsed spec for each TLB ... */
ss_tlb_spec_t dtlbspec; /* contains duplicated fields FIXME */
ss_l1_cache_t * icachep; /* linear array of icaches - 1/core */
ss_l1_cache_t * dcachep; /* linear array of dcaches - 1/core */
#if INTERNAL_BUILD
asi_stream_CWQ_t * stream_cwq_p; /* linear array of stream units */
asi_stream_MA_t * mod_arith_p; /* linear array of mod_arith units */
#endif
bool_t is_inited; /* set once allocated simcpu_t for each strand */
/* JTAG registers. Note that these are aliases for ASI's*/
config_dev_t *jtag_devp;
#ifdef VFALLS /* { */
/* NCX registers */
ncx_t *ncxp;
config_dev_t *ncx_devp;
/* LFU registers */
lfu_t *lfup;
config_dev_t *lfu_devp;
/* COU registers */
cou_t *coup;
config_dev_t *cou_devp;
global_add_stat_t global_addressing_ok;
#endif /* } VFALLS */
/* SSI registers */
ssi_t *ssip;
config_dev_t *ssi_devp; /* pseudo device for SSI regs */
/* NCU registers */
ncu_t *ncup;
config_dev_t *ncu_devp; /* pseudo device for NCU regs */
/* Clock unit registers */
ccu_t *clockp;
config_dev_t *clock_devp; /* pseudo device for clock unit regs */
/* HW Debug unit registers */
hwdbg_t *hwdbgp;
config_dev_t *hwdbg_devp; /* pseudo device for debug unit regs */
/* Reset unit registers */
rcu_t *rcup;
config_dev_t *rcu_devp; /* pseudo device for reset unit regs */
/* L2 Cache controllers */
uint_t num_l2banks;
l2c_t *l2p;
config_dev_t *l2c_devp; /* pseudo device for l2 controller regs */
/* Memory controllers */
uint_t num_mbanks;
mcu_bank_t *mbankp;
config_dev_t *mcu_devp; /* pseudo device for dram ctrl regs */
error_conf_t * pend_errlistp; /* processor list of pending errors */
pthread_mutex_t err_lock;
bool_t error_check;
error_proc_t * errorp;
proc_debug_t proc_debug;
#if ERROR_TRAP_GEN /* { */
ss_error_state_t ss_err_state; /* error framework state */
cpu_error_state_t *cpu_err_statep; /* CPU specific state */
#endif /* } ERROR_TRAP_GEN */
};
/*
* macros used in MMU area
*/
/* For the moment, ISFSR and DSFSR have the same bit mask. */
#define MMU_SFSR_MASK MASK64(3,0)
#define DEFAULT_ITLB_ENTRIES 64
#define DEFAULT_DTLB_ENTRIES 128
#define SS_TLB_REAL_MASK MASK64(10,10)
#define SS_TLB_IS_REAL(n) (bool_t)(((uint64_t)n >> 10) & 0x1)
/* Inserting RA to PA translations forces this context value */
#define NIAGARA2_REAL_CONTEXT 3
/*
* chip-specific macros used for determing the fields of sun4v TTE format
*/
#define N2_TTET_RSVD0 MASK64(63, 61)
#define N2_TTET_RSVD1 MASK64(47, 42)
#define SUN4V_TTET_RSVD(n) ((uint64_t)n & (N2_TTET_RSVD0|N2_TTET_RSVD1))
#define SUN4V_TTET_CTXT(n) (((uint64_t)n & MASK64(60, 48)) >> 48)
#define SUN4V_TTED_RA(n) ((uint64_t)n & MASK64(55, 13))
#define SUN4V_PN_UBIT 39
#define SUN4V_PN_LBIT 13
#define SUN4V_PN_MASK MASK64(SUN4V_PN_UBIT, SUN4V_PN_LBIT)
#define UPDATE_MMU_TAG_ACCESS(_mmup, _va, _ctx) do{\
(_mmup)->tag_access_reg = (VA48(_va) & MASK64(63,13)) | ((_ctx) & MASK64(12,0));\
DBGMMU( lprintf(sp->gid, "%cMMU tag access = 0x%llx\n", (_mmup)->is_immu ? 'I' : 'D', (_mmup)->tag_access_reg); ); \
} while (0)
#define NIAGARA2_DATA_ACCESS_PAR_BIT 61
#define NIAGARA2_DATA_IN_MASK (MASK64(63,62) | MASK64(39,13) | \
MASK64(12,10) | MASK64(8,8) | MASK64(6,6) | MASK64(3,0))
#define NIAGARA2_DATA_ACCESS_MASK ((1ull << NIAGARA2_DATA_ACCESS_PAR_BIT) | \
NIAGARA2_DATA_IN_MASK)
/*
* macros used to calculate the phys addr of an TTE entry in the TSB
*
* ps: refers to page_size field of the TSB config register
* n: refers to tsb_size field of the TSB config register
*/
#define SUN4V_PAGE_OFFSET(ps) (uint_t)((SUN4V_PN_LBIT + 3*(ps)))
#define SUN4V_VPN_MASK(ps) MASK64(47, SUN4V_PAGE_OFFSET(ps));
#define SUN4V_TTE_IDX_MASK(n,ps) MASK64((21+(n)+3*(ps)),SUN4V_PAGE_OFFSET(ps))
#define SUN4V_TSB_BASE_MASK(n) MASK64(SUN4V_PN_UBIT, 13+(n))
#define SET_DTLB_FAULT(_nsp, _va) do{ (_nsp)->dmmu.fault_addr = (_va); } while (0)
#define SET_ITLB_FAULT(_nsp, _va) do{ (_nsp)->immu.fault_addr = (_va); } while (0)
/*
* niagara 2 function prototypes
*/
void niagara2_write_tsb_config(simcpu_t*, ss_tsb_info_t *tsb_config_reg, uint64_t data);
/*
* external function prototypes used in this file
*/
extern ss_trap_type_t ss_tlb_insert(simcpu_t*, ss_mmu_t*, ss_tlb_t*, uint_t, bool_t, uint64_t, uint_t*, uint64_t*);
extern ss_trap_type_t ss_tlb_insert_idx(simcpu_t*, ss_mmu_t*, ss_tlb_t*, uint_t, bool_t, uint64_t, uint_t);
extern void ss_setup_pseudo_devs(domain_t *domainp, ss_proc_t *procp);
/* Processor specific parsing for "proc" elements in config file */
extern bool_t ss_parse_proc_entry(ss_proc_t*, domain_t *);
/*
* default CPU version values
* from NG2 PRM rev 1.0, section 3.4.5
*/
#define SS_VER_MANUF 0x003eULL
#define SS_VER_IMPL 0x0024ULL
#ifdef VFALLS /* { */
#define SS_VER_MASK 0x0028ULL
#else /* N2 */
#define SS_VER_MASK 0x0020ULL
#endif /* } VFALLS */
#define SS_VER_MAXGL 3
#define SS_VER_MAXTL 6
#define SS_VER_MAXWIN 7
#ifdef VFALLS
#define MAX_NODEID 0x3
#endif
/*
* %pcr
*/
#define SS_PCR_PRIV BIT(0)
#define SS_PCR_ST BIT(1)
#define SS_PCR_UT BIT(2)
#define SS_PCR_HT BIT(3)
#define SS_PCR_TOE0 BIT(4)
#define SS_PCR_TOE1 BIT(5)
#define SS_PCR_MASK0_SHIFT 6
#define SS_PCR_MASK0 MASK64(13,SS_PCR_MASK0_SHIFT)
#define SS_PCR_SL0_SHIFT 14
#define SS_PCR_SL0 MASK64(17,SS_PCR_SL0_SHIFT)
#define SS_PCR_OV0 BIT(18)
#define SS_PCR_MASK1_SHIFT 19
#define SS_PCR_MASK1 MASK64(26,SS_PCR_MASK0_SHIFT)
#define SS_PCR_SL1_SHIFT 27
#define SS_PCR_SL1 MASK64(30,SS_PCR_SL0_SHIFT)
#define SS_PCR_OV1 BIT(31)
#define SS_PCR_UT_ST (SS_PCR_UT | SS_PCR_ST)
#define SS_PCR_MASK MASK64(31,0)
#define SS_PCR_CLEAR_ON_READ (SS_PCR_OV1 | SS_PCR_OV0)
#define SS_PCR_TEST_OVF_PENDING(_pcr) \
(((_pcr) & (SS_PCR_OV0 | SS_PCR_TOE0)) == (SS_PCR_OV0 | SS_PCR_TOE0) || \
((_pcr) & (SS_PCR_OV1 | SS_PCR_TOE1)) == (SS_PCR_OV1 | SS_PCR_TOE1))
#endif /* } NIAGARA2 */
#ifdef __cplusplus
}
#endif
#endif /* _NIAGARA2_H_ */
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