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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / legion / src / procs / sunsparc / libniagara2 / include / niagara2_device.h
/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: niagara2_device.h
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _NIAGARA2_DEVICE_H
#define _NIAGARA2_DEVICE_H
#pragma ident "@(#)niagara2_device.h 1.27 07/09/18 SMI"
#ifdef __cplusplus
extern "C" {
#endif
#include "device.h"
#define GETMASK64(x, hi, lo) (((uint64_t)(x) & MASK64((hi), (lo)))>>(lo))
/* IO Device Physical Address map that is common to N2 and VF */
#define PHYS_ADDR_NCU 0x8000000000
#define PHYS_ADDR_CCU 0x8300000000
#define PHYS_ADDR_MCU 0x8400000000
#define PHYS_ADDR_HWDBG 0x8600000000
#define PHYS_ADDR_DMU 0x8800000000
#define PHYS_ADDR_RCU 0x8900000000
#define PHYS_ADDR_L2C 0xA000000000
#define PHYS_ADDR_PIU_LB 0xC000000000
#define PHYS_ADDR_PIU_UB 0xCF00000000
#define PHYS_ADDR_SSI 0xFF00000000
#define PHYS_ADDR_JTAG 0x9000000000
#define NCU_RANGE 0x100000000
#define CCU_RANGE 0x100000000
#define L2C_RANGE 0x2000000000
#define SSI_RANGE 0x10000000 /* Note this covers only the SSI CSR space and not the boot ROM.
Boot ROM is taken care of by the conf file */
#define RCU_RANGE 0x100000000
#define JTAG_RANGE 0x100000000
#ifdef VFALLS /* { */
#define PHYS_ADDR_NCX 0x8100000000
#define PHYS_ADDR_COU 0x8110000000
#define PHYS_ADDR_LFU 0x8120000000
#define PHYS_ADDR_ZAM 0x8130000000
#define PCIADDR2NODE(addr) ((addr & MASK64(35,34)) >> 34)
#define NCX_RANGE 0x10000000
#define COU_RANGE 0x10000000
#define LFU_RANGE 0x10000000
#define PHYS_ADDR_NCU_REMOTE(_node_id) (0xE000000000 + (_node_id * 0x400000000))
#define PHYS_ADDR_CCU_REMOTE(_node_id) (0xE300000000 + (_node_id * 0x400000000))
#define PHYS_ADDR_MCU_REMOTE(_node_id) (0xD000000000 + (_node_id * 0x400000000))
#define PHYS_ADDR_DMU_REMOTE(_node_id) (0xD200000000 + (_node_id * 0x400000000))
#define PHYS_ADDR_RCU_REMOTE(_node_id) (0xD300000000 + (_node_id * 0x400000000))
#define PHYS_ADDR_PIU_REMOTE(_node_id) (0xC000000000 + (_node_id * 0x400000000))
#define PHYS_ADDR_JTAG_REMOTE(_node_id) (0x9200000000 + (_node_id * 0x400000000))
#define PHYS_ADDR_NCX_REMOTE(_node_id) (0xE100000000 + (_node_id * 0x400000000))
#define PHYS_ADDR_COU_REMOTE(_node_id) (0xE110000000 + (_node_id * 0x400000000))
#define PHYS_ADDR_LFU_REMOTE(_node_id) (0xE120000000 + (_node_id * 0x400000000))
#define MAGIC_SSI 0xFFFFFF0000 /* Magic SSI address where SYS_MODE_REG info is stored
for consumption by reset(dumb and standalone) */
#else /* N2 */
/*
* N2 specific IO device physical addess map
*/
#define PHYS_ADDR_NIU 0x8100000000
#endif /* } VFALLS */
#define PSEUDO_DEV_NAME_NCU "ncu"
#define PSEUDO_DEV_NAME_CCU "ccu" /* clock unit */
#define PSEUDO_DEV_NAME_MCU "mcu" /* dram */
#define PSEUDO_DEV_NAME_L2C "l2c" /* L2 Control */
#define PSEUDO_DEV_NAME_SSI "ssi"
#define PSEUDO_DEV_NAME_HWDBG "hwdbg" /* Hardware debug */
#define PSEUDO_DEV_NAME_RCU "rcu" /* Reset Unit */
#define PSEUDO_DEV_NAME_JTAG "jtag" /* JTAG/TAP region */
#ifdef VFALLS /* { */
#define PSEUDO_DEV_NAME_NCX "ncx" /* Non-cache Crossbar region */
#define PSEUDO_DEV_NAME_COU "cou" /* Coherency Unit */
#define PSEUDO_DEV_NAME_LFU "lfu" /* Link Framing Unit */
#endif /* } VFALLS */
#define PHYS_ADDR_MASK 0xFF00000000
/*
* NCU address mapped registers (MSB[39:32] = 0x80)
*/
#define NCU_TARGETS 64 /* number of virtual cores */
#define NCU_DEV_MAX 128 /* max number of device Ids */
#define NCU_DEV_ERR 1 /* device Id for ECC error */
#define NCU_DEV_SSI 2 /* device Id for SSI interrupt */
#define NCU_DEV_NIU_LB 64 /* device Id range for NIU interrupt */
#define NCU_DEV_NIU_UB NCU_DEV_MAX-1
#define NCU_INT_MAN_CPUID(n) (((n) & MASK64(13, 8)) >> 8)
#define NCU_INT_ACK 0
#define NCU_INT_NACK -1
#define NCU_INT_TGTOFFSET_MASK ((NCU_TARGETS * 8) - 1)
#define NCU_MONDO_INT_MASK 0x40fff
#define NCU_MONDO_INT_BUSY MASK64(6,6)
#define NCU_REG_MASK 0x4ffff
#define NCU_SOC_MASK MASK64(42,40)|MASK64(38,37)|MASK64(35,34)|MASK64(32,31)|MASK64(29,0)
#define UINT64_RANGE_CHECK(_low, _val, _high) \
(((uint64_t)(_val) - (uint64_t)(_low)) < ((uint64_t)(_high) - (uint64_t)(_low)))
typedef enum {
INT_MAN = 0x00000,
MONDO_INT_VEC = 0x00a00,
SER_NUM = 0x01000,
EFU_STAT = 0x01008,
CORE_AVAIL = 0x01010, /* same as ASI_CORE_AVAILABLE */
BANK_AVAIL = 0x01018,
BANK_ENABLE = 0x01020,
BANK_ENABLE_STATUS = 0x01028,
L2_IDX_HASH_EN = 0x01030,
L2_IDX_HASH_EN_STATUS = 0x01038,
PCIE_A_MEM32_OFFSET_BASE = 0x02000,
PCIE_A_MEM32_OFFSET_MASK = 0x02008,
PCIE_A_MEM64_OFFSET_BASE = 0x02010,
PCIE_A_MEM64_OFFSET_MASK = 0x02018,
PCIE_A_IOCON_OFFSET_BASE = 0x02020,
PCIE_A_IOCON_OFFSET_MASK = 0x02028,
PCIE_A_FSH = 0x02030,
SOC_ESR = 0x03000,
SOC_LOG_ENABLE = 0x03008,
SOC_INTERRUPT_ENABLE = 0x03010,
SOC_ERROR_INJECTION = 0x03018,
SOC_FATAL_ERROR_ENABLE = 0x03020,
SOC_PENDING_ERROR_STATUS = 0x03028, /* same as SOC_ESR */
SOC_SII_ERROR_SYNDROME = 0x03030,
SOC_NCU_ERROR_SYNDROME = 0x03038,
MONDO_INT_DATA0 = 0x40000,
MONDO_INT_DATA1 = 0x40200,
MONDO_INT_ADATA0 = 0x40400,
MONDO_INT_ADATA1 = 0x40600,
MONDO_INT_BUSY = 0x40800,
MONDO_INT_ABUSY = 0x40a00
} ncu_reg_offset_t;
typedef struct {
uint64_t int_man[NCU_DEV_MAX];
uint64_t mondo_int_vec;
uint64_t ser_num;
uint64_t efu_stat;
uint64_t bank_enb;
uint64_t bank_enb_stat;
bool_t l2_idx_hash_en_stat;
uint64_t pcie_a_mem32_offset_base;
uint64_t pcie_a_mem32_offset_mask;
uint64_t pcie_a_mem64_offset_base;
uint64_t pcie_a_mem64_offset_mask;
uint64_t pcie_a_iocon_offset_base;
uint64_t pcie_a_iocon_offset_mask;
uint64_t pcie_a_fsh;
uint64_t soc_esr;
uint64_t soc_log_enb;
uint64_t soc_intr_enb;
uint64_t soc_err_steering; /* mapped in JTAG space */
uint64_t soc_err_inject;
uint64_t soc_fatal_enb;
uint64_t soc_sii_err_syndrome;
uint64_t soc_ncu_err_syndrome;
uint64_t mondo_int_data0[NCU_TARGETS];
uint64_t mondo_int_data1[NCU_TARGETS];
uint64_t mondo_int_busy[NCU_TARGETS];
} ncu_reg_t;
/*
* PIU region map address
*/
#define PIU_MAX_REGION 4
#define PIU_REGION_OFFSET_MASK MASK64(35,24)
#define PIU_REGION_OFFSET_MASK_HI MASK64(39,36)
typedef struct {
uint64_t base;
uint64_t mask;
uint64_t size;
int func;
bool_t enable;
uint8_t priority;
int align_size;
int reverse_endian;
} map_info_t;
typedef enum {
PIU_REGION_CFGIO = 0,
PIU_REGION_MEM32 = 1,
PIU_REGION_MEM64 = 2,
PIU_REGION_8MB = 3,
PIU_REGION_UNMAPPED
} piu_region_t;
/*
* NCU pseudo device
*/
typedef struct {
ncu_reg_t regs; /* NCU CSRs */
map_info_t map[PIU_MAX_REGION]; /* PIU region map info */
pthread_mutex_t ncu_lock; /* hold this lock for any ncu register access */
int node_id;
} ncu_t;
/*
* DMU 8MB configu region address map
*/
#define DMU_8MB_GAP_MASK MASK64(31,23)
#define DMU_8MB_OFFSET_MASK MASK64(22,0)
/*
* L2 Cache controller definition
*/
#define L2_BANKS 8
/*
* L2 Cache Diagnostic Access section 28.17.1 N2 PRM, Rev. 1.2
*/
typedef struct L2C {
uint64_t * diag_datap;
uint64_t * diag_tagp;
#define L2_TAG MASK64(39,18) /* table 28-46 */
#define L2_TAG_ECC MASK64(5,0)
uint64_t * diag_vuadp;
#define L2_ODDEVEN_SHIFT 22 /* table 28-43 */
#define L2_WAY_MASK 0xf << 18
#define L2_WAY MASK64(21,18) & L2_WAY_MASK
#define L2_LINE MASK64(17,9) /* vs. MASK64(17,8) for N1 */
#define L2_BANK MASK64(8,6) /* vs. MASK64(7,6) for N1 */
#define L2_WORD MASK64(5,3)
#define L2_VDSEL MASK64(22,22)
#define L2_DM_MASK MASK64(21,6)
/*
* index into data with way/line/bank/word/oddeven bits
* access 64bits: 32bit data, 7bit ECC, plus rsvd bits, total of 8MB
*/
#define L2_DATA_SIZE ((L2_WAY|L2_LINE|L2_BANK|L2_WORD|(1<<L2_ODDEVEN_SHIFT))+8)
/*
* index into tags with way/line/bank bits
* access 64bits: 22bit tag, 6bit ECC plus rsvd bits (512K size)
*/
#define L2_TAG_SIZE (((L2_WAY|L2_LINE|L2_BANK)>>3)+8)
/*
* index into vuad with way/line/bank bits
* access 64bits: valid/dirty or alloc/used bits and associated parity (64K size)
*/
#define L2_VUAD_SIZE (((L2_LINE|L2_BANK|(L2_VDSEL>>4))>>3)+8)
uint32_t control[L2_BANKS]; /* table 28-34 */
#ifdef VFALLS /* { */
#define L2_NODEID MASK64(24,23)
#define L2_NODEID_SHIFT 23
#endif /* } */
#define L2_DBGEN MASK64(21,21)
#define L2_DBGEN_SHIFT 21
#define L2_ERRORSTEER MASK64(20,15)
#define L2_SCRUBINTERVAL MASK64(14,3)
#define L2_SCRUBENABLE MASK64(2,2)
#define L2_DMMODE MASK64(1,1)
#define L2_DIS MASK64(0,0)
uint64_t error_enable[L2_BANKS]; /* table 12-20 */
#define L2_DBG_TRIG_EN MASK64(2,2)
#define L2_NCEEN MASK64(1,1)
#define L2_CEEN MASK64(0,0)
uint64_t error_status[L2_BANKS]; /* table 12-21 */
#ifdef VFALLS
uint64_t error_status_ii[L2_BANKS]; /* VF PRM table 12-2 */
#endif
uint64_t error_address[L2_BANKS];
uint64_t error_notdata[L2_BANKS];
uint8_t error_inject[L2_BANKS];
uint16_t bist_ctl[L2_BANKS];
} l2c_t;
/*
* L2 Cache Error Registers, section 12.10.2 of N2 PRM, Rev. 1.0
*/
#define BIT(i) ((uint64_t)1<<i)
#define L2_MEU_bit BIT(63)
#define L2_MEC_bit BIT(62)
#define L2_RW_bit BIT(61)
#define L2_MODA_bit BIT(60)
#define L2_LDAC_bit BIT(53)
#define L2_LDAU_bit BIT(52)
#define L2_LDWC_bit BIT(51)
#define L2_LDWU_bit BIT(50)
#define L2_LDRC_bit BIT(49)
#define L2_LDRU_bit BIT(48)
#define L2_LDSC_bit BIT(47)
#define L2_LDSU_bit BIT(46)
#define L2_LTC_bit BIT(45)
#define L2_LRF_bit BIT(44)
#define L2_LVF_bit BIT(43)
#define L2_DAC_bit BIT(42)
#define L2_DAU_bit BIT(41)
#define L2_DRC_bit BIT(40)
#define L2_DRU_bit BIT(39)
#define L2_DSC_bit BIT(38)
#define L2_DSU_bit BIT(37)
#define L2_VEC_bit BIT(36)
#define L2_VEU_bit BIT(35)
#define L2_LVC_bit BIT(34)
#define L2_SYND_MASK MASK64(27,0)
#define L2_TID(val) (((uint64_t)val & 0x3f) << 54)
#define L2_FAKE_SYND_SINGLE 0x43 /* single bit error on bit 0 */
#define L2_FAKE_SYND_DOUBLE 0x33 /* uncorrectible double bit error */
#define L2_FAKE_SYND_POISON 0x03 /* poisoned ecc */
/*
* bits captured for some error type, table 12-26, section 12.10.3 of N2 PRM, Rev. 1.0
*/
#define L2_PA_LINE(val) (val & MASK64(39,6))
#define L2_PA_QUAD(val) (val & MASK64(39,4))
#define L2_INDEX(val) (val & MASK64(21,6))
#define L2_DIR_IDX(val) (val & MASK64(15,6))
/*
* SSI
*/
typedef struct SSI {
uint64_t timeout;
uint64_t log;
uint64_t magic_ssi;
} ssi_t;
/*
* HWDBG
*/
typedef struct HWDBG {
uint64_t debug_port_config;
uint64_t io_quiesce_control;
} hwdbg_t;
/*
* Reset Unit
*/
typedef struct RCU {
uint64_t reset_gen;
uint64_t reset_status;
uint64_t reset_source;
#ifdef VFALLS /* { */
uint64_t comt_divs;
uint64_t comt_cfg;
uint64_t clk_steer;
uint64_t comt_lock_time;
#endif /* } */
} rcu_t;
/*
* Clock Unit
*/
#define RC_DELAY_MASK 0xffff
#define RC_DELAY_SHIFT 9
#define RC_BYPASS_SHIFT 8
#define RC_FREQ_SEL_MASK 0x3
#define RC_FREQ_SEL_SHIFT 6
#define RC_ANALOG_SEL_MASK 0x3
#define RC_ANALOG_SEL_SHIFT 4
#define RC_MODE_SHIFT 3
#define RC_NOISE_CELL_SEL_MASK 0x7
#define RC_NOISE_CELL_SEL_SHIFT 0
#define RC_REG_MASK MASK64(24, 0)
typedef struct {
uint64_t ctl;
uint8_t freqidx[3];
double phase[3];
double frequency[4][3];
double noise[4][3];
} rand_state_t;
typedef struct CCU {
uint64_t control;
rand_state_t rand_state;
} ccu_t;
/*
* Memory controller
*/
/*
* max number of AMBs per channel
* note that for 2 channel mode this may need to be
* 16 to support acces to FBD_CHNL_STATE reg
*/
#define MAX_AMBS 16
/* active link trained state for fbd_chnl_state */
#define L0_STATE 0x6
typedef struct {
uint8_t val; /* value for reg */
uint8_t ambstate[MAX_AMBS]; /* state for each amb off */
}fbstate_t;
/* fbdimm regs */
typedef enum {
FBD_VID_DID = 0x000,
FBDS = 0x140,
EMASK = 0x18c,
FERR = 0x190,
NERR = 0x194,
PSBYTE3_0 = 0x1b0,
PSBYTE7_4 = 0x1b4,
PSBYTE11_8 = 0x1b8,
PSBYTE13_12 = 0x1bc,
C2DINCRCUR_CMD2DATANXT = 0x1e8,
MBCSR = 0x340,
DAREFTC = 0x370,
MTR_DSREFTC = 0x374,
DRT = 0x378,
DRC = 0x37c,
DCALCSR = 0x440,
DCALADDR = 0x444,
DDR2ODTC = 0x4fc,
FBDIMM_ILLEGAL_REG = -1
} fbdimm_ctl_regs_t;
typedef struct AMB {
uint32_t vid_did;
uint32_t fbds;
uint32_t emask;
uint32_t ferr;
uint32_t nerr;
uint32_t psbyte3_0;
uint32_t psbyte7_4;
uint32_t psbyte11_8;
uint32_t psbyte13_12;
uint32_t c2dincrcur_cmd2datanxt;
uint32_t mbcsr;
uint32_t dareftc;
uint32_t mtr_dsreftc;
uint32_t drt;
uint32_t drc;
uint32_t dcalcsr;
uint32_t dcaladdr;
uint32_t ddr2odtc;
} amb_ctl_t;
/* extract ambaddr and ambid from Configuration Register Access Address Reg */
#define AMBID(reg) ((reg & MASK64(14, 11)) >> 11)
#define AMBADDR(reg) (reg & MASK64(10, 2))
/* link regs */
/*
* FBDS0: FBD Status 0
Bit Attr Default Description
7:5 RV 0h Reserved
4 RO 0h SP: Parity: This bit contains an odd parity bit that
covers the S[3:0] field.
3 RO 0h S3: Northbound Debug Event(1 = asserted, 0 = inactive):
This bit is used to communicate debug events to the
host.
2:1 RO 0h S[2:1]: Thermal Trip: This field indicates various
thermal conditions of the AMB as follows:
00 Below TEMPLO
01 Above TEMPLO
10 Above TEMPMID and falling
11 Above TEMPMID and rising
The TEMPLO threshold is generally used to inform the
host to accelerate refresh events. The TEMPMID threshold
is generally used to inform the host that a thermal
limit has been exceeded and that thermal throttling is
needed. Refer to the RAS chapter for more details on
thermal management.
0 RO 0h S0: ERROR Asserted: This bit indicates an error has been
detected by the AMB. Errors can be alert or other type.
*/
#define S0_ERROR (1ULL << 0)
/* ddr regs */
/*
DRC: DRAM Controller Mode Register
Bit Attr Default Description
31:30 RV 00 Reserved
29 RW 0 INITDONE: Initialization Complete. This scratch bit
communicates software state from the AMB to BIOS. BIOS
sets this bit to 1 after initialization of the DRAM
memory array is complete. This bit has no effect on AMB
operation.
28 RV 0 Reserved
27:24 RWST 0 CLKDIS: clock[3:0] output disable
23 RWST 0 SEQADDR: When set to 1 turns off address balancing to
support DRAMs programmed for Sequential Burst Type
19:22 RV 00 Reserved
18 RWST 1 ODTZ: On-Die Termination Strength. 0 Disabled 1
Enabled
17 RWST 0 HLDDIS: command/address hold disable
16 RWST 0 BALDIS: command/address balancing disable
15 RW 0 CADIS: command/address output disable
14 RW 0 CSDIS: chip select output disable
13 RW 0 ODTDIS: ODT output disable
12 RWST 1 CKEFRCLOW: CKE Force Low Forces CKE low. Must be cleared
to enable normal DDR functionality. This bit overrides
the CKE1 and CKE0 fields described below, and also
overrides all channel commands and other hardware
fuctions that would otherwise affect the state of the
CKE outputs.
11 RW 0 CKEDIS: CKE output disable
10 RWST 0 CKE1: CKE output 1 control and status. Software can
write to this bit to change the state of the CKE 1
output. Hardware will update this bit with the current
status of the CKE1 output two core cycles after a
channel command or other hardware function changes the
state of the CKE1 output. 1 = CKE1 pads asserted. 0
= CKE1 pads de-asserted.
9 RWST 0 CKE0: CKE output 0 control and status. Software can
write to this bit to change the state of the CKE 0
output. Hardware will update this bit with the current
status of the CKE 0 output two core cycles after a
channel command or other hardware function changes the
state of the CKE 0 output. 1 = CKE0 pads asserted. 0
= CKE0 pads de-asserted.
8 RWST 0 BL: DRAM burst length. 1 = bl8 0 = bl4
7:4 RWST 2h AL: DRAM Additive Latency [3:0]
3:0 RWST 3h CL: DRAM CAS Latency [3:0]
*/
#define CKEFRCLOW (1ULL << 12)
#define CKE1 (1ULL << 10)
#define CKE0 (1ULL << 9)
typedef struct MCU_BANK {
uint8_t cas_addr_width;
uint8_t ras_addr_width;
uint8_t cas_lat;
uint16_t scrub_freq;
uint16_t refresh_freq;
uint16_t refresh_counter;
uint8_t scrub_enable;
uint8_t trrd;
uint8_t trc;
uint8_t trcd;
uint8_t twtr;
uint8_t trtw;
uint8_t trtp;
uint8_t tras;
uint8_t trp;
uint8_t twr;
uint8_t trfc;
uint8_t tmrd;
uint8_t fawin;
uint8_t tiwtr;
uint8_t dimm_stack;
uint16_t ext_wr_mode2;
uint16_t ext_wr_mode1;
uint16_t ext_wr_mode3;
uint8_t eight_bank_mode;
uint8_t branch_disabled;
uint8_t sel_lo_addr_bits;
uint8_t single_chnl_mode;
#ifdef VFALLS
uint8_t mirror_mode;
#endif VFALLS
uint8_t dimm_init;
uint8_t init_status;
uint8_t dimm_present;
uint8_t failover_status;
uint64_t failover_mask;
uint8_t power_down_mode;
fbstate_t fbd_chnl_state;
amb_ctl_t amb[MAX_AMBS];
uint8_t fbd_fast_reset_flag;
uint8_t fbd_chnl_reset;
uint8_t ts1_sb_nb_mapping;
uint32_t ts1_test_parameter;
uint16_t ts3_failover_config;
uint32_t electrical_idle_detected;
uint8_t disable_state_period;
uint8_t disable_state_period_done;
uint32_t calibrate_state_period;
uint8_t calibrate_state_period_done;
uint16_t training_state_min_time;
uint8_t training_state_done;
uint8_t training_state_timeout;
uint8_t testing_state_done;
uint8_t testing_state_timeout;
uint8_t polling_state_done;
uint8_t polling_state_timeout;
uint8_t config_state_done;
uint8_t config_state_timeout;
uint16_t dram_per_rank_cke;
uint8_t l0s_duration;
uint8_t chnl_sync_frame_freq;
uint16_t chnl_read_lat;
uint16_t chnl_capability;
uint8_t loopback_mode_cntl;
uint32_t serdes_config_bus;
uint64_t serdes_invpair;
uint64_t serdes_test_config_bus;
uint16_t config_reg_access_addr;
uint32_t config_reg_access_data;
uint64_t error_status;
uint64_t error_address;
uint64_t error_inject;
uint16_t error_counter;
uint64_t error_location;
uint64_t error_retry;
uint64_t fbd_error_synd;
uint64_t fbd_inj_error_src;
uint64_t fbr_count;
uint8_t perf_ctl;
uint64_t perf_count;
uint32_t open_bank_max;
uint16_t prog_time_cntr;
uint8_t dbg_trg_en;
uint64_t ibist_nbfib_ctl;
uint64_t ibist_sbfib_ctl;
} mcu_bank_t;
/*
* DRAM Error Registers, section 12.12.1 of N2 PRM, Rev. 1.0
*/
#define DRAM_MEU_bit BIT(63)
#define DRAM_MEC_bit BIT(62)
#define DRAM_DAC_bit BIT(61)
#define DRAM_DAU_bit BIT(60)
#define DRAM_DSC_bit BIT(59)
#define DRAM_DSU_bit BIT(58)
#define DRAM_DBU_bit BIT(57)
#define DRAM_MEB_bit BIT(56)
#define DRAM_FBU_bit BIT(55)
#define DRAM_FBR_bit BIT(54)
#define DRAM_SYND_MASK MASK64(15,0)
#define DRAM_FAKE_SYND_SINGLE 0x00010101 /* nibble 31, bit 1 in error */
#define DRAM_FAKE_SYND_DOUBLE 0x00000101 /* uncorrectible multi-nibble error */
#define DRAM_FAKE_SYND_POISON 0x00008221 /* poisoned ecc */
/*
* SSI
*/
typedef enum {
SSI_TIMEOUT = 0x10088,
SSI_LOG = 0x00018
} ssi_reg_t;
/*
* HW Debug Unit
*/
typedef enum {
DEBUG_PORT_CONFIG = 0x0,
IO_QUIESCE_CONTROL = 0x8
} hwdbg_reg_t;
/*
* Reset Unit
*/
typedef enum {
#ifdef VFALLS /* { */
COMT_DIVS = 0x920,
COMT_CFG = 0x940,
CLK_STEER = 0x960,
COMT_LOCK_TIME = 0x970,
#endif /* } */
RESET_GEN = 0x808,
RESET_STATUS = 0x810,
RESET_SOURCE = 0x818
} rcu_reg_t;
/*
* JTAG
*/
typedef enum {
INT_VECTOR_DISPATCH = 0x1cc0000,
ASI_CORE_AVAILABLE = 0x1040000,
ASI_CORE_ENABLE_STATUS = 0x1040010,
ASI_CORE_ENABLE = 0x1040020,
ASI_CORE_RUNNING_RW = 0x1040050,
ASI_CORE_RUNNING_STATUS = 0x1040058,
ASI_CORE_RUNNING_W1S = 0x1040060,
ASI_CORE_RUNNING_W1C = 0x1040068,
SOC_ERROR_STEERING = 0x1041000
} jtag_reg_t;
#ifdef VFALLS /* { */
/*
* NCX
*/
typedef enum {
CF_SYS_MODE_REG = 0x8,
CF_SLOW_PULSE_WAIT = 0x18,
NCX_TIC_EN_SLOW = 0x20,
NCX_TWR = 0x1000,
NCX_TPESR = 0x1008,
NCX_TPELSE = 0x1010,
NCX_TPEAR = 0x1018
} ncx_reg_t;
#define SM_E2WAY_SEL_SHIFT 9
#define SM_E3WAY_SEL_SHIFT 8
#define SM_E4WAY_SEL_SHIFT 7
#define SM_EXTERN_HUB_SEL_SHIFT 6
#define SM_NODE_SEL_MASK 0x3
#define SM_NODE_SEL_SHIFT 4
#define SM_PLANE_EN_SEL_MASK 0xf
#define SM_PLANE_EN_SEL_SHIFT 0
#define SM_REG_MASK MASK64(9, 0)
#define SM_EWAY_BITS(_sys_mode) (((_sys_mode) >> SM_E4WAY_SEL_SHIFT) & \
7)
#define SM_2_NODE(_sys_mode) (((_sys_mode) >> SM_NODE_SEL_SHIFT) & \
SM_NODE_SEL_MASK)
typedef struct NCX {
uint64_t sys_mode;
uint64_t tick_en_slow;
uint64_t slow_pulse_wait;
uint64_t twr;
uint64_t tpesr;
uint64_t tpelse;
uint64_t tpear;
} ncx_t;
/*
* COU
*/
#define COU_LINK_MAX 4ULL
#define COU_LINK_SHIFT 12
#define COU_LINK_MASK ((COU_LINK_MAX-1) << COU_LINK_SHIFT)
typedef enum {
COU_ERR_ENABLE_REG = 0x00,
COU_ESR = 0x10,
COU_EAR = 0x18
} cou_reg_t;
typedef struct COU {
uint64_t cou_err_enable[COU_LINK_MAX];
uint64_t cou_esr[COU_LINK_MAX];
uint64_t cou_ear[COU_LINK_MAX];
} cou_t;
/*
* LFU
*/
typedef enum {
CL_INIT_STATE = 0x0,
CL_CFG_REG = 0x8,
CL_SERDES_CFG = 0x58,
CL_SER_INVPAIR = 0x60,
CL_TEST_CFG = 0x68,
CL_ERROR_STAT = 0x80
} lfu_reg_t;
#define LFU_MAX_LINKS 0x4
#define LFU_LINK_MASK 0x3000
#define LFU_LINK_L0 0x5
#define LFU_LINK_MASTER_EN 0x3
#define LFU_LINK_SLAVE_EN 0x1
typedef struct LFU {
uint64_t cl_init_state[LFU_MAX_LINKS];
uint64_t cl_cfg_reg[LFU_MAX_LINKS];
uint64_t cl_serdes_cfg[LFU_MAX_LINKS];
uint64_t cl_ser_invpair[LFU_MAX_LINKS];
uint64_t cl_test_cfg[LFU_MAX_LINKS];
uint64_t cl_error_stat[LFU_MAX_LINKS];
} lfu_t;
#endif /* } VFALLS */
/*
* Clock unit
*/
typedef enum {
CLOCK_CONTROL = 0x00,
RAND_CTL = 0x20,
RAND_GEN = 0x30
} ccu_reg_t;
/*
* L2 Cache Registers, section 28.17 of N2 PRM, Rev. 1.0
*/
typedef enum {
L2_DIAG_DATA = 0x0, /* Table 28-44 */
L2_DIAG_TAG = 0x4, /* Table 28-46 */
L2_DIAG_VUAD = 0x6, /* Table 28-50 */
L2_TAG_BIST = 0x8, /* Table 28-51 */
L2_CONTROL = 0x9, /* Table 28-34 */
L2_ERROR_ENABLE = 0xa, /* Table 12-20 */
L2_ERROR_STATUS = 0xb, /* Table 12-21 */
#ifdef VFALLS
L2_ERROR_STATUS_II = 0xf, /* VF PRM, Table 12-2 */
#endif
L2_ERROR_ADDRESS = 0xc, /* Table 12-25 */
L2_ERROR_INJECT = 0xd, /* Table 12-29 */
L2_ERROR_NOTDATA = 0xe /* Table 12-27 */
} l2c_reg_t;
/*
* DRAM controller section 25.10 of N2 RPM, Rev. 1.0
*/
typedef enum {
DRAM_CAS_ADDR_WIDTH = 0x000,
DRAM_RAS_ADDR_WIDTH = 0x008,
DRAM_CAS_LAT = 0x010,
DRAM_SCRUB_FREQ = 0x018,
DRAM_REFRESH_FREQ = 0x020,
DRAM_OPEN_BANK_MAX = 0x028,
DRAM_REFRESH_COUNTER = 0x038,
DRAM_SCRUB_ENABLE = 0x040,
DRAM_PROG_TIME_CNTR = 0x048,
DRAM_TRRD = 0x080,
DRAM_TRC = 0x088,
DRAM_TRCD = 0x090,
DRAM_TWTR = 0x098,
DRAM_TRTW = 0x0a0,
DRAM_TRTP = 0x0a8,
DRAM_TRAS = 0x0b0,
DRAM_TRP = 0x0b8,
DRAM_TWR = 0x0c0,
DRAM_TRFC = 0x0c8,
DRAM_TMRD = 0x0d0,
DRAM_FAWIN = 0x0d8,
DRAM_TIWTR = 0x0e0,
DRAM_DIMM_STACK = 0x108,
DRAM_EXT_WR_MODE2 = 0x110,
DRAM_EXT_WR_MODE1 = 0x118,
DRAM_EXT_WR_MODE3 = 0x120,
DRAM_8_BANK_MODE = 0x128,
DRAM_BRANCH_DISABLED = 0x138,
DRAM_SEL_LO_ADDR_BITS = 0x140,
DRAM_SINGLE_CHNL_MODE = 0x148, /* Table 25-30, possible PRM doc error */
#ifdef VFALLS
DRAM_MIRROR_MODE = 0x150,
#endif
DRAM_DIMM_INIT = 0x1a0,
DRAM_INIT_STATUS = 0x210,
DRAM_DIMM_PRESENT = 0x218,
DRAM_FAILOVER_STATUS = 0x220,
DRAM_FAILOVER_MASK = 0x228,
DRAM_DBG_TRG_EN = 0x230,
DRAM_POWER_DOWN_MODE = 0x238,
DRAM_ERROR_STATUS = 0x280,
DRAM_ERROR_ADDRESS = 0x288,
DRAM_ERROR_INJECT = 0x290,
DRAM_ERROR_COUNTER = 0x298,
DRAM_ERROR_LOCATION = 0x2a0,
DRAM_ERROR_RETRY = 0x2a8,
DRAM_PERF_CTL = 0x400,
DRAM_PERF_COUNT = 0x408,
FBD_CHNL_STATE = 0x800,
FBD_FAST_RESET_FLAG = 0x808,
FBD_CHNL_RESET = 0x810,
TS1_SB_NB_MAPPING = 0x818,
TS1_TEST_PARAMETER = 0x820,
TS3_FAILOVER_CONFIG = 0x828,
ELECTRICAL_IDLE_DETECTED = 0x830,
DISABLE_STATE_PERIOD = 0x838,
DISABLE_STATE_PERIOD_DONE = 0x840,
CALIBRATE_STATE_PERIOD = 0x848,
CALIBRATE_STATE_PERIOD_DONE = 0x850,
TRAINING_STATE_MIN_TIME = 0x858,
TRAINING_STATE_DONE = 0x860,
TRAINING_STATE_TIMEOUT = 0x868,
TESTING_STATE_DONE = 0x870,
TESTING_STATE_TIMEOUT = 0x878,
POLLING_STATE_DONE = 0x880,
POLLING_STATE_TIMEOUT = 0x888,
CONFIG_STATE_DONE = 0x890,
CONFIG_STATE_TIMEOUT = 0x898,
DRAM_PER_RANK_CKE = 0x8a0,
L0S_DURATION = 0x8a8,
CHNL_SYNC_FRAME_FREQ = 0x8b0,
CHNL_READ_LAT = 0x8b8,
CHNL_CAPABILITY = 0x8c0,
LOOPBACK_MODE_CNTL = 0x8c8,
SERDES_CONFIG_BUS = 0x8d0,
SERDES_INVPAIR = 0x8d8,
SERDES_TEST_CONFIG_BUS = 0x8e0,
CONFIG_REG_ACCESS_ADDR = 0x900,
CONFIG_REG_ACCESS_DATA = 0x908,
DRAM_FBD_ERROR_SYND = 0xc00,
DRAM_FBD_INJ_ERROR_SRC = 0xc08,
DRAM_FBR_COUNT = 0xc10,
IBIST_SBFIB_CTL = 0xe80,
IBIST_NBFIB_CTL = 0xec0,
DRAM_ILLEGAL_REG = -1
} ss_memory_ctl_reg_t;
/*
* prototypes
*/
void niagara2_pcie_mapping(simcpu_t *sp, ncu_t *ncup, piu_region_t region);
#ifdef __cplusplus
}
#endif
#endif /* _NIAGARA2_DEVICE_H */
Full OpenSPARC architecture tarball including simulator, hypervisor, and OBP.