legion/src/procs/sunsparc/libniagara2/include/niagara2_error.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: niagara2_error.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _NIAGARA2_ERROR_H
#define _NIAGARA2_ERROR_H

#pragma ident   "@(#)niagara2_error.h   1.2     06/08/28 SMI"

#ifdef  __cplusplus
extern "C" {
#endif

#if ERROR_INJECTION
/*
 * Niagara 2 Error Types. At the present, it only defines the errors detected by the core.
 */
enum ERROR_TYPE {
        NONE    = 0xffff,
        /*
         * errors handled by SS_trap_instruction_access_MMU_error (table 12-7, PRM v1.0)
         */
        ITTM    = 0x01,
        ITTP    = 0x02,
        ITDP    = 0x03,
        ITMU    = 0x04,
        ITL2U   = 0x05,
        ITL2ND  = 0x06,
        ICL2U   = 0x07,
        ICL2ND  = 0x08,
        /*
         * errors handled by SS_trap_internal_processor_error (table 12-8, PRM v1.0)
         */
        IRFU    = 0x09,
        IRFC    = 0x0a,
        FRFU    = 0x0b,
        FRFC    = 0x0c,
        SBDLC   = 0x0d,
        SBDLU   = 0x0e,
        MRAU    = 0x0f,
        TSAC    = 0x10,
        TSAU    = 0x11,
        SCAC    = 0x12,
        SCAU    = 0x13,
        TCCP    = 0x14,
        TCCU    = 0x15,
        /*
         * errors handled by SS_trap_data_access_MMU_error (table 12-8, PRM v1.0)
         */
        DTTM    = 0x16,
        DTTP    = 0x17,
        DTDP    = 0x18,
        DTMU    = 0x19,
        DTL2U   = 0x1a,
        DTL2ND  = 0x1b,
        /*
         * errors handled by SS_trap_data_access_error (table 12-8, PRM v1.0)
         */
        DCL2U   = 0x1c,
        DCL2ND  = 0x1d,
        SOCU    = 0x1e,
        /*
         * errors handled by SS_trap_hw_corrected_error (table 12-13, PRM v1.0)
         */
        ICVP    = 0x1f,
        ICTP    = 0x20,
        ICTM    = 0x21,
        ICDP    = 0x22,
        DCVP    = 0x23,
        DCTP    = 0x24,
        DCTM    = 0x25,
        DCDP    = 0x26,
        L2C     = 0x27,
        SBDPC   = 0x28,
        SOCC    = 0x29,
        /*
         * errors handled by SS_trap_sw_recoverable_error (table 12-13, PRM v1.0)
         */
        SBDPU   = 0x2a,
        TCCD    = 0x2b,
        TCUD    = 0x2c,
        MAMU    = 0x2d,
        MAL2C   = 0x2e,
        MAL2U   = 0x2f,
        MAL2ND  = 0x30,
        CWQL2C  = 0x31,
        CWQL2U  = 0x32,
        CWQL2ND = 0x33,
        L2C1    = 0x34, /* FIXME: L2C defined twice, rename it to L2C1 for now */
        L2U     = 0x35,
        L2ND    = 0x36,
        ITL2C   = 0x37,
        ICL2C   = 0x38,
        DTL2C   = 0x39,
        DCL2C   = 0x3a,
        SOCU1   = 0x3b  /* FIXME: SOCU defined twice, rename it to SOCU1 for now */
};

#define ERROR_MAXNUM    0x40                    /* maximum number of errors handled currently */

typedef struct SS_ERROR_DESC {
        error_type_t    error_type;
        char            *error_name;
        ss_trap_type_t  trap_type;
        char            *trap_name;
        int             trap_priority;
        int             error_code;
        char            *enable_name;
        uint64_t        enable_bit;
} ss_error_desc_t;

ss_error_desc_t ss_error_list[ERROR_MAXNUM];

/*
 * L2 error enable register, table 12-20, N2 PRM, Rev. 1.0
 */
#define NA_NCEEN        MASK64(1,1)
#define NA_CEEN         MASK64(0,0)


/*
 * Niagara2 error injection routine prototypes
 */
void niagara2_init_error_list();
bool_t itlb_hit_error_match(simcpu_t *sp, tlb_entry_t *tep);
bool_t dtlb_hit_error_match(simcpu_t *sp, int op, tlb_entry_t *tep, tpaddr_t va);
bool_t l2dram_access_error_match(simcpu_t *sp, int op, tpaddr_t pa);
bool_t tlb_data_access_error_match(simcpu_t *sp, ss_mmu_t *mmup, uint64_t idx);
bool_t tlb_tag_access_error_match(simcpu_t *sp, ss_mmu_t *mmup, uint64_t idx);
void xicache_error_match(simcpu_t *sp, tpaddr_t pa);

#endif  /* ERROR_INJECTION */

#ifdef  __cplusplus
}
#endif

#endif  /* _NIAGARA2_ERROR_H */