Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / legion / src / simcore / xdcache.c
/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: xdcache.c
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "@(#)xdcache.c 1.7 06/08/08 SMI"
/*
* Support routines for the execution data cache
*/
#include <assert.h>
#include "basics.h"
#include "allocate.h"
#include "simcore.h"
#include "config.h"
#include "xdcache.h"
void xdcache_flush(simcpu_t * sp)
{
xdcache_t * xdcp = &(sp->xdc);
xdcache_line_t * lp;
ulong_t i;
XDC_FLUSH(sp);
DBGXCACHE( lprintf(sp->gid, "xdcache_flush: pc=0x%llx "
"[cycle=0x%llx]\n", sp->pc, sp->cycle); );
lp = &xdcp->line[0];
for (i=0; i<XDCACHE_NUM_LINES; i++, lp++) {
if ((lp->tag & XCACHE_TAGSTATE_MASK) != XCACHE_TAGSTATE_PHYS)
lp->tag = XDCACHE_INVALID_TAG;
}
}