legion/src/support/asmgen.c

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: asmgen.c
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#pragma ident   "@(#)asmgen.c   1.9     06/03/16 SMI"

#include <stdio.h>
#include <unistd.h>
#include <stdlib.h>

        /*
         * dumb program to generate symbols for various C data structures
         * so that assembler code can access them ... FIXME
         */

#include "basics.h"
#include "fatal.h"
#include "simcore.h"
#include "tsparcv9.h"
#include "tsparcv9internal.h"
#include "config.h"
#include "xicache.h"
#include "xdcache.h"


#define DD( _type, _field, _name)                                               \
        printf("#define\t%s_OFFSET      0x%llx\n",                              \
                #_name,                                                         \
                (unsigned long long)&( ((_type *)0)->_field ) )

int
main(int argc, char ** argv)
{
                /* simcpu_t stuff ; */

        DD( simcpu_t, pc, SIMCPU_PC );
        DD( simcpu_t, npc, SIMCPU_NPC );

                /* This is for SPARCv9 target */
        DD( simcpu_t, v9_ccr, SIMCPU_v9CCR );
        DD( simcpu_t, v9_asi, SIMCPU_v9ASI );
        DD( simcpu_t, v9_y, SIMCPU_v9Y );
        DD( simcpu_t, v9_fsr_exc, SIMCPU_v9FSR_EXC );
        DD( simcpu_t, v9_fsr_tem, SIMCPU_v9FSR_TEM );
        DD( simcpu_t, v9_fsr_ctrl, SIMCPU_v9FSR_CTRL );
        DD( simcpu_t, v9_gsr, SIMCPU_v9GSR_CTRL );

        DD( simcpu_t, scratch64, SIMCPU_SCRATCH64 );

        DD( simcpu_t, fpreg.s32[0], SIMCPU_FPREG );

        DD( simcpu_t, specificp, SIMCPU_SPECIFICP );
        DD( sparcv9_cpu_t, fpu_on, SPARCV9_FPU_ON );

        DD( simcpu_t, pc, SIMCPU_PC );
        DD( simcpu_t, npc, SIMCPU_NPC );


                /* xicache stuff */

        DD( xicache_instn_t, di.rri.simm16, XIC_SIMM16 );
        DD( xicache_instn_t, di.breg.offset32, XIC_BREGOFF32 );
        DD( xicache_instn_t, di.brcond.offset32, XIC_BROFF32 );
        DD( xicache_instn_t, di.rrr.rs1o, XIC_INTREG_SRC1 );
        DD( xicache_instn_t, di.rrr.rs2o, XIC_INTREG_SRC2 );
        DD( xicache_instn_t, di.rrr.rdo, XIC_INTREG_DEST );

        DD( xicache_instn_t, di.rrr.rs1o, XIC_FPREG_SRC1 );
        DD( xicache_instn_t, di.rrr.rs2o, XIC_FPREG_SRC2 );
        DD( xicache_instn_t, di.rrr.rdo, XIC_FPREG_DEST );

        return (0);
}