obp/obp/dev/southbridge/huron/isa/isa.tok

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\ Hypervisor Software File: isa.tok
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id: @(#)isa.tok 1.3 06/08/30
purpose:
copyright: Copyright 2006 Sun Microsystems, Inc.  All Rights Reserved
copyright: Use is subject to license terms.

fcode-version3

headerless

\ this device will be deleted in dropins.src after initializing
\ these few registers

: my-b@  ( offset -- data )  my-space + " config-b@" $call-parent ;
: my-b!  ( data offset -- )  my-space + " config-b!" $call-parent ;
: my-l@  ( offset -- data )  my-space + " config-l@" $call-parent ;
: my-l!  ( data offset -- )  my-space + " config-l!" $call-parent ;

: isa-init

[ifdef] INTX-MESSAGES?

   \ Officially, this "pcie" southbridge device does not support intx.
   \ Unofficially, it seems to work for now, so the platform team has
   \ requested we turn this functionality on until the real solution
   \ (sideband interrupts through the fpga over the ssi bus) is implemented.

   \ The pcie to pci bridge at the root of the southbridge nexus has a
   \ zero valued, read only 'interrupt-pin' register. Because of this,
   \ the common OBP probing code does not create an 'interrupts' property,
   \ and Solaris does not enable INTx. Therefore, we have to do it here.

   my-self my-parent to my-self         ( my-self )
   4 my-l@ h# 400 invert and 4 my-l!    ( my-self )
   1 encode-int " interrupts" property  ( my-self )
   to my-self                           (  )

[else]

   h# 90  my-l@ 1 d# 22 << or h# 90 my-l!  \ enable sideband interrupts

   \ See ULI 1575 End Point Mode Application Note
   h# 48  my-l@ 1 d# 26 << or h# 48 my-l!  \ disable INTx virtual wire messages
[then]
;

isa-init

end0