Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / obp / obp / dev / southbridge / isa / isa.fth
\ ========== Copyright Header Begin ==========================================
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\ Hypervisor Software File: isa.fth
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id: @(#)isa.fth 1.7 02/05/24
purpose:
copyright: Copyright 1996-2002 Sun Microsystems, Inc. All Rights Reserved
copyright: Use is subject to license terms.
headers
" isa" encode-string " name" property
2 encode-int " #address-cells" property
1 encode-int " #size-cells" property
external
: config-b@ ( offset -- b ) " config-b@" $call-parent ;
: config-w@ ( offset -- w ) " config-w@" $call-parent ;
: config-l@ ( offset -- l ) " config-l@" $call-parent ;
: config-b! ( b offset -- ) " config-b!" $call-parent ;
: config-w! ( w offset -- ) " config-w!" $call-parent ;
: config-l! ( l offset -- ) " config-l!" $call-parent ;
headers
: my-b@ ( offset -- b ) my-space or config-b@ ;
: my-w@ ( offset -- w ) my-space or config-w@ ;
: my-l@ ( offset -- l ) my-space or config-l@ ;
: my-b! ( b offset -- ) my-space or config-b! ;
: my-w! ( w offset -- ) my-space or config-w! ;
: my-l! ( l offset -- ) my-space or config-l! ;
: en+ encode-int encode+ ;
: 0+ 0 en+ ;
0 0 encode-bytes
my-space en+ 0+ 0+ 0+ 0+
my-space h# 8100.0010 or en+ 0+ 0+ 0+ h# 1.0000 en+ \ IO
my-space h# 8200.0014 or en+ 0+ 0+ 0+ h# 10.0000 en+ \ 1meg memory
[ifdef] isa-flashprom?
my-space h# 8200.0018 or en+ 0+ h# f000.0000 en+ 0+ h# 10.0000 en+ \ flashprom
[then]
" reg" property
0 0 encode-bytes
0+ 0+ my-space h# 8100.0010 or en+ 0+ 0+ h# 1.0000 en+
1 en+ 0+ my-space h# 8200.0014 or en+ 0+ 0+ h# 10.0000 en+
[ifdef] isa-flashprom?
2 en+ 0+ my-space h# 8200.0018 or en+ 0+ h# f000.0000 en+ h# 10.0000 en+
[then]
" ranges" property
alias sb@ my-b@
alias sb! my-b!
external
\ Southbridge does not really have the base registers, se we
\ need to fake them.
: map-in ( pa.lo pa.hi len -- va )
>r case ( lo )
0 of h# 10 h# 81 0 endof ( lo bar type off )
1 of h# 14 h# 82 0 endof ( lo bar type off )
2 of h# 18 h# 82 h# f000.0000 endof ( lo bar type off )
endcase ( lo bar type off )
>r d# 24 lshift ( lo bar type' )
my-space or or ( lo hi )
swap r> + 0 rot r> ( lo' 0 hi len )
" map-in" $call-parent ( va )
;
: map-out ( va len -- ) " map-out" $call-parent ;
: dma-alloc ( n -- vaddr ) " dma-alloc" $call-parent ;
: dma-free ( vaddr n -- ) " dma-free" $call-parent ;
: dma-map-in ( vaddr n cache? -- devaddr ) " dma-map-in" $call-parent ;
: dma-map-out ( vaddr devaddr n -- ) " dma-map-out" $call-parent ;
: dma-sync ( vaddr devaddr n -- )
" dma-sync" ['] $call-parent
catch if
2drop 3drop \ no parent dma-sync, and none needed
then
;
: decode-unit parse-2int ;
: encode-unit ( l h -- ) swap <# u#s drop ascii , hold u#s u#> ;
: open ( -- ok? ) true ;
: close ( -- ) ;
headers