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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / devtools / v9 / include / spix_sparc.h
/* %COPYRIGHT% */
#ifndef SPIX_SPARC_H
#define SPIX_SPARC_H
#pragma ident "@(#)spix_sparc.h 1.32"
#include <stddef.h>
#include <spixtypes.h>
#include <spix_sparc_iop.h>
#include <spix_sparc_inames.h>
#include <spix_sparc_iwords.h>
#include <IHASH.h>
#ifdef __cplusplus
extern "C" {
#endif
#define DOUBLE_REGNO(x) (((x) & 0x1e) | (((x) & 1) << 5))
#define QUAD_REGNO(x) (((x) & 0x1c) | (((x) & 1) << 5))
/*
* The format of a SPARC instruction.
*/
typedef union {
unsigned inst;
#ifdef ARCH_X64
/*
* On x64 platform, bit-fields are allocated from right to left,
* which is the reverse of SPARC platform.
*/
/*
* SPIX_SPARC_IOP_CALL
*/
struct {
signed disp:30;
unsigned op:2;
} call;
/*
* SPIX_SPARC_IOP_SETHI, SPIX_SPARC_IOP_NOP, SPIX_SPARC_IOP_ILLTRAP
*/
struct {
unsigned imm:22;
unsigned op2:3;
unsigned rd:5;
unsigned op:2;
} sethi;
/*
* SPIX_SPARC_ITYPE_BICC, SPIX_SPARC_ITYPE_FBFCC
*/
struct {
signed disp:22;
unsigned op2:3;
unsigned cond:4;
unsigned a:1;
unsigned op:2;
} bcc;
/*
* SPIX_SPARC_ITYPE_BPCC, SPIX_SPARC_ITYPE_FBPFCC
*/
struct {
signed disp:19;
unsigned p:1;
unsigned cc:2;
unsigned op2:3;
unsigned cond:4;
unsigned a:1;
unsigned op:2;
} bpcc;
/*
* SPIX_SPARC_ITYPE_BPR
*/
struct {
unsigned displo:14;
unsigned rs1:5;
unsigned p:1;
unsigned disphi:2;
unsigned op2:3;
unsigned rcond:3;
unsigned :1;
unsigned a:1;
unsigned op:2;
} bpr;
/*
* SPIX_SPARC_ITYPE_LOAD, SPIX_SPARC_ITYPE_USTORE,
* SPIX_SPARC_ITYPE_CSTORE
*
* SPIX_SPARC_IOP_ADD, SPIX_SPARC_IOP_ADDC, SPIX_SPARC_IOP_ADDCC,
* SPIX_SPARC_IOP_ADDCCC, SPIX_SPARC_IOP_AND, SPIX_SPARC_IOP_ANDCC,
* SPIX_SPARC_IOP_ANDN, SPIX_SPARC_IOP_ANDNCC, SPIX_SPARC_IOP_JMPL,
* SPIX_SPARC_IOP_MULSCC, SPIX_SPARC_IOP_MULX, SPIX_SPARC_IOP_OR,
* SPIX_SPARC_IOP_ORCC, SPIX_SPARC_IOP_ORN, SPIX_SPARC_IOP_ORNCC,
* SPIX_SPARC_IOP_POPC, SPIX_SPARC_IOP_PREFETCH, SPIX_SPARC_IOP_RDASI,
* SPIX_SPARC_IOP_RDASR, SPIX_SPARC_IOP_RDCCR, SPIX_SPARC_IOP_RDFPRS,
* SPIX_SPARC_IOP_RDPC, SPIX_SPARC_IOP_RDTICK, SPIX_SPARC_IOP_RDY,
* SPIX_SPARC_IOP_RESTORE, SPIX_SPARC_IOP_RETURN, SPIX_SPARC_IOP_SAVE,
* SPIX_SPARC_IOP_SDIV, SPIX_SPARC_IOP_SDIVCC, SPIX_SPARC_IOP_SDIVX,
* SPIX_SPARC_IOP_RDGSR, SPIX_SPARC_IOP_SIR, SPIX_SPARC_IOP_SMUL,
* SPIX_SPARC_IOP_SMULCC, SPIX_SPARC_IOP_SUB, SPIX_SPARC_IOP_SUBC,
* SPIX_SPARC_IOP_SUBCC, SPIX_SPARC_IOP_SUBCCC, SPIX_SPARC_IOP_TADDCC,
* SPIX_SPARC_IOP_TADDCCTV, SPIX_SPARC_IOP_TSUBCC,
* SPIX_SPARC_IOP_TSUBCCTV, SPIX_SPARC_IOP_UDIV, SPIX_SPARC_IOP_UDIVCC,
* SPIX_SPARC_IOP_UDIVX, SPIX_SPARC_IOP_UMUL, SPIX_SPARC_IOP_UMULCC,
* SPIX_SPARC_IOP_WRGSR, SPIX_SPARC_IOP_WRASI, SPIX_SPARC_IOP_WRASR,
* SPIX_SPARC_IOP_WRCCR, SPIX_SPARC_IOP_WRFPRS, SPIX_SPARC_IOP_WRY,
* SPIX_SPARC_IOP_XNOR, SPIX_SPARC_IOP_XNORCC, SPIX_SPARC_IOP_XOR,
* SPIX_SPARC_IOP_XORCC, SPIX_SPARC_IOP_FLUSHW, SPIX_SPARC_IOP_WRPR,
* SPIX_SPARC_IOP_FLUSH, SPIX_SPARC_IOP_RDPR, SPIX_SPARC_IOP_WRHPR,
* SPIX_SPARC_IOP_RDHPR
*/
struct {
unsigned rs2:5;
unsigned :8;
unsigned i:1;
unsigned rs1:5;
unsigned op3:6;
unsigned rd:5;
unsigned op:2;
} memarithr;
struct {
unsigned rs2:5;
unsigned :8;
unsigned i:1;
unsigned rs1:5;
unsigned op3:6;
unsigned fcn:5;
unsigned op:2;
} prefetch;
struct {
unsigned imm13:13;
unsigned i:1;
unsigned rs1:5;
unsigned op3:6;
unsigned fcn:5;
unsigned op:2;
} prefetchi;
struct {
unsigned rs2:5;
unsigned imm_asi:8;
unsigned i:1;
unsigned rs1:5;
unsigned op3:6;
unsigned fcn:5;
unsigned op:2;
} prefetcha;
struct {
unsigned imm13:13;
unsigned i:1;
unsigned rs1:5;
unsigned op3:6;
unsigned fcn:5;
unsigned op:2;
} prefetchai;
struct {
signed imm:13;
unsigned i:1;
unsigned rs1:5;
unsigned op3:6;
unsigned rd:5;
unsigned op:2;
} memarithi;
struct {
unsigned rs2:5;
unsigned imm_asi:8;
unsigned i:1;
unsigned rs1:5;
unsigned op3:6;
unsigned rd:5;
unsigned op:2;
} memasi;
/*
* SPIX_SPARC_ITYPE_MOVR
*/
struct {
unsigned rs2:5;
unsigned :5;
unsigned rcond:3;
unsigned i:1;
unsigned rs1:5;
unsigned op3:6;
unsigned rd:5;
unsigned op:2;
} movrr;
struct {
signed imm:10;
unsigned rcond:3;
unsigned i:1;
unsigned rs1:5;
unsigned op3:6;
unsigned rd:5;
unsigned op:2;
} movri;
/*
* SPIX_SPARC_IOP_MEMBAR
*/
struct {
unsigned mmask:4;
unsigned cmask:3;
unsigned :6;
unsigned i:1;
unsigned rs1:5;
unsigned op3:6;
unsigned rd:5;
unsigned op:2;
} membar;
/*
* SPIX_SPARC_IOP_IMPDEP1, SPIX_SPARC_IOP_IMPDEP2
*/
struct {
unsigned impdep2:19;
unsigned op3:6;
unsigned impdep1:5;
unsigned op:2;
} impdep;
/*
* SPIX_SPARC_IOP_FMADDS, SPIX_SPARC_IOP_FMADDD,
* SPIX_SPARC_IOP_FMSUBS, SPIX_SPARC_IOP_FMSUBD,
* SPIX_SPARC_IOP_FNMADDS, SPIX_SPARC_IOP_FNMADDD,
* SPIX_SPARC_IOP_FNMSUBS, SPIX_SPARC_IOP_FNMSUBD
* SPIX_SPARC_IOP_FUMADDS, SPIX_SPARC_IOP_FUMADDD,
* SPIX_SPARC_IOP_FUMSUBS, SPIX_SPARC_IOP_FUMSUBD,
* SPIX_SPARC_IOP_FUNMADDS, SPIX_SPARC_IOP_FUNMADDD,
* SPIX_SPARC_IOP_FUNMSUBS, SPIX_SPARC_IOP_FUNMSUBD
*/
struct {
unsigned rs2:5;
unsigned size:2;
unsigned var:2;
unsigned rs3:5;
unsigned rs1:5;
unsigned op3:6;
unsigned rd:5;
unsigned op:2;
} fmadd;
/*
* SPIX_SPARC_IOP_SLL, SPIX_SPARC_IOP_SLLX,
* SPIX_SPARC_IOP_SRL, SPIX_SPARC_IOP_SRLX,
* SPIX_SPARC_IOP_SRA, SPIX_SPARC_IOP_SRAX
*/
struct {
unsigned rs2:5;
unsigned :7;
unsigned x:1;
unsigned i:1;
unsigned rs1:5;
unsigned op3:6;
unsigned rd:5;
unsigned op:2;
} shiftr;
struct {
unsigned shcnt32:5;
unsigned :7;
unsigned x:1;
unsigned i:1;
unsigned rs1:5;
unsigned op3:6;
unsigned rd:5;
unsigned op:2;
} shifti32;
struct {
unsigned shcnt64:6;
unsigned :6;
unsigned x:1;
unsigned i:1;
unsigned rs1:5;
unsigned op3:6;
unsigned rd:5;
unsigned op:2;
} shifti64;
/*
* SPIX_SPARC_IOP_FCMPS, SPIX_SPARC_IOP_FCMPD, SPIX_SPARC_IOP_FCMPQ,
* SPIX_SPARC_IOP_FCMPES, SPIX_SPARC_IOP_FCMPED, SPIX_SPARC_IOP_FCMPEQ
*/
struct {
unsigned rs2:5;
unsigned opf:9;
unsigned rs1:5;
unsigned op3:6;
unsigned cc:2;
unsigned :3;
unsigned op:2;
} fcmp;
/*
* SPIX_SPARC_ITYPE_FPOP1
*/
struct {
unsigned rs2:5;
unsigned opf:9;
unsigned rs1:5;
unsigned op3:6;
unsigned rd:5;
unsigned op:2;
} fpop1;
/*
* SPIX_SPARC_IOP_SAVED, SPIX_SPARC_IOP_RESTORED,
* SPIX_SPARC_IOP_DONE, SPIX_SPARC_IOP_RETRY
*/
struct {
unsigned :19;
unsigned op3:6;
unsigned fcn:5;
unsigned op:2;
} fcn;
/*
* SPIX_SPARC_ITYPE_TRAP
*/
struct {
unsigned rs2:5;
unsigned :6;
unsigned cc:2;
unsigned i:1;
unsigned rs1:5;
unsigned op3:6;
unsigned cond:4;
unsigned :1;
unsigned op:2;
} tccr;
struct {
unsigned sw_trap:7;
unsigned :4;
unsigned cc:2;
unsigned i:1;
unsigned rs1:5;
unsigned op3:6;
unsigned cond:4;
unsigned :1;
unsigned op:2;
} tcci;
/*
* SPIX_SPARC_ITYPE_MOVCC
*/
struct {
unsigned rs2:5;
unsigned :6;
unsigned cc:2;
unsigned i:1;
unsigned cond:4;
unsigned cc2:1;
unsigned op3:6;
unsigned rd:5;
unsigned op:2;
} movccr;
struct {
signed imm:11;
unsigned cc:2;
unsigned i:1;
unsigned cond:4;
unsigned cc2:1;
unsigned op3:6;
unsigned rd:5;
unsigned op:2;
} movcci;
/*
* SPIX_SPARC_ITYPE_FMOVR
*/
struct {
unsigned rs2:5;
unsigned opf_low:5;
unsigned rcond:3;
unsigned :1;
unsigned rs1:5;
unsigned op3:6;
unsigned rd:5;
unsigned op:2;
} fmovr;
/*
* SPIX_SPARC_ITYPE_FMOVCC
*/
struct {
unsigned rs2:5;
unsigned opf_low:6;
unsigned opf_cc:3;
unsigned cond:4;
unsigned :1;
unsigned op3:6;
unsigned rd:5;
unsigned op:2;
} fmovcc;
/*
* SPIX_SPARC_ITYPE_SIAM
*/
struct {
unsigned mode:3;
unsigned :2;
unsigned opf:9;
unsigned :5;
unsigned op3:6;
unsigned :5;
unsigned op:2;
} siam;
#else
/*
* SPIX_SPARC_IOP_CALL
*/
struct {
unsigned op:2;
signed disp:30;
} call;
/*
* SPIX_SPARC_IOP_SETHI, SPIX_SPARC_IOP_NOP, SPIX_SPARC_IOP_ILLTRAP
*/
struct {
unsigned op:2;
unsigned rd:5;
unsigned op2:3;
unsigned imm:22;
} sethi;
/*
* SPIX_SPARC_ITYPE_BICC, SPIX_SPARC_ITYPE_FBFCC
*/
struct {
unsigned op:2;
unsigned a:1;
unsigned cond:4;
unsigned op2:3;
signed disp:22;
} bcc;
/*
* SPIX_SPARC_ITYPE_BPCC, SPIX_SPARC_ITYPE_FBPFCC
*/
struct {
unsigned op:2;
unsigned a:1;
unsigned cond:4;
unsigned op2:3;
unsigned cc:2;
unsigned p:1;
signed disp:19;
} bpcc;
/*
* SPIX_SPARC_ITYPE_BPR
*/
struct {
unsigned op:2;
unsigned a:1;
unsigned :1;
unsigned rcond:3;
unsigned op2:3;
unsigned disphi:2;
unsigned p:1;
unsigned rs1:5;
unsigned displo:14;
} bpr;
/*
* SPIX_SPARC_ITYPE_LOAD, SPIX_SPARC_ITYPE_USTORE,
* SPIX_SPARC_ITYPE_CSTORE
*
* SPIX_SPARC_IOP_ADD, SPIX_SPARC_IOP_ADDC, SPIX_SPARC_IOP_ADDCC,
* SPIX_SPARC_IOP_ADDCCC, SPIX_SPARC_IOP_AND, SPIX_SPARC_IOP_ANDCC,
* SPIX_SPARC_IOP_ANDN, SPIX_SPARC_IOP_ANDNCC, SPIX_SPARC_IOP_JMPL,
* SPIX_SPARC_IOP_MULSCC, SPIX_SPARC_IOP_MULX, SPIX_SPARC_IOP_OR,
* SPIX_SPARC_IOP_ORCC, SPIX_SPARC_IOP_ORN, SPIX_SPARC_IOP_ORNCC,
* SPIX_SPARC_IOP_POPC, SPIX_SPARC_IOP_PREFETCH, SPIX_SPARC_IOP_RDASI,
* SPIX_SPARC_IOP_RDASR, SPIX_SPARC_IOP_RDCCR, SPIX_SPARC_IOP_RDFPRS,
* SPIX_SPARC_IOP_RDPC, SPIX_SPARC_IOP_RDTICK, SPIX_SPARC_IOP_RDY,
* SPIX_SPARC_IOP_RESTORE, SPIX_SPARC_IOP_RETURN, SPIX_SPARC_IOP_SAVE,
* SPIX_SPARC_IOP_SDIV, SPIX_SPARC_IOP_SDIVCC, SPIX_SPARC_IOP_SDIVX,
* SPIX_SPARC_IOP_RDGSR, SPIX_SPARC_IOP_SIR, SPIX_SPARC_IOP_SMUL,
* SPIX_SPARC_IOP_SMULCC, SPIX_SPARC_IOP_SUB, SPIX_SPARC_IOP_SUBC,
* SPIX_SPARC_IOP_SUBCC, SPIX_SPARC_IOP_SUBCCC, SPIX_SPARC_IOP_TADDCC,
* SPIX_SPARC_IOP_TADDCCTV, SPIX_SPARC_IOP_TSUBCC,
* SPIX_SPARC_IOP_TSUBCCTV, SPIX_SPARC_IOP_UDIV, SPIX_SPARC_IOP_UDIVCC,
* SPIX_SPARC_IOP_UDIVX, SPIX_SPARC_IOP_UMUL, SPIX_SPARC_IOP_UMULCC,
* SPIX_SPARC_IOP_WRGSR, SPIX_SPARC_IOP_WRASI, SPIX_SPARC_IOP_WRASR,
* SPIX_SPARC_IOP_WRCCR, SPIX_SPARC_IOP_WRFPRS, SPIX_SPARC_IOP_WRY,
* SPIX_SPARC_IOP_XNOR, SPIX_SPARC_IOP_XNORCC, SPIX_SPARC_IOP_XOR,
* SPIX_SPARC_IOP_XORCC, SPIX_SPARC_IOP_FLUSHW, SPIX_SPARC_IOP_WRPR,
* SPIX_SPARC_IOP_FLUSH, SPIX_SPARC_IOP_RDPR, SPIX_SPARC_IOP_WRHPR,
* SPIX_SPARC_IOP_RDHPR
*/
struct {
unsigned op:2;
unsigned rd:5;
unsigned op3:6;
unsigned rs1:5;
unsigned i:1;
unsigned :8;
unsigned rs2:5;
} memarithr;
struct {
unsigned op:2;
unsigned fcn:5;
unsigned op3:6;
unsigned rs1:5;
unsigned i:1;
unsigned :8;
unsigned rs2:5;
} prefetch;
struct {
unsigned op:2;
unsigned fcn:5;
unsigned op3:6;
unsigned rs1:5;
unsigned i:1;
unsigned imm13:13;
} prefetchi;
struct {
unsigned op:2;
unsigned fcn:5;
unsigned op3:6;
unsigned rs1:5;
unsigned i:1;
unsigned imm_asi:8;
unsigned rs2:5;
} prefetcha;
struct {
unsigned op:2;
unsigned fcn:5;
unsigned op3:6;
unsigned rs1:5;
unsigned i:1;
unsigned imm13:13;
} prefetchai;
struct {
unsigned op:2;
unsigned rd:5;
unsigned op3:6;
unsigned rs1:5;
unsigned i:1;
signed imm:13;
} memarithi;
struct {
unsigned op:2;
unsigned rd:5;
unsigned op3:6;
unsigned rs1:5;
unsigned i:1;
unsigned imm_asi:8;
unsigned rs2:5;
} memasi;
/*
* SPIX_SPARC_ITYPE_MOVR
*/
struct {
unsigned op:2;
unsigned rd:5;
unsigned op3:6;
unsigned rs1:5;
unsigned i:1;
unsigned rcond:3;
unsigned :5;
unsigned rs2:5;
} movrr;
struct {
unsigned op:2;
unsigned rd:5;
unsigned op3:6;
unsigned rs1:5;
unsigned i:1;
unsigned rcond:3;
signed imm:10;
} movri;
/*
* SPIX_SPARC_IOP_MEMBAR
*/
struct {
unsigned op:2;
unsigned rd:5;
unsigned op3:6;
unsigned rs1:5;
unsigned i:1;
unsigned :6;
unsigned cmask:3;
unsigned mmask:4;
} membar;
/*
* SPIX_SPARC_IOP_IMPDEP1, SPIX_SPARC_IOP_IMPDEP2
*/
struct {
unsigned op:2;
unsigned impdep1:5;
unsigned op3:6;
unsigned impdep2:19;
} impdep;
/*
* SPIX_SPARC_IOP_FMADDS, SPIX_SPARC_IOP_FMADDD,
* SPIX_SPARC_IOP_FMSUBS, SPIX_SPARC_IOP_FMSUBD,
* SPIX_SPARC_IOP_FNMADDS, SPIX_SPARC_IOP_FNMADDD,
* SPIX_SPARC_IOP_FNMSUBS, SPIX_SPARC_IOP_FNMSUBD
* SPIX_SPARC_IOP_FUMADDS, SPIX_SPARC_IOP_FUMADDD,
* SPIX_SPARC_IOP_FUMSUBS, SPIX_SPARC_IOP_FUMSUBD,
* SPIX_SPARC_IOP_FUNMADDS, SPIX_SPARC_IOP_FUNMADDD,
* SPIX_SPARC_IOP_FUNMSUBS, SPIX_SPARC_IOP_FUNMSUBD
*/
struct {
unsigned op:2;
unsigned rd:5;
unsigned op3:6;
unsigned rs1:5;
unsigned rs3:5;
unsigned var:2;
unsigned size:2;
unsigned rs2:5;
} fmadd;
/*
* SPIX_SPARC_IOP_SLL, SPIX_SPARC_IOP_SLLX,
* SPIX_SPARC_IOP_SRL, SPIX_SPARC_IOP_SRLX,
* SPIX_SPARC_IOP_SRA, SPIX_SPARC_IOP_SRAX
*/
struct {
unsigned op:2;
unsigned rd:5;
unsigned op3:6;
unsigned rs1:5;
unsigned i:1;
unsigned x:1;
unsigned :7;
unsigned rs2:5;
} shiftr;
struct {
unsigned op:2;
unsigned rd:5;
unsigned op3:6;
unsigned rs1:5;
unsigned i:1;
unsigned x:1;
unsigned :7;
unsigned shcnt32:5;
} shifti32;
struct {
unsigned op:2;
unsigned rd:5;
unsigned op3:6;
unsigned rs1:5;
unsigned i:1;
unsigned x:1;
unsigned :6;
unsigned shcnt64:6;
} shifti64;
/*
* SPIX_SPARC_IOP_FCMPS, SPIX_SPARC_IOP_FCMPD, SPIX_SPARC_IOP_FCMPQ,
* SPIX_SPARC_IOP_FCMPES, SPIX_SPARC_IOP_FCMPED, SPIX_SPARC_IOP_FCMPEQ
*/
struct {
unsigned op:2;
unsigned :3;
unsigned cc:2;
unsigned op3:6;
unsigned rs1:5;
unsigned opf:9;
unsigned rs2:5;
} fcmp;
/*
* SPIX_SPARC_ITYPE_FPOP1
*/
struct {
unsigned op:2;
unsigned rd:5;
unsigned op3:6;
unsigned rs1:5;
unsigned opf:9;
unsigned rs2:5;
} fpop1;
/*
* SPIX_SPARC_IOP_SAVED, SPIX_SPARC_IOP_RESTORED,
* SPIX_SPARC_IOP_DONE, SPIX_SPARC_IOP_RETRY
*/
struct {
unsigned op:2;
unsigned fcn:5;
unsigned op3:6;
unsigned :19;
} fcn;
/*
* SPIX_SPARC_ITYPE_TRAP
*/
struct {
unsigned op:2;
unsigned :1;
unsigned cond:4;
unsigned op3:6;
unsigned rs1:5;
unsigned i:1;
unsigned cc:2;
unsigned :6;
unsigned rs2:5;
} tccr;
struct {
unsigned op:2;
unsigned :1;
unsigned cond:4;
unsigned op3:6;
unsigned rs1:5;
unsigned i:1;
unsigned cc:2;
unsigned :4;
unsigned sw_trap:7;
} tcci;
/*
* SPIX_SPARC_ITYPE_MOVCC
*/
struct {
unsigned op:2;
unsigned rd:5;
unsigned op3:6;
unsigned cc2:1;
unsigned cond:4;
unsigned i:1;
unsigned cc:2;
unsigned :6;
unsigned rs2:5;
} movccr;
struct {
unsigned op:2;
unsigned rd:5;
unsigned op3:6;
unsigned cc2:1;
unsigned cond:4;
unsigned i:1;
unsigned cc:2;
signed imm:11;
} movcci;
/*
* SPIX_SPARC_ITYPE_FMOVR
*/
struct {
unsigned op:2;
unsigned rd:5;
unsigned op3:6;
unsigned rs1:5;
unsigned :1;
unsigned rcond:3;
unsigned opf_low:5;
unsigned rs2:5;
} fmovr;
/*
* SPIX_SPARC_ITYPE_FMOVCC
*/
struct {
unsigned op:2;
unsigned rd:5;
unsigned op3:6;
unsigned :1;
unsigned cond:4;
unsigned opf_cc:3;
unsigned opf_low:6;
unsigned rs2:5;
} fmovcc;
/*
* SPIX_SPARC_ITYPE_SIAM
*/
struct {
unsigned op:2;
unsigned :5;
unsigned op3:6;
unsigned :5;
unsigned opf:9;
unsigned :2;
unsigned mode:3;
} siam;
#endif
} spix_sparc_inst_t;
/*
* SPARC architecture versions.
*/
typedef enum {
SPIX_SPARC_V8,
SPIX_SPARC_V9
} spix_sparc_ver_t;
/*
* Instruction types.
*/
typedef enum {
/*
* These correspond to the architecture independent instruction
* classifications in Shade.
*/
SPIX_SPARC_ITYPE_FP,
SPIX_SPARC_ITYPE_LOAD,
SPIX_SPARC_ITYPE_USTORE,
SPIX_SPARC_ITYPE_CSTORE,
SPIX_SPARC_ITYPE_BRANCH,
SPIX_SPARC_ITYPE_UBRANCH,
SPIX_SPARC_ITYPE_CBRANCH,
SPIX_SPARC_ITYPE_TRAP,
/*
* These are SPARC specific instruction classifications.
*/
SPIX_SPARC_ITYPE_V8,
SPIX_SPARC_ITYPE_V9,
SPIX_SPARC_ITYPE_VIS,
SPIX_SPARC_ITYPE_PRIV,
SPIX_SPARC_ITYPE_BAA,
SPIX_SPARC_ITYPE_DCTI,
SPIX_SPARC_ITYPE_USECCR,
SPIX_SPARC_ITYPE_SETCCR,
SPIX_SPARC_ITYPE_SETFCC,
SPIX_SPARC_ITYPE_MOVCC,
SPIX_SPARC_ITYPE_FMOVCC,
SPIX_SPARC_ITYPE_MOVR,
SPIX_SPARC_ITYPE_FMOVR,
SPIX_SPARC_ITYPE_BICC,
SPIX_SPARC_ITYPE_FBFCC,
SPIX_SPARC_ITYPE_BPCC,
SPIX_SPARC_ITYPE_FBPFCC,
SPIX_SPARC_ITYPE_BPR,
SPIX_SPARC_ITYPE_FPOP1,
SPIX_SPARC_ITYPE_ALU,
SPIX_SPARC_ITYPE_ILOAD,
SPIX_SPARC_ITYPE_ISTORE,
SPIX_SPARC_ITYPE_ANNUL,
SPIX_SPARC_ITYPE_PREDICTION,
SPIX_SPARC_ITYPE_PRED_TRUE,
/* SPIX EXT */
SPIX_SPARC_ITYPE_PREFETCH,
SPIX_SPARC_ITYPE_SAVE,
SPIX_SPARC_ITYPE_RESTORE,
SPIX_SPARC_NITYPE
} spix_sparc_itype_t;
/*
* Register usage, action performed.
*/
typedef enum {
SPIX_SPARC_RUACT_NONE, /* register position not used */
SPIX_SPARC_RUACT_RI, /* read int reg */
SPIX_SPARC_RUACT_R2I, /* read int reg pair */
SPIX_SPARC_RUACT_WI, /* write int reg */
SPIX_SPARC_RUACT_W2I, /* write int reg pair */
SPIX_SPARC_RUACT_RWI, /* read/write int reg */
SPIX_SPARC_RUACT_RW2I, /* read/write int reg pair */
SPIX_SPARC_RUACT_RF, /* read single FP reg */
SPIX_SPARC_RUACT_R2F, /* read double FP reg */
SPIX_SPARC_RUACT_R4F, /* read quad FP reg */
SPIX_SPARC_RUACT_WF, /* write single FP reg */
SPIX_SPARC_RUACT_W2F, /* write double FP reg */
SPIX_SPARC_RUACT_W4F, /* write quad FP reg */
SPIX_SPARC_RUACT_RWF, /* read/write single FP reg */
SPIX_SPARC_RUACT_RW2F, /* read/write double FP reg */
SPIX_SPARC_RUACT_RW4F, /* read/write quad FP reg */
SPIX_SPARC_RUACT_RS, /* read special register */
SPIX_SPARC_RUACT_WS, /* write special register */
SPIX_SPARC_RUACT_RWS /* read/write special register */
} spix_sparc_ruact_t;
/*
* Register usage, register position.
*/
typedef enum {
SPIX_SPARC_RUPOS_RS1, /* rs1 field */
SPIX_SPARC_RUPOS_RS2, /* rs2 field */
SPIX_SPARC_RUPOS_RS3, /* rs3 field (for fmadd) */
SPIX_SPARC_RUPOS_RD, /* rd field */
SPIX_SPARC_RUPOS_IMP /* implied register */
} spix_sparc_rupos_t;
/*
* Special registers.
*/
typedef enum {
SPIX_SPARC_SREG_Y, /* %y register */
SPIX_SPARC_SREG_ASI, /* %asi register */
SPIX_SPARC_SREG_CCR, /* %ccr register */
SPIX_SPARC_SREG_FPRS, /* %fprs register */
SPIX_SPARC_SREG_FCC, /* condition code fields of %fsr */
SPIX_SPARC_SREG_RM, /* rounding mode field of %fsr */
SPIX_SPARC_SREG_FSR, /* %fsr register (other than fcc or rm) */
SPIX_SPARC_SREG_TICK, /* %tick register */
SPIX_SPARC_SREG_GSR /* %gsr register */
} spix_sparc_sreg_t;
/*
* Return opcode value for instruction encoding.
*/
spix_sparc_iop_t spix_sparc_iop(spix_sparc_ver_t, const void *);
/*
* Disassemble an instruction.
*/
#ifdef SPIX_I64
size_t spix_sparc_dis(char *, size_t, spix_sparc_iop_t, const void *,
spix_addr64_t);
#endif
size_t spix_sparc_dis32(char *, size_t, spix_sparc_iop_t, const void *,
spix_addr32_t);
/*
* Return software names for register numbers.
*/
const char * spix_sparc_ireg_name(unsigned);
const char * spix_sparc_asreg_name(unsigned);
/*
* Classify instruction opcode values.
*/
spix_bool_t spix_sparc_iop_istype(spix_sparc_iop_t, spix_sparc_itype_t);
#define spix_sparc_iop_isfp(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_FP)
#define spix_sparc_iop_isload(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_LOAD)
#define spix_sparc_iop_isustore(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_USTORE)
#define spix_sparc_iop_iscstore(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_CSTORE)
#define spix_sparc_iop_isbranch(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_BRANCH)
#define spix_sparc_iop_isubranch(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_UBRANCH)
#define spix_sparc_iop_iscbranch(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_CBRANCH)
#define spix_sparc_iop_isannul(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_ANNUL)
#define spix_sparc_iop_istrap(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_TRAP)
#define spix_sparc_iop_isv8(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_V8)
#define spix_sparc_iop_isv9(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_V9)
#define spix_sparc_iop_isvis(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_VIS)
#define spix_sparc_iop_ispriv(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_PRIV)
#define spix_sparc_iop_isbaa(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_BAA)
#define spix_sparc_iop_isdcti(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_DCTI)
#define spix_sparc_iop_isuseccr(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_USECCR)
#define spix_sparc_iop_issetccr(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_SETCCR)
#define spix_sparc_iop_issetfcc(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_SETFCC)
#define spix_sparc_iop_ismovcc(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_MOVCC)
#define spix_sparc_iop_isfmovcc(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_FMOVCC)
#define spix_sparc_iop_ismovr(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_MOVR)
#define spix_sparc_iop_isfmovr(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_FMOVR)
#define spix_sparc_iop_isbicc(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_BICC)
#define spix_sparc_iop_isfbfcc(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_FBFCC)
#define spix_sparc_iop_isbpcc(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_BPCC)
#define spix_sparc_iop_isfbpfcc(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_FBPFCC)
#define spix_sparc_iop_isbpr(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_BPR)
#define spix_sparc_iop_isfpop1(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_FPOP1)
#define spix_sparc_iop_isalu(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_ALU)
#define spix_sparc_iop_isiload(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_ILOAD)
#define spix_sparc_iop_isistore(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_ISTORE)
#define spix_sparc_iop_isprediction(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_PREDICTION)
#define spix_sparc_iop_ispredtrue(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_PRED_TRUE)
#define spix_sparc_iop_isproc(iop) \
( (iop == SPIX_SPARC_IOP_CALL) || (iop == SPIX_SPARC_IOP_JMPL) || (iop == SPIX_SPARC_IOP_RETURN) )
#define spix_sparc_iop_isvalid(iop) ((unsigned) iop < SPIX_SPARC_NIOP)
#define spix_sparc_iop_isprefetch(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_PREFETCH)
#define spix_sparc_iop_issave(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_SAVE)
#define spix_sparc_iop_isrestore(iop) \
spix_sparc_iop_istype(iop, SPIX_SPARC_ITYPE_RESTORE)
/*
* Compute register usage of instruction.
*/
void spix_sparc_reguse(spix_sparc_iop_t, const void *,
void (*)(spix_sparc_ruact_t, spix_sparc_rupos_t, unsigned, void *),
void *);
/*
* Determine how an instruction uses a given register position.
*/
spix_sparc_ruact_t spix_sparc_iop_regpos(spix_sparc_iop_t,
spix_sparc_rupos_t);
/*
* Return the name of an instruction opcode.
*/
const char * spix_sparc_iop_name(spix_sparc_iop_t);
extern const size_t spix_sparc_iop_Lname;
/*
* Return the register id at a given location, or -1 if does not apply.
* iop must be the correct iop previously computed for instr using
* spix_sparc_iop()
* pos must be one of SPIX_SPARC_RUPOS_RS1, RS2, RS3 or RD
*/
int spix_sparc_regid(spix_sparc_iop_t iop, unsigned instr, spix_sparc_rupos_t pos);
/*
* Return the number of bytes of memory referenced by a load or store.
*/
size_t spix_sparc_iop_memsize(spix_sparc_iop_t);
#define spix_sparc_ofsize(of) ((of)->of_msb - (of)->of_lsb + 1)
#define spix_sparc_ofmask(of) (ofsize(of) == 32 ? 0xffffffff : \
(((1 << ofsize(of)) - 1) << (of)->of_lsb))
/*
* Field description structure
*/
typedef struct {
const char *of_name;
char of_msb;
char of_lsb;
char of_signed;
char of_pcrel;
} spix_sparc_iop_field;
/*
* Return the op_field description by its name
*/
extern const spix_sparc_iop_field* spix_sparc_get_iop_field(const char*);
/*
* Returns iop type name as a string
*/
extern const char* spix_sparc_iop_type_name(spix_sparc_itype_t);
#ifdef __cplusplus
}
#endif
#endif /*SPIX_SPARC_H*/
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