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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / lib / cpu / src / N2_Strand.h
/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: N2_Strand.h
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
#ifndef __N2_Strand_h__
#define __N2_Strand_h__
#include "SS_Strand.h"
#include "SS_Tsb.h"
#include "N2_State.h"
#include "N2_Fpu.h"
#include "N2_StoreBuffer.h"
class N2_Core;
class N2_Strand : public SS_Strand
{
public:
N2_Strand( N2_Core& core, const char* _name, uint_t sid );
static const char* n2_get_state_name( SS_Strand*, SS_Registers::Index index );
static SS_Registers::Error n2_get_state( SS_Strand*, SS_Registers::Index index, uint64_t* value );
static SS_Registers::Error n2_set_state( SS_Strand*, SS_Registers::Index index, uint64_t value );
void warm_reset(bool intp=true);
void snapshot( SS_SnapShot& ss );
N2_Core& core;
N2_Fpu fpu;
N2_Pcr pcr;
N2_Pic pic;
N2_CoreIntrId core_intr_id;
N2_CoreId core_id;
N2_Context primary_context[2];
N2_Context secondary_context[2];
N2_TagTarget inst_tag_target;
N2_TagAccess inst_tag_access;
N2_TagTarget data_tag_target;
N2_TagAccess data_tag_access;
N2_PartitionId partition_id;
N2_RealRange real_range[4];
N2_PhysicalOffset physical_offset[4];
N2_TsbConfig nucleus_tsb_config[4];
N2_TsbConfig non_nucleus_tsb_config[4];
N2_TsbPointer inst_tsb_pointer[4];
N2_TsbPointer data_tsb_pointer[4];
N2_HwtwConfig hwtw_config;
N2_TwControl tw_control;
N2_InstSfsr inst_sfsr;
N2_DataSfsr data_sfsr;
N2_DataSfar data_sfar;
N2_DataWp data_wp;
N2_IntrQueuePtr cpu_mondo_head;
N2_IntrQueuePtr cpu_mondo_tail;
N2_IntrQueuePtr dev_mondo_head;
N2_IntrQueuePtr dev_mondo_tail;
N2_IntrQueuePtr resumable_head;
N2_IntrQueuePtr resumable_tail;
N2_IntrQueuePtr non_resumable_head;
N2_IntrQueuePtr non_resumable_tail;
uint64_t intr_recv;
N2_IntrR intr_r;
N2_Seter seter;
N2_Desr desr;
uint64_t tw_status; // 1 when this strand is doing hwtw, 0 otherwise
BL_EccBits frf_ecc[64]; // Ecc values for FRF RAS
BL_EccBits sp_ecc[8]; // Ecc values for Scratchpad Registers
// Ecc values for Tick Compare Array 00-Tick Cmpr 01 - Stick Cmpr 10 - Hstick Cmpr
BL_EccBits tick_cmpr_array_ecc[N2_TickAccess::TICK_ACCESS_MAX];
void inst_tag_update( uint_t context, SS_Vaddr va );
void data_tag_update( uint_t context, SS_Vaddr va );
// Store Buffer RAS support
N2_StoreBuffer stb;
SS_Trap::Type fill_store_buffer_mem(const MemoryTransaction &memXact);
SS_Trap::Type fill_store_buffer_asi(uint64_t addr, uint8_t asi,uint64_t data);
SS_Trap::Type check_store_buffer_RAWtrap(const MemoryTransaction &memXact);
SS_Trap::Type flush_store_buffer();
protected:
static SS_AsiSpace::Error tsb_config_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
static SS_AsiSpace::Error tsb_ra2pa_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
static SS_AsiSpace::Error tag_access_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
static SS_AsiSpace::Error tlb_data_in_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
static SS_AsiSpace::Error tlb_data_access_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
static SS_AsiSpace::Error tlb_data_access_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
static SS_AsiSpace::Error tlb_tag_read_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
static SS_AsiSpace::Error inst_tlb_demap_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
static SS_AsiSpace::Error data_tlb_demap_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
static SS_AsiSpace::Error partition_id_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
static SS_AsiSpace::Error pri_ctx_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
static SS_AsiSpace::Error sec_ctx_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
static SS_AsiSpace::Error n2_lsu_ctr_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
static SS_AsiSpace::Error data_wp_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
static SS_AsiSpace::Error inst_tlb_probe_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
static SS_AsiSpace::Error intr_queue_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
static SS_AsiSpace::Error intr_queue_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
static SS_AsiSpace::Error intr_recv_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
static SS_AsiSpace::Error intr_recv_wr64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
static SS_AsiSpace::Error intr_recv_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
static SS_AsiSpace::Error intr_r_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
static SS_AsiSpace::Error desr_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
static SS_AsiSpace::Error stb_access_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
static SS_AsiSpace::Error irf_ecc_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
static SS_AsiSpace::Error frf_ecc_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
static SS_AsiSpace::Error tsa_access_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
static SS_AsiSpace::Error mra_access_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
static SS_AsiSpace::Error tick_access_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
static SS_AsiSpace::Error scratchpad_access_ld64( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
static SS_AsiSpace::Error n2_scratchpad_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* data );
static SS_AsiSpace::Error n2_scratchpad_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
static SS_AsiSpace::Error tw_control_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t data );
static SS_Vaddr n2_trap( SS_Vaddr pc, SS_Vaddr npc, SS_Strand* s, SS_Instr* i, SS_Trap::Type tt );
static SS_Vaddr n2_inst_mmu_va( SS_Vaddr pc, SS_Vaddr npc, SS_Strand* s, SS_Instr* i, SS_InstrCache::Tag* );
static SS_Vaddr n2_inst_mmu_ra( SS_Vaddr pc, SS_Vaddr npc, SS_Strand* s, SS_Instr* i, SS_InstrCache::Tag* );
static SS_Vaddr n2_inst_mmu_pa( SS_Vaddr pc, SS_Vaddr npc, SS_Strand* s, SS_Instr* i, SS_InstrCache::Tag* );
static SS_Vaddr n2_data_mmu( SS_Vaddr pc, SS_Vaddr npc, SS_Strand* s, SS_Instr* i, SS_Vaddr va, uint_t mem );
static SS_Vaddr n2_inst_trap( SS_Vaddr pc, SS_Vaddr npc, SS_Strand* s, SS_Instr* i, SS_Vaddr va, SS_Trap::Type tt );
static SS_Vaddr n2_data_trap( SS_Vaddr pc, SS_Vaddr npc, SS_Strand* s, SS_Instr* i, SS_Vaddr va, SS_Trap::Type tt );
static SS_Vaddr n2_invalid_asi( SS_Vaddr pc, SS_Vaddr npc, SS_Strand* s, SS_Instr* i, SS_Vaddr );
static void n2_run_perf( SS_Strand* s, Sam::Vcpu::perfcntr which, int64_t incr );
static void n2_external_interrupt( SS_Strand*, uint64_t*, bool raise );
static void n2_internal_interrupt( SS_Strand*, uint_t vector, bool raise );
void intr_update();
SS_Tte* n2_inst_htw( SS_Vaddr va, SS_Context ctxt0, SS_Context ctxt1 );
SS_Tte* n2_data_htw( SS_Vaddr va, SS_Context ctxt0, SS_Context ctxt1 );
SS_TsbConfig tsb_config[8];
SS_TsbRaToPa tsb_ra2pa[4];
N2_TsbTteTag tsb_tte_tag;
N2_TsbTteData tsb_tte_data;
SS_Trap::Type trap_htw; // The trap htw caused if returned TTE == 0
SS_Trap::Type trap_dae_inv_asi; // When rd/wrasi causes a trap other then dae_inv_asi throw this.
int_t tlb_entry; // Pli command for HWTW and TLBWRITE forces TLB entry to be used
SS_Paddr data_wp_pa_mask;
SS_Paddr data_wp_pa_addr;
SS_Vaddr data_wp_va_mask;
SS_Vaddr data_wp_va_addr;
uint8_t data_wp_bytes; // Which bytes to check for match address
uint8_t data_wp_flags; // Read and/or write flags to check
uint8_t data_wp_check; // Set to non zero to disable TTE caching
bool va_watchpoint_hit( SS_Instr* i, SS_Vaddr va )
{
return ((va & data_wp_va_mask) == data_wp_va_addr) // Match address
&& (((~uint64_t(0) >> (64 - i->len)) << (va & 7)) & data_wp_bytes) // Match byte mask
&& (i->flg & data_wp_flags) // Match read or write
&& (sim_state.priv() != SS_HPRV); // Only in user or priv mode
}
bool pa_watchpoint_hit( SS_Instr* i, SS_Paddr pa )
{
return ((pa & data_wp_pa_mask) == data_wp_pa_addr) // Match address
&& (((~uint64_t(0) >> (64 - i->len)) << (pa & 7)) & data_wp_bytes) // Match byte mask
&& (i->flg & data_wp_flags); // Match read or write
}
static Sam::Vcpu::TranslateError n2_cnv2pa( SS_Strand* s, Sam::Vcpu::TranslateMode, SS_Vaddr, uint64_t ctx, uint64_t pid, SS_Paddr* pa );
static SS_Execute v8_run_exe_table[];
static SS_Execute run_exe_table[];
static SS_Execute trc_exe_table[];
static SS_Memop mem_run_table[][4];
static SS_Memop mem_trc_table[][4];
static SS_Memop mem_ras_table[][4];
static SS_DecodeTable run_dec_xx_xxxxxx;
static void n2_ras_enable( SS_Strand*, char* );
#ifdef COMPILE_FOR_COSIM
static SS_Trap::Type n2_inst_hwtw( SS_Strand* strand, SS_Vaddr va, int_t entry );
static SS_Trap::Type n2_data_hwtw( SS_Strand* strand, SS_Vaddr va, uint8_t asi, int_t entry );
#endif
};
#endif
Full OpenSPARC architecture tarball including simulator, hypervisor, and OBP.