Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / lib / ras / xml / N2_DramErrorStatusMem.xml

<!-- interpreter=xml2reg args='-t' -->
<register_list>
<register name="DRAM_ERROR_STATUS_REG (DRAM_ERROR_STATUS_REG)">
   <class_name>N2_DramErrorStatusMem</class_name>
   <submodule>N2</submodule>
   <comment>
DRAM Error Status Register. This register contains status on DRAM errors. The status bits in this register are cleared by writing a 1 to the bit position. The error register is not cleared on reset so software can examine its contents after an error-induced reset. Note - Since this register is not cleared on reset, after a power-on reset the contents of this register are undefined, and the bits could be in an illegal state that could not possibly be generated by any error combination (e.g. MEU bit set with all other bits cleared). Operation while in this illegal state leads to undefined behavior for the register, so software should always clear this register after a power-on reset. TABLE 12-31 shows the format of the DRAM Error Status Register. TABLE 12-31 Register64 DRAM Error Status Register - DRAM_ERROR_STATUS_REG (0x84-0000-0280) (Count 4 Step 4096)
   </comment>
   <base_address>0x8400000280ULL</base_address>
   <count>4</count>
   <stride>4096</stride>
   <priv>yes</priv>
   <field name="SYND">
       <start_offset>0</start_offset>
       <end_offset>15</end_offset>
       <initial_value>0</initial_value>
       <protection>RW</protection>
       <field_type>NORMAL</field_type>
       <comment>
ECC syndrome.
       </comment>
       <format type="hex"/>
   </field>
   <field name="RSVD0">
       <start_offset>16</start_offset>
       <end_offset>53</end_offset>
       <initial_value>0</initial_value>
       <protection>RO</protection>
       <field_type>ZERO</field_type>
       <comment>
Reserved
       </comment>
   </field>
   <field name="FBR">
       <start_offset>54</start_offset>
       <end_offset>54</end_offset>
       <initial_value>0</initial_value>
       <protection>RW1C</protection>
       <field_type>NORMAL</field_type>
       <comment>
Set to 1 if the error was a FBDIMM channel recoverable error.
       </comment>
       <format type="hex"/>
   </field>
   <field name="FBU">
       <start_offset>55</start_offset>
       <end_offset>55</end_offset>
       <initial_value>0</initial_value>
       <protection>RW1C</protection>
       <field_type>NORMAL</field_type>
       <comment>
Set to 1 if the error was a FBDIMM channel unrecoverable error.
       </comment>
       <format type="hex"/>
   </field>
   <field name="MEB">
       <start_offset>56</start_offset>
       <end_offset>56</end_offset>
       <initial_value>0</initial_value>
       <protection>RW1C</protection>
       <field_type>NORMAL</field_type>
       <comment>
Set to 1 if there were multiple out-of-bounds errors.
       </comment>
       <format type="hex"/>
   </field>
   <field name="DBU">
       <start_offset>57</start_offset>
       <end_offset>57</end_offset>
       <initial_value>0</initial_value>
       <protection>RW1C</protection>
       <field_type>NORMAL</field_type>
       <comment>
Set to 1 if the error was an access to a nonexistent DRAM address (address out of bounds).
       </comment>
       <format type="hex"/>
   </field>
   <field name="DSU">
       <start_offset>58</start_offset>
       <end_offset>58</end_offset>
       <initial_value>0</initial_value>
       <protection>RW1C</protection>
       <field_type>NORMAL</field_type>
       <comment>
Set to 1 if the error was a DRAM scrub uncorrectable error.
       </comment>
       <format type="hex"/>
   </field>
   <field name="DSC">
       <start_offset>59</start_offset>
       <end_offset>59</end_offset>
       <initial_value>0</initial_value>
       <protection>RW1C</protection>
       <field_type>NORMAL</field_type>
       <comment>
Set to 1 if the error was a DRAM scrub correctable error.
       </comment>
       <format type="hex"/>
   </field>
   <field name="DAU">
       <start_offset>60</start_offset>
       <end_offset>60</end_offset>
       <initial_value>0</initial_value>
       <protection>RW1C</protection>
       <field_type>NORMAL</field_type>
       <comment>
Set to 1 if the error was a DRAM access uncorrectable error.
       </comment>
       <format type="hex"/>
   </field>
   <field name="DAC">
       <start_offset>61</start_offset>
       <end_offset>61</end_offset>
       <initial_value>0</initial_value>
       <protection>RW1C</protection>
       <field_type>NORMAL</field_type>
       <comment>
Set to 1 if the error was a DRAM access correctable error.
       </comment>
       <format type="hex"/>
   </field>
   <field name="MEC">
       <start_offset>62</start_offset>
       <end_offset>62</end_offset>
       <initial_value>0</initial_value>
       <protection>RW1C</protection>
       <field_type>NORMAL</field_type>
       <comment>
Multiple corrected errors, one or more corrected errors were not logged.
       </comment>
       <format type="hex"/>
   </field>
   <field name="MEU">
       <start_offset>63</start_offset>
       <end_offset>63</end_offset>
       <initial_value>0</initial_value>
       <protection>RW1C</protection>
       <field_type>NORMAL</field_type>
       <comment>
Multiple uncorrected errors, one or more uncorrected errors were not logged.
       </comment>
       <format type="hex"/>
   </field>
</register>
</register_list>