<!-- interpreter=xml2reg args='-t' -->
<register name=
"DRAM_FBD_COUNT_REG (DRAM_FBD_COUNT_REG)">
<class_name>N2_DramFbdCountReg
</class_name>
<submodule>N2
</submodule>
DRAM FBD Count Register. This register controls the sending of FDB
Recoverable interrupts to the NCU.
TABLE
12-
39 shows the format of the DRAM FDB Count
Register. TABLE
12-
39 FBD Count Register - DRAM_FBD_COUNT_REG (
0x84-
0000-
0c10) (Count
4 Step
4096)
<base_address>0x8400000c10ULL
</base_address>
<start_offset>17</start_offset>
<end_offset>63</end_offset>
<initial_value>0</initial_value>
<protection>RO
</protection>
<field_type>ZERO
</field_type>
<start_offset>16</start_offset>
<end_offset>16</end_offset>
<initial_value>0</initial_value>
<protection>RW
</protection>
<field_type>NORMAL
</field_type>
If set, the MCU will generate an interrupt to the NCU on every FBR error.
<start_offset>0</start_offset>
<end_offset>15</end_offset>
<initial_value>0</initial_value>
<protection>RW
</protection>
<field_type>NORMAL
</field_type>
Count of FBR errors, decremented on every FBR error if COUNTONE is not
set. When this value decrements from
1 to
0, an FBR interrupt will be