<!-- interpreter=xml2reg args='-t' -->
<register name=
"DRAM_FBD_ERROR_SYND_REG (DRAM_FBD_ERROR_SYND_REG)">
<class_name>N2_DramFbdErrorSyndromeReg
</class_name>
<submodule>N2
</submodule>
DRAM FBD Error Syndrome Register. Each DRAM channel has an FBD Error
Syndrome for FBD link errors. When an FBD link error is detected, the
syndrome is captured in this register and for a recoverable
(unrecoverable) link error, the corresponding MCU[
0-
3]FBR
(MCU[
0-
3]FBU) bit is set in th SOC_ERROR_STATUS_REG described in
Section
12.24., which if enabled will generate a sw_recoverable_error
trap ito the lowest enabled strand in the ASI_CORE_ENABLE_STATUS
register. Once the valid bit is set, no further FBD link errors are
logged, so software will need to clear the valid bit to enable further
FBD link error detection.
TABLE
12-
37 shows the format of the DRAM FBD Error Syndrome
Register. TABLE
12-
37 DRAM FBD Error Syndrome Register - DRAM_FBD_ERROR_SYND_REG (
0x84-
0000-
0c00) (Count
4 Step
4096)
<base_address>0x8400000c00ULL
</base_address>
<start_offset>63</start_offset>
<end_offset>63</end_offset>
<initial_value>0</initial_value>
<protection>RW
</protection>
<field_type>NORMAL
</field_type>
<start_offset>30</start_offset>
<end_offset>62</end_offset>
<initial_value>0</initial_value>
<protection>RO
</protection>
<field_type>ZERO
</field_type>
<start_offset>18</start_offset>
<end_offset>29</end_offset>
<initial_value>0</initial_value>
<protection>RW
</protection>
<field_type>NORMAL
</field_type>
AMB alert bits set in Channel
1.
<start_offset>6</start_offset>
<end_offset>17</end_offset>
<initial_value>0</initial_value>
<protection>RW
</protection>
<field_type>NORMAL
</field_type>
AMB alert bits set in Channel
0.
<start_offset>5</start_offset>
<end_offset>5</end_offset>
<initial_value>0</initial_value>
<protection>RW
</protection>
<field_type>NORMAL
</field_type>
MCU issued a Soft channel reset command to the channel.
<start_offset>4</start_offset>
<end_offset>4</end_offset>
<initial_value>0</initial_value>
<protection>RW
</protection>
<field_type>NORMAL
</field_type>
MCU issued a fast reset of a channel due to a soft channel reset for
the error not being effective.
<start_offset>3</start_offset>
<end_offset>3</end_offset>
<initial_value>0</initial_value>
<protection>RW
</protection>
<field_type>NORMAL
</field_type>
Status Frame Parity Error.
<start_offset>2</start_offset>
<end_offset>2</end_offset>
<initial_value>0</initial_value>
<protection>RW
</protection>
<field_type>NORMAL
</field_type>
<start_offset>1</start_offset>
<end_offset>1</end_offset>
<initial_value>0</initial_value>
<protection>RW
</protection>
<field_type>NORMAL
</field_type>
<start_offset>0</start_offset>
<end_offset>0</end_offset>
<initial_value>0</initial_value>
<protection>RW
</protection>
<field_type>NORMAL
</field_type>