<!-- interpreter=xml2reg args='-t' -->
<register name=
"L2_ADDRESSING_FIELDS (L2_ADDRESSING_FIELDS)">
<class_name>N2_L2AddressingFields
</class_name>
<submodule>N2
</submodule>
This class is based on N2 PRM
1.1 Table B-
4 and splits a virtual
address into the bit fields needed to index the L2 cache. This class
<start_offset>0</start_offset>
<end_offset>2</end_offset>
<initial_value>0</initial_value>
<protection>RO
</protection>
<field_type>ZERO
</field_type>
All zero for
64-bit access.
<start_offset>3</start_offset>
<end_offset>5</end_offset>
<initial_value>0</initial_value>
<protection>RW
</protection>
<field_type>NORMAL
</field_type>
Selects
64-bit (doubleword) in cache line. See PRM Rev
1.1 Tbl.
28-
43
<start_offset>6</start_offset>
<end_offset>8</end_offset>
<initial_value>0</initial_value>
<protection>RW
</protection>
<field_type>NORMAL
</field_type>
Selects bank containing the cache line.
<start_offset>9</start_offset>
<end_offset>17</end_offset>
<initial_value>0</initial_value>
<protection>RW
</protection>
<field_type>NORMAL
</field_type>
Selects cache set containing the cache line. Assumes L2 cache
<start_offset>18</start_offset>
<end_offset>39</end_offset>
<initial_value>0</initial_value>
<protection>RW
</protection>
<field_type>NORMAL
</field_type>