<!-- interpreter=xml2reg args='-t' -->
<register name=
"L2_CACHE_FLUSHING_ADDRESSING_FIELDS (L2_CACHE_FLUSHING_ADDRESSING_FIELDS)">
<class_name>N2_L2CacheFlushAddrFields
</class_name>
<submodule>N2
</submodule>
This class is based on N2 PRM
1.1 Table
28-
41 and splits a virtual
address into the bit fields needed for the prefetchICE instruction. This class
bool checkKey() { return getKEY() ==
0x3; }
<start_offset>0</start_offset>
<end_offset>5</end_offset>
<initial_value>0</initial_value>
<protection>RO
</protection>
<field_type>ZERO
</field_type>
All zero for
64-bit access.
<start_offset>6</start_offset>
<end_offset>8</end_offset>
<initial_value>0</initial_value>
<protection>RW
</protection>
<field_type>NORMAL
</field_type>
Selects bank containing the cache line.
<start_offset>9</start_offset>
<end_offset>17</end_offset>
<initial_value>0</initial_value>
<protection>RW
</protection>
<field_type>NORMAL
</field_type>
Selects cache set containing the cache line. Assumes L2 cache
<start_offset>18</start_offset>
<end_offset>21</end_offset>
<initial_value>0</initial_value>
<protection>RW
</protection>
<field_type>NORMAL
</field_type>
Selects way in cache set.
<start_offset>22</start_offset>
<end_offset>36</end_offset>
<initial_value>0</initial_value>
<protection>RO
</protection>
<field_type>ZERO
</field_type>
<start_offset>37</start_offset>
<end_offset>39</end_offset>
<initial_value>0x3</initial_value>
<protection>RW
</protection>
<field_type>NORMAL
</field_type>
Must be
011, i.e.
0x3. Use of any other value places Niagara II in an
<start_offset>40</start_offset>
<end_offset>63</end_offset>
<initial_value>0</initial_value>
<protection>RO
</protection>
<field_type>ZERO
</field_type>