Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / lib / ras / xml / N2_L2DiagVdMem.xml
<!-- interpreter=xml2reg args='-t' -->
<register_list>
<register name="L2_DIAG_VD (L2_DIAG_VD)">
<class_name>N2_L2DiagVdMem</class_name>
<submodule>N2</submodule>
<comment>
Diagnostic access to the L2 VUAD array is done through a pair of address access ranges. The first accesses the valid and dirty bits for an entire set plus the parity for each of those bits across the set via 64 bit read/writes. Diag loads of the VUAD do not check parity, and thus cannot generate a parity error. L2 Diagnostic VD - L2_DIAG_VD (0xA6-0040-0000) (count 4096 step 64)
</comment>
<base_address>0xA600400000ULL</base_address>
<count>4096</count>
<stride>64</stride>
<priv>yes</priv>
<field name="DIRTY">
<start_offset>0</start_offset>
<end_offset>15</end_offset>
<initial_value>0</initial_value>
<protection>RW</protection>
<field_type>NORMAL</field_type>
<comment>
Dirty bits for way 15 down to way 0.
</comment>
<format type="hex"/>
</field>
<field name="VALID">
<start_offset>16</start_offset>
<end_offset>31</end_offset>
<initial_value>0</initial_value>
<protection>RW</protection>
<field_type>NORMAL</field_type>
<comment>
Valid bits for way 15 down to way 0.
</comment>
<format type="hex"/>
</field>
<field name="VDECC">
<start_offset>32</start_offset>
<end_offset>38</end_offset>
<initial_value>0</initial_value>
<protection>RW</protection>
<field_type>NORMAL</field_type>
<comment>
ECC for all dirty and valid bits.
</comment>
<format type="hex"/>
</field>
<field name="RSVD0">
<start_offset>39</start_offset>
<end_offset>63</end_offset>
<initial_value>0</initial_value>
<protection>RO</protection>
<field_type>ZERO</field_type>
<comment>
Reserved
</comment>
</field>
</register>
</register_list>