Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / lib / ras / xml / N2_L2NotdataErrorReg.xml

<!-- interpreter=xml2reg args='-t' -->
<register_list>
<register name="L2_NOTDATA_ERROR_REG (L2_NOTDATA_ERROR_REG)">
   <class_name>N2_L2NotdataErrorReg</class_name>
   <submodule>N2</submodule>
   <comment>
Each L2 bank has a NotData error register which contains the status and address for the L2 NotData error within that bank. The error register is not cleared on reset so software can examine its contents after an error-induced reset. The L2 NotData Error Register is available at address 0xAE-0000-0000 and 0xBE-0000-0000. Address bits 8:6 select the cache bank, address bits 31:9 and 5:3 are ignored (i.e. the register aliases across the address range). TABLE 12-27 shows the format of the L2 NotData Error Register. TABLE 12-27 Register64 L2 NotData Error Register - L2_NOTDATA_ERROR_REG (0xAE-0000-0000) (Count 8 Step 64)
   </comment>
   <priv>yes</priv>
   <base_address>0xAE00000000ULL</base_address>
   <count>8</count>
   <stride>64</stride>
   <field name="RSVD0">
       <start_offset>0</start_offset>
       <end_offset>3</end_offset>
       <initial_value>0x0</initial_value>
       <protection>RO</protection>
       <field_type>ZERO</field_type>
       <comment>
Reserved. warm-reset=0
       </comment>
   </field>
   <field name="ADDRESS">
       <start_offset>4</start_offset>
       <end_offset>39</end_offset>
       <initial_value>0x0</initial_value>
       <protection>RW</protection>
       <field_type>NORMAL</field_type>
       <comment>
Preserved. warm-reset=X
       </comment>
       <format type="hex"/>
   </field>
   <field name="VCID">
       <start_offset>40</start_offset>
       <end_offset>45</end_offset>
       <initial_value>0x0</initial_value>
       <protection>RW</protection>
       <field_type>NORMAL</field_type>
       <comment>
Preserved. warm-reset=X
       </comment>
       <format type="hex"/>
   </field>
   <field name="RSVD1">
       <start_offset>46</start_offset>
       <end_offset>47</end_offset>
       <initial_value>0x0</initial_value>
       <protection>RO</protection>
       <field_type>ZERO</field_type>
       <comment>
Reserved. warm-reset=0
       </comment>
   </field>
   <field name="NDDM">
       <start_offset>48</start_offset>
       <end_offset>48</end_offset>
       <initial_value>0x0</initial_value>
       <protection>RW1C</protection>
       <field_type>NORMAL</field_type>
       <comment>
Preserved. warm-reset=X
       </comment>
       <format type="hex"/>
   </field>
   <field name="NDSP">
       <start_offset>49</start_offset>
       <end_offset>49</end_offset>
       <initial_value>0x0</initial_value>
       <protection>RW1C</protection>
       <field_type>NORMAL</field_type>
       <comment>
Preserved. warm-reset=X
       </comment>
       <format type="hex"/>
   </field>
   <field name="RW">
       <start_offset>50</start_offset>
       <end_offset>50</end_offset>
       <initial_value>0x0</initial_value>
       <protection>RW</protection>
       <field_type>NORMAL</field_type>
       <comment>
Preserved. warm-reset=X
       </comment>
       <format type="hex"/>
   </field>
   <field name="MEND">
       <start_offset>51</start_offset>
       <end_offset>51</end_offset>
       <initial_value>0x0</initial_value>
       <protection>RW1C</protection>
       <field_type>NORMAL</field_type>
       <comment>
Preserved. warm-reset=X
       </comment>
       <format type="hex"/>
   </field>
   <field name="RSVD2">
       <start_offset>52</start_offset>
       <end_offset>63</end_offset>
       <initial_value>0x0</initial_value>
       <protection>RO</protection>
       <field_type>ZERO</field_type>
       <comment>
Reserved. warm-reset=0
       </comment>
   </field>
</register>
</register_list>