sam-t2/sam/cpus/vonk/ss/api/pli/tst/diag.conf

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: diag.conf
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: diag.conf
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
OBJECT sim TYPE sim {
        cpu_switch_time: 1
        time_model: "on"
        continue_disabled: 0

        instruction_profile_mode: instruction-cache-access-trace
        instruction_profile_line_size: 4

}
OBJECT memory_ciop TYPE ram {
        image: memory_ciop_image
}
OBJECT memory_ciop_image TYPE image {
        size: 0x7f00000000
        queue: th00
}
OBJECT swvmem0 TYPE swerver-memory {

        irq: irq0


        snoop: 0


        tso_checker: 1
        debug_level: 0

        queue: th00
}


OBJECT irqbus0 TYPE sparc-irq-bus {
}


OBJECT irq0 TYPE swerver-interrupt {
        thread_base: 0
        need_ssi: 1
        queue: th00
}


OBJECT swvp0 TYPE swerver-processor {
        thread0: th00
        thread1: th01
        thread2: th02
        thread3: th03
        thread4: th04
        thread5: th05
        thread6: th06
        thread7: th07
        mmu:swmmu0
}
OBJECT swmmu0 TYPE swerver-proc-mmu {
}

OBJECT th00 TYPE niagara2 {
        freq_mhz: 800
        mmu: stmmu00
        max-trap-levels: 6
        va_bits: 48
        physical_memory: phys_mem0
        control_registers: (("mid", 0))
        irq_bus: irqbus0
        thread_id: 0
        other_threads: (th01, th02, th03, th04, th05, th06, th07)
        queue: th00

        extra_irq_enable: 0

}

OBJECT stmmu00 TYPE swerver-thread-mmu {
        thread-status: 1
        full-swerver-decode: 1
        niagara-mmu: 1
        disable-sun4u-interrupts: 1
        intr_trap_type: 0x60
        stream_cmpl_trap_type: 0x70
        ma_cmpl_trap_type: 0x74
        model-real-sfar: 1


        ignore_asi_0x73: 1
        match_rtl: 1


}

OBJECT th01 TYPE niagara2 {
        freq_mhz: 800
        mmu: stmmu01
        max-trap-levels: 6
        va_bits: 48
        physical_memory: phys_mem0
        control_registers: (("mid", 1))
        irq_bus: irqbus0
        queue: th01
        thread_id: 1
        other_threads: (
                        th00,
                        th02,
                        th03,
                        th04,
                        th05,
                        th06,
                        th07
                       )

        extra_irq_enable: 0

}

OBJECT stmmu01 TYPE swerver-thread-mmu {
        full-swerver-decode: 1
        niagara-mmu: 1
        disable-sun4u-interrupts: 1
        model-real-sfar: 1
}

OBJECT th02 TYPE niagara2 {
        freq_mhz: 800
        mmu: stmmu02
        max-trap-levels: 6
        va_bits: 48
        physical_memory: phys_mem0
        control_registers: (("mid", 2))
        irq_bus: irqbus0
        queue: th02
        thread_id: 2
        other_threads: (
                        th00,
                        th01,
                        th03,
                        th04,
                        th05,
                        th06,
                        th07
                       )

        extra_irq_enable: 0

}

OBJECT stmmu02 TYPE swerver-thread-mmu {
        full-swerver-decode: 1
        niagara-mmu: 1
        disable-sun4u-interrupts: 1
        model-real-sfar: 1
}

OBJECT th03 TYPE niagara2 {
        freq_mhz: 800
        mmu: stmmu03
        max-trap-levels: 6
        va_bits: 48
        physical_memory: phys_mem0
        control_registers: (("mid", 3))
        irq_bus: irqbus0
        queue: th03
        thread_id: 3
        other_threads: (
                        th00,
                        th01,
                        th02,
                        th04,
                        th05,
                        th06,
                        th07
                       )

        extra_irq_enable: 0

}

OBJECT stmmu03 TYPE swerver-thread-mmu {
        full-swerver-decode: 1
        niagara-mmu: 1
        disable-sun4u-interrupts: 1
        model-real-sfar: 1
}

OBJECT th04 TYPE niagara2 {
        freq_mhz: 800
        mmu: stmmu04
        max-trap-levels: 6
        va_bits: 48
        physical_memory: phys_mem0
        control_registers: (("mid", 4))
        irq_bus: irqbus0
        queue: th04
        thread_id: 4
        other_threads: (
                        th00,
                        th01,
                        th02,
                        th03,
                        th05,
                        th06,
                        th07
                       )

        extra_irq_enable: 0

}

OBJECT stmmu04 TYPE swerver-thread-mmu {
        full-swerver-decode: 1
        niagara-mmu: 1
        disable-sun4u-interrupts: 1
        model-real-sfar: 1
}

OBJECT th05 TYPE niagara2 {
        freq_mhz: 800
        mmu: stmmu05
        max-trap-levels: 6
        va_bits: 48
        physical_memory: phys_mem0
        control_registers: (("mid", 5))
        irq_bus: irqbus0
        queue: th05
        thread_id: 5
        other_threads: (
                        th00,
                        th01,
                        th02,
                        th03,
                        th04,
                        th06,
                        th07
                       )

        extra_irq_enable: 0

}

OBJECT stmmu05 TYPE swerver-thread-mmu {
        full-swerver-decode: 1
        niagara-mmu: 1
        disable-sun4u-interrupts: 1
        model-real-sfar: 1
}

OBJECT th06 TYPE niagara2 {
        freq_mhz: 800
        mmu: stmmu06
        max-trap-levels: 6
        va_bits: 48
        physical_memory: phys_mem0
        control_registers: (("mid", 6))
        irq_bus: irqbus0
        queue: th06
        thread_id: 6
        other_threads: (
                        th00,
                        th01,
                        th02,
                        th03,
                        th04,
                        th05,
                        th07
                       )

        extra_irq_enable: 0

}

OBJECT stmmu06 TYPE swerver-thread-mmu {
        full-swerver-decode: 1
        niagara-mmu: 1
        disable-sun4u-interrupts: 1
        model-real-sfar: 1
}

OBJECT th07 TYPE niagara2 {
        freq_mhz: 800
        mmu: stmmu07
        max-trap-levels: 6
        va_bits: 48
        physical_memory: phys_mem0
        control_registers: (("mid", 7))
        irq_bus: irqbus0
        queue: th07
        thread_id: 7
        other_threads: (
                        th00,
                        th01,
                        th02,
                        th03,
                        th04,
                        th05,
                        th06
                       )

        extra_irq_enable: 0

}

OBJECT stmmu07 TYPE swerver-thread-mmu {
        full-swerver-decode: 1
        niagara-mmu: 1
        disable-sun4u-interrupts: 1
        model-real-sfar: 1
}

OBJECT phys_mem0 TYPE memory-space {
        map: (
              (0x00000000000, memory_cache, 0x0, 0, 0x2000000000),
              (0x08000000000, memory_ciop, 0x0, 0, 0x7f00000000),

              (0x0ff00000000, memory0, 0x0, 0, 0x100000000))


        timing_model: swvmem0
        snoop_device: swvmem0

}

OBJECT memory0 TYPE ram {
        image: memory0_image
}

OBJECT memory0_image TYPE image {
        size: 0x100000000
        queue: th00
}

OBJECT memory_cache TYPE ram {
        image: memory_cache_image
}

OBJECT memory_cache_image TYPE image {
        size: 0x2000000000
        queue: th00
}


OBJECT socket0 TYPE pli-socket {

        force_pc: 1


        int_model: 1


        mem_model: 1


        cmd_intf: 1


        replay_log: 0
        socket: 13028
        open: 1


        close: 0
        test: 0


        pli_log: 0


        reg_cmp: 1


        debug_level: 1


        tlb_sync: 1


        tlb_debug: 0
        show_trap: 0


        enable_ras: 0

}